8M x 8-Bit Dynamic RAM HYB 3164805AJ/AT(L) -40/-50/-60 HYB 3165805AJ/AT(L) -40/-50/-60 (4k & 8k Refresh, EDO-Version) Advanced Information • 8 388 608 words by 8-bit organization • 0 to 70 °C operating temperature • Hyper Page Mode - EDO - operation • Performance: -40 -50 -60 tRAC RAS access time 40 50 60 ns tCAC CAS access time 10 13 15 ns tAA Access time from address 20 25 30 ns tRC Read/write cycle time 69 84 104 ns tHPC Hyper page mode (EDO) cycle time 16 20 25 ns • Single + 3.3 V (± 0.3V) power supply • Low power dissipation: max. 450 active mW ( HYB 3164805AJ/AT(L)-40) max. 360 active mW ( HYB 3164805AJ/AT(L)-50) max. 324 active mW ( HYB 3164805AJ/AT(L)-60) max. 612 active mW ( HYB 3165805AJ/AT(L)-40) max. 468 active mW ( HYB 3165805AJ/AT(L)-50) max. 432 active mW ( HYB 3165805AJ/AT(L)-60) 7.2 mW standby (LVTTL) 3.24 mW standby (LVMOS) 720 µA standby for L-version • Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh Self refresh (L-version only) 8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164805AJ/AT) 4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165805AJ/AT) • 256 msec refresh period for L-versions • Plastic Package: P-SOJ-32-1 400 mil HYB 3164(5)805AJ P-TSOPII-32-1 400 mil HYB 3164(5)805AT(L) • • Semiconductor Group 1 6.97 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM This HYB3164(5)805A is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated on an advanced second generation 64Mbit 0,35µm-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)805A operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)805A to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)805ATL parts have a very low power „sleep mode“ supported by Self Refresh. Ordering Information Type Ordering Code Package Descriptions 8k-refresh versions: HYB 3164805AJ-40 P-SOJ-32-1 400 mil DRAM (access time 40 ns) HYB 3164805AJ-50 P-SOJ-32-1 400 mil DRAM (access time 50 ns) HYB 3164805AJ-60 P-SOJ-32-1 400 mil DRAM (access time 60 ns) HYB 3164805AT-40 P-TSOPII-32-1 400 mil DRAM (access time 40 ns) HYB 3164805AT-50 P-TSOPII-32-1 400 mil DRAM (access time 50 ns) HYB 3164805AT-60 P-TSOPII-32-1 400 mil DRAM (access time 60 ns) HYB 3164805ATL-50 P-TSOPII-32-1 400 mil DRAM (access time 50 ns) HYB 3164805ATL-60 P-TSOPII-32-1 400 mil DRAM (access time 60 ns) HYB 3165805AJ-40 P-SOJ-32-1 400 mil DRAM (access time 40 ns) HYB 3165805AJ-50 P-SOJ-32-1 400 mil DRAM (access time 50 ns) HYB 3165805AJ-60 P-SOJ-32-1 400 mil DRAM (access time 60 ns) HYB 3165805AT-40 P-TSOPII-32-1 400 mil DRAM (access time 40 ns) HYB 3165805AT-50 P-TSOPII-32-1 400 mil DRAM (access time 50 ns) HYB 3165805AT-60 P-TSOPII-32-1 400 mil DRAM (access time 60 ns) HYB 3165805ATL-50 P-TSOPII-32-1 400 mil DRAM (access time 50 ns) HYB 3165805ATL-60 P-TSOPII-32-1 400 mil DRAM (access time 60 ns) 4k-refresh versions: Semiconductor Group 2 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM P-SOJ-32-1 (400 mil) P-TSOPII-32-1 (400 mil) VCC I/O1 I/O2 I/O3 I/O4 N.C. VCC WE RAS . A0 A1 A2 A3 A4 A5 VCC O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS I/O8 I/O7 I/O6 I/O5 VSS CAS OE A12 / N.C. * A11 A10 A9 A8 A7 A6 VSS * Pin 24 is A12 for HYB 3164805AJ/AT(L) and N.C. for HYB 3165805AJ/AT(L) Pin Configuration Pin Names A0-A12 Address Inputs for 8k-refresh version HYB 3164805AJ/AT(L) A0-A11 Address Inputs for 4k-refresh version HYB 3165805AJ/AT(L) RAS Row Address Strobe OE Output Enable I/O1-I/O8 Data Input/Output CAS Column Address Strobe WE Read/Write Input Vcc Power Supply ( + 3.3V) Vss Ground Semiconductor Group 3 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM TRUTH TABLE FUNCTION RAS CAS WE OE ROW ADDR COL ADDR I/O1I/O8 Standby H H-X X X X X High Impedance Read L L H L ROW COL Data Out Early-Write L L L X ROW COL Data In Delayed-Write L L H-L H ROW COL Data In Read-Modify-Write L L H-L L-H ROW COL Data Out, Data In Hyper Page Mode Read 1st Cycle L H-L H L ROW COL Data Out 2nd Cycle L H-L H L n/a COL Data Out Hyper Page Mode Write 1st Cycle L H-L L X ROW COL Data In 2nd Cycle L H-L L X n/a COL Data In Hyper Page Mode RMW 1st Cycle L H-L H-L L-H ROW COL Data Out, Data In 2st Cycle L H-L H-L L-H n/a COL Data Out, Data In L H X X ROW n/a High Impedance CAS-before-RAS refresh H-L L H X X n/a High Impedance Test Mode Entry H-L L L X X n/a High Impedance READ L-H-L L H L ROW COL Data Out WRITE L-H-L L L X ROW COL Data In H-L L H X X X High Impedance RAS only refresh Hidden Refresh Self Refresh (L-version only) Semiconductor Group 4 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM I/O1 I/O2 I/O8 WE CAS & . Data in Buffer 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 No. 2 Clock Generator 8 Column Address Buffer(10) 10 Data out Buffer 8 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (13) 1024 x8 13 Row 13 RAS Address Buffers(13) Row Decoder 8192 13 No. 1 Clock Generator Block Diagram for HYB 3164805AJ/AT(L) Semiconductor Group OE 5 Memory Array 8192 x 1024 x 8 8 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM I/O1 I/O2 I/O8 WE CAS & . Data in Buffer 11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 No. 2 Clock Generator 8 Column Address Buffer(11) 11 Data out Buffer 8 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (12) 2048 x8 12 Row 12 RAS Address Buffers(12) 12 Row Decoder 4096 No. 1 Clock Generator Block Diagram for HYB 3165805AJ/AT(L) Semiconductor Group OE 6 Memory Array 4096 x 2048 x 8 8 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 °C Storage temperature range.........................................................................................– 55 to 150 °C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.0 W Data out current (short circuit)..................................................................................................50 mA Note Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. DC Characteristics TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Note Input high voltage VIH 2.0 Vcc+0.3 V 1) Input low voltage VIL – 0.3 0.8 V 1) Output high voltage (LVTTL) Output „H“ level voltage (Iout = -2mA) VOH 2.4 – V Output low voltage (LVTTL) Output „L“level voltage (Iout = +2mA) VOL – 0.4 V Output high voltage (LVCMOS) Output „H“ level voltage (Iout = -100uA) VOH Vcc-0.2 - V Ouput low voltage (LVCMOS) Output „L“ level voltage (Iout = +100uA) VOL - 0.2 V Input leakage current,any input II(L) –2 2 µA IO(L) –2 2 µA (0 V < Vin < Vcc , all other pins = 0 V Output leakage current (DO is disabled, 0 V < Vout < Vcc ) Semiconductor Group 7 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM DC-Characteristics (cont’d) TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V Parameter Symbol refresh version Unit Note 4k row 8k row 170 140 115 125 100 85 mA mA mA 2) 3) 4) 2 2 mA – 170 140 115 125 100 85 mA mA mA 2) 4) 140 105 85 140 105 85 mA mA 2) 3) 4) ICC5 900 900 µA – ICC5 200 200 µA – 170 140 115 170 140 115 mA mA 2) 4) 400 400 µA ICC1 Operating Current -40 ns version -50 ns version -60 ns version - (RAS, CAS, address cycling: tRC = tRC min.) Standby Current (RAS=CAS= Vih) ICC2 RAS Only Refresh Current: - ICC3 -40 ns version -50 ns version -60 ns version (RAS cycling: CAS = VIH: tRC = tRC min.) Hyper Page Mode (EDO) Current: ICC4 -40 ns version -50 ns version -60 ns version (RAS = VIL, CAS, address cycling: tHPC=tHPC min.) Standby Current (RAS=CAS= Vcc-0.2V) Standby Current (L-Version) (RAS=CAS= Vcc-0.2V) ICC6 CAS Before RAS Refresh Current -40 ns version -50 ns version -60 ns version (RAS, CAS cycling: tRC = tRC min.) Self Refresh Current (L-version only) ICC7 (CBR cycle with tRAS>TRASSmin, CAS held low, WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V) Capacitance TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A11,A12) CI1 – 5 pF Input capacitance (RAS, CAS, WE, OE) CI2 – 7 pF I/O capacitance (I/O1-I/O8) CIO – 7 pF Semiconductor Group 8 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns Parameter AC64-2E Limit Values Symbol - 40 - 50 Unit Note - 60 min. max. min. max. min. max. Common Parameters Random read or write cycle time tRC 69 – 84 – 104 – ns RAS pulse width tRAS 40 100k 50 100k 60 100k ns CAS pulse width tCAS 6 100k 8 100k 10 100k ns RAS precharge time tRP 25 – 30 – 40 – ns CAS precharge time tCP 6 – 8 – 10 – ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 5 – 7 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 5 – 7 – 10 – ns RAS to CAS delay time tRCD 9 30 11 37 14 45 ns RAS to column address delay time tRAD 7 20 9 25 12 30 ns RAS hold time tRSH 6 – 8 10 – ns CAS hold time tCSH 32 – 40 48 – ns CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 1 50 1 50 1 50 ns Refresh period for 8k-refresh-version tREF – 128 – 128 – 128 ms Refresh period for 4k-refresh version tREF – 64 – 64 – 64 ms Refresh period for L-versions tREF – 256 – 256 – 256 ms Access time from RAS tRAC – 40 – 50 – 60 ns 8, 9 Access time from CAS tCAC – 10 – 13 – 15 ns 8, 9 Access time from column address tAA – 20 – 25 – 30 ns 8,10 OE access time tOEA – 10 – 13 – 15 ns Column address to RAS lead time tRAL 20 – 25 – 30 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 7 Read Cycle Semiconductor Group 9 11 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns Parameter AC64-2E Limit Values Symbol - 40 - 50 Unit Note - 60 min. max. min. max. min. max. Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 10 0 13 0 15 ns 12 Output buffer turn-off delay from OE tOEZ 0 10 0 13 0 15 ns 12 Data to CAS low delay tDZC 0 – 0 – 0 – ns 13 Data to OE low delay tDZO 0 – 0 – 0 – ns 13 CAS high to data delay tCDD 10 – 13 – 15 – ns 14 OE high to data delay tODD 10 – 13 – 15 – ns 14 Write command hold time tWCH 5 – 7 – 10 – ns Write command pulse width tWP 5 – 7 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns Write command to RAS lead time tRWL 6 – 8 – 10 – ns Write command to CAS lead time tCWL 6 – 8 – 10 – ns Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 5 – 7 – 10 – ns 16 Read-write cycle time tRWC 89 – 109 – 133 – ns RAS to WE delay time tRWD 52 – 65 – 77 – ns 15 CAS to WE delay time tCWD 22 – 28 – 32 – ns 15 Column address to WE delay time tAWD 32 – 40 – 47 – ns 15 OE command hold time tOEH 5 – 7 – 10 – ns Hyper page mode (EDO) cycle time tHPC 16 – 20 – 24 – ns Access time from CAS precharge tCPA – 22 – 27 – 32 ns Output data hold time tCOH 3 – 5 – 5 – ns Write Cycle 15 Read-modify-Write Cycle Hyper Page Mode (EDO) Cycle Semiconductor Group 10 7 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns Parameter AC64-2E Limit Values Symbol - 40 - 50 Unit Note - 60 min. max. min. max. min. max. RAS pulse width in hyper page mode tRAS 40 200k 50 200k 60 200k ns CAS precharge to RAS Delay tRHPC 22 – 27 – 32 – ns OE pulse width tOEP 5 – 5 – 5 – ns OE hold time from CAS high tOEHC 5 – 5 – 5 – ns Output buffer turn-off delay from WE tWEZ 0 10 0 13 0 15 ns OE setup time prior to CAS tOES 5 – 5 – 5 – ns Hyper page mode (EDO) read-write cycle time tPRWC 44 – 54 – 63 – ns CAS precharge to WE tCPWD 34 – 42 – 49 – ns CAS setup time tCSR 5 – 5 – 5 – ns CAS hold time tCHR 5 – 5 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – 5 – ns Write to RAS precharge time tWRP 5 – 5 – 10 – ns Write hold time referenced to RAS tWRH 5 – 5 – 10 – ns 100k _ 100k _ ns 17 Hyper Page Mode (EDO) Readmodify-Write Cycle CAS before RAS Refresh Cycle Self Refresh Cycle (L-versions only) RAS pulse width tRASS 100k RAS precharge time tRPS 69 – 84 – 104 – ns 17 CAS hold time tCHS -50 – -50 – -50 – ns 17 Write command setup time tWTS 5 – 5 – 5 – ns 18 Write command hold time tWTH 5 – 5 – 5 – ns 18 Test Mode Cycle Semiconductor Group 11 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM Notes: 1) All voltages are referenced to VSS. Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. 2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a hyper page mode cycle ( thpc). 5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh. If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh 18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value. These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must be adjusted by 5 ns. Semiconductor Group 12 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRC tRAS V RAS IH VIL tCSH CAS IH VIL tRAD tASR V Address AAA AAAA AAA IH AAAA AAAA AAA AAAA AAA AAAA AAA VIL AAAAAAA Row tRAL tCAH tASC AAAAAAA AAA AAAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA tCRP tRSH tCAS tRCD V tRP tASR AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA Column tRCH tRAH tRCS tRRH V WE AAAAAAAA AAAAAAAA AAAAAA AAAA IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA VIL V OE I/O (Inputs) AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tOEA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A IH AAAA VIL V AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA tCDD tDZC tODD tDZO AAAAAAAA AAAAAAAA AAAAAAAA AAAA IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA VIL Row AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tCAC tCLZ V OH I/O (Outputs) V Hi Z OL tOFF AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAA A tOEZ AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA Valid Data Out Hi Z tRAC AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA WL1 “H” or “L” Read Cycle Semiconductor Group 13 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD V CAS IH VIL tRAD tASR V Address AAAAAAA AAAA AAAAAAA AAA AAAA AAA IH AAAA AAAAAAA AAA VIL V AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA AAAA AAA tASR AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAA Column AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA . Row tCWL tWCS IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA VIL tCAH tASC Row tCRP tRAL tRAH WE tRSH tCAS t WP AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWCH tRWL OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA VIL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA tDS I/O (Inputs) tDH V IH Valid Data In VIL V OH I/O (Outputs) V Hi Z OL AAAA AAAAAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAAAAA WL2 “H” or “L” Write Cycle (Early Write) Semiconductor Group 14 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRC tRAS V RAS IH VIL tCSH tRCD IH VIL tRAD tASR tCAH tASC V AAAAAAAAA AAAAAA IHAAAA AAAA AAAAAAAA AAAAAA Row Address V AAAA AAAA AAAA AAAAA IL AAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA tRAL Column tASR AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tCWL tRAH V WE tCRP tRSH tCAS V CAS tRP AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA IH AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA VIL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA tRWL tWP . Row AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tOEH V OE IH AAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA tODD tDS tOEZ tDZO tDZC I/O (Inputs) V IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA VIL AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAA AA V OH I/O (Outputs) V tCLZ tOEA Hi-Z OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAA A AAAA A AAAA A AAAA A AAAA AAAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” Valid Data AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA Hi-Z WL3 Write Cycle (OE Controlled Write) Semiconductor Group AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAA tDH 15 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRWC tRAS tRP V IH RAS tCSH VIL tRSH tCAS tRCD V tCRP IH CAS VIL tRAH tCAH tASR V A IH AAA AAA AAAAA Address VIL AAAAA AAA AAAA Row tASR tASC AAAA AA AAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAA tCWL tAWD Column tRAD tCWD tRWL tWP tRWD V WE AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA IH AAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA VIL AAA AAAAAAAAAAAAAAAAAAA AAAA Row AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAA AA tAA tRCS tOEH tOEA V OE AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA IH AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tDS tDZO tDZC V I/O (Inputs) AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAA A tDH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA AAAAAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA tCLZ Valid Data in AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAA AAA tODD tCAC tOEZ V OH AAAA AA AAAA AA AAAA AA Data AAAA AAAAAA AA Out AAAA AA I/O (Outputs) VOL tRAC AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL4 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 16 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRP tRAS V tRHPC tRCD IH RAS VIL tRSH tHPC tCRP V CAS tCAS tCAS IH VIL tCSH tRAH tASC tASR V Address tCP tCAS tCRP IH AAAA AAAAAA VIL AAAA AA AAAA AAAA AAAAAA tRAL tCAH tASC tCAH tASC tCAH AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAA AAAA AAAA AAAAAAAA AAAAAA AA Column 2 AAAA AAAA AAAAAA AA Column N AAAA AAAA AAAAA A AAA AAAA AAAA Row AAA AAA Column 1 AAAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAA AA AAAAAAAA AAAAA A tRAD tRRH tRCH tRCS WE VIH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA VIL AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA tOES V OE OH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A V OL tCAC tAA tCAC tAA tCPA tCPA tOEA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AAAAAAAAAA AA tOFF AAAA AAAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tRAC tAA tCAC tOEZ tCOH tCOH tCLZ V AAAA AAAA AAAA AAAA AAAA AAAA AAAA I/O IH (Output) V IL AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA Data Out 1 Data Out 2 AAA AAA AAA AAA AAA AAA AAA Data Out N WL5 “H” or “L” Hyper Page Mode (EDO) Read Cycle Semiconductor Group AAAA AAAA AAAA AAAA AAAA AAAA AAAA 17 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRP tRAS V tRCD IH RAS tRHCP VIL tRSH tHPC tCRP V CAS tCAS IH VIL tCSH tRAH tASC tASR V Address tCAS tCP tCAS tCRP IH AAAA AAAAAA VIL AAAA AA AAAA AAAA AAAAAA tRAL tASC tCAH tASC tCAH tCAH AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAA AA AAAAAAAA AAAAA A AAAA Column N AAAA Column 2 AAAA AAA AAAA AAAA Row AAA AAA Column 1 AAAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAA AA AAAAAAAA AAAAA A tRAD tRRH tRCH tRCS WE VIH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA VIL AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA tCAC tAA tOES OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAA V AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A OH AAAA OL tOEA tCPA tCLZ V AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA A AAAA A AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A tOEP tOFF tOEHC AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA tOEP tOEA tOEA tOEZ tOEZ Data Out 1 tOEZ AAA AAA AAA AAA AAA AAA AAA Data Out 2 AAA AAA AAA AAA AAA AAA AAA Data Out N WL6 “H” or “L” Hyper Page Mode (EDO) Read Cycle (OE Control) Semiconductor Group tCPA tOEHC tRAC tAA tCAC I/O IH (Output) V IL tCAC tAA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AAAAAAAAAA AA 18 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRP tRAS V tRCD IH RAS tRHPC VIL tRSH tHPC tCRP V CAS tCSH tRAH tASC tASR V AAAAA AAAA AA AAAA AAAA AAAAAA IH AAAA AAAAAA VIL Row AAA AAA AAA AAA AAA AAA tRAL Column tRCS AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA 1 AAAAAAAAAA AA AAAA AAAA AAAAAAAAAA AA Column tRCH tRRH tRCH tRCH tRCS AAAA AAAA A AAAA AAAA A AAAA AAAA A AAAA AAAA A AAAA AAAA A AAAA AAAA AAAAAAAAA A AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAA tCAC tOES V Column AAAA AAAA A AAAA AAAA A AAAA AAAA A AAAA AAAA N AAAAAAAAAA AAAA AAAA AAAAAAAAA A tAA tRCS tWP OE AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA 2 AAAAAAAAAA AA AAAA AAAA AAAAAAAAAA AA tAA VIH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA VIL tASC tCAH tASC tCAH tCAH tRAD WE tCAS IH VIL Address tCAS tCP tCAS tCRP OH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tCPA tWP tCAC tOFF tCPA tOEA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A V OL AAAAAAAAAAAAAAAAAAAAAAAAAAAAA tRAC tAA tCAC tOEZ tWEZ tWEZ tCLZ V AAAA A AAAA AAAAA A AAAA A AAAA A AAAA AAAAA A I/O IH (Output) V IL AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA Data Out 1 Data Out 2 AAAA AAAA AAAA AAAA AAAA AAAA AAAA Data Out N WL7 “H” or “L” Hyper Page Mode (EDO) Read Cycle (WE Control) Semiconductor Group AAA AAA AAA AAA AAA AAA AAA 19 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRP tRAS V tRCD IH RAS tRHPC VIL tCRP V CAS tCP tRAH tASC tRAL AAAAAAAA AAAAAAAA VIH AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA VIL V tASC tCAH tASC tCAH tCAH V AAAAA AAAA AAAA AA IHAAAAA Row AAA AAA AAAA AAAA AA AAAA AA AAA AAAA AAAA AA Column 2 Column 1 AAAA AAA AAAA AAAA Addr AAAAAA AAA AAAA AAAAAA AA VIL AAAA AAA AAAAAAAA AA tWCS OE tCAS tCSH tRAD WE tCAS IH VIL tASR Address tCAS tCRP tRSH tHPC AAAA AAAA A AAAA AAAA A AAAA AAAA A AAAA AAAA AAAAAAAA AAAAA A AAAA A tCWL tCWL tWCH tWCS tWCH tWP tWP AAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA Column N AAAA AAAA AAAAAAAA AAAA AAAAAAAA tRWL tCWL tWCS AAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAA AAAA AAAA AAAAA A AAAA AAAA AAAAAAAAAAAA AAAAA A tWCH tWP AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAA AA AAAA AAAA AAAA AAAAAAAAAAAAAAAA AAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A V OL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDS V AAAAAAAAAAAAAAA IH AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA I/O (Input) V IL AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAAAAAAAAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA tDH tDS AAAAAAAAAA AAAAAAAAAA AAAAAA AAAA Data In 1 AAAA AAAAAAAA AAAAAA AA Data In 2 AAAAAAAAAA “H” or “L” tDS AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA tDH Data In N AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAA A WL8 Hyper Page Mode (EDO) Early Write Cycle Semiconductor Group tDH 20 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRP tRAS V tRCD IH RAS VIL tRSH tHPC tCRP V CAS tCP tCAS IH VIL tCSH V IH AAAA AAAAAA VIL AAAA AA AAAA AAAA AAAAAA tRAL tCAH tRAH tASC tASR Address tCAS tCP tCAS tCRP tASC tCAH tASC tCAH AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAA AA AAAAAAAA AAAAA A AAAA Column 2 AAAA Column N AAAA AAA AAAA AAAA Row AAA AAA Column 1 AAAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAA AA AAAAAAAA AAAAA A tRAD tCWL tCWL tCWL tRWL tRCS tRCS WE OE tRCS VIH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA VIL AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AAAAAAAAAA AA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA V AAAAAAAA AAA OH AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA tWP tWP tWP tOEH tOEH tOEH AAAA A AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A AAAA AAAAAAAA AAA AAAA V AAAAAAAA AAAAAAAA AAAAAAA AAA OL AAAAAAAAAAAAAAA tODD tDS tDH AAAAAAAAAAAAAAAAAAAA AAA AAAA AAAA AAAA AAAA A AAA AAAA AAAA AAAA AAAA A AAA AAAA AAAA AAAA AAAA A AAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAA A AAAA A AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A tODD tDS tDS tDH tDH tODD I/O (Input) V AAAA AA AAAA AAAA AA AAAA AAAA AAAAAAA AAAA IH VIL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA Data In 1 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Data In N WL16 “H” or “L” Hyper Page Mode (EDO) Late Write Cycle Semiconductor Group Data In 2 21 tDS Data Out tCAC tAA AAAA AA AAAA AA AAAA AAAAAA AA tDH tOEH tDS Data In Data Out tOEZ AAAA AA AAAA AA AAAA AAAAAA AA Data Out tDS tRAC V OH I/O (Outputs) V IH OL tOEH tOEZ tDH AAAAAA AAAA AA AAAA AAAAAA AA tCAC Data In tODD tAA tCLZ tCPA tDZC AAAA A AAAA AAAAA A I/O (Inputs) V IL OE 22 AAAA A AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA AAAA AAAAAAA AAA V V IH AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA A AAAA AAAAA A tDZC tCLZ tDZO AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA tDH Data In tCLZ tCPA tDZC AAAA A AAAA A AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A tODD AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA V IL tOEA tOEA tAWD tAA V IH WE V IL tRCS AAAA AAA AAAA AAA AAAA AAAAAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA AAAA AAAAAAA AAA Hyper Page Mode (EDO) Read-Modify-Write Cycle Semiconductor Group AAAAA A AAAA AAAAA tODD tWP tOEA tWP tAWD tWP tCWL Row IH V Address V IL AAAA A AAAA AAAAAAA AAAA AAAAA tASR CAS V IL IH tAWD tCPWD tCWD tCPWD tCWD tASC Column tCAH AAAA AA AAAA AAAA A AAAA AAAAAA tRAD tRAH tRCD V tRWD tCWD tASC Column tCAH tCP AAAA AA AAAA AAAA AA AAAA AAAA AAAAAAA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA A AAAA AAAAAAA AAAA AAAAA tCAS tCSH IH V IL RAS tCWL Column tASC AAAA A AAAA AAAAAAA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AAAAAAA AAAA AAAA AA AAAA AAAA A AAAA AAAAAA tCAS tPRWC tRASP V tRWL tCWL Row tASR tRAL tCAH tCAS tRSH tCRP tRP AAAAA AAAAA AAAAA AAAAA AAA AAAAA AA AAAAA AAAAA AAA AAAAA AA AAAAA AAAAA AAAAA AAA AAAAA AA AAAAA AAAAA AAA AA AAA AA AAA AA AAA AA AAA AAAAA AA AAA AA AAA AA AAA AA AAA AA AAA AA AAA AA AAA AAAAA AA AAAAA AAAAA AAAAA AAAAA AAAA AAAAA A AAAAA AAAAA AAAAA AAAA AAAAA A AAAAA AAAAA AAAAA AAAA AAAAA A AAAAA AAAAA AAAA AAAAA A AAAAA AAAAA AAAAA AAAA AAAAA A AAAAA AAAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA tOEH HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM WL17 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRC tRAS tRP V IH RAS VIL tCRP tRPC V AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA IH CAS VIL tRAH tASR tASR V Address AAAA AAAA IH AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA VIL AAAAAAAAAAAA AAAA Row AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A V OH I/O (Outputs) V HI-Z OL AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA “H” or “L” WL9 RAS Only Refresh Cycle Semiconductor Group 23 Row HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRC tRP V RAS tRAS IH VIL tRPC tCSR tCRP tCP tRPC tCHR V CAS tRP AAAA A AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A IH VIL tWRP tWRH V WE AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA VIL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tOEZ V OE AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA IH VIL tCDD V AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA IH I/O (Inputs) V IL tODD V OH I/O (Outputs)VOL HI-Z tOFF AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL10 CAS-before-RAS Refresh Cycle Semiconductor Group 24 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRC tRC RAS tRP tRAS V tRP tRAS IH VIL tRSH tRCD tCRP tCHR V CAS IH tRAD VIL tWRP tASC tASR Address V AAAAAAA IHAAAA AAAAAAA AAA AAAAAAA AAA VIL AAAA AAAA AAAAAAA AAA tRAH AAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA Column AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA Row AAAA AAAA AAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA Row tRRH tRCS WE tASR tWRH tCAH V AAAAAAAAAAAAAAAA IHAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA VIL AAAA AAAAAAAAAAAA AAAAAAAA AAAA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AA tAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA tOEA OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA VIL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA tDZC tCDD tDZO V I/O (Inputs) IH VIL AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAA tODD tCAC tOFF tCLZ tOEZ tRAC V AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A OH I/O (Outputs) V OL AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA Valid Data Out “H” or “L” HI-Z WL11 Hidden Refresh Read Cycle Semiconductor Group AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAA A 25 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRC tRC tRP tRAS V RAS IH tRAS tRP VIL tRCD tRSH tCHR tCRP V CAS IH VIL tRAD tRAH tASC tCAH tASR Address V AAAAAAA IHAAAAAAA AAAAAAA Row AAAAAAA VIL AAAA AAAAAAA AAA AAAA AA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AA Column AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA tWCS tWRP tWRH tWCH tWP V WE AAAAAAAA AAAA AAAA AAA AAAA AAAA AAAA AAA IH AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA VIL AAAA AAA tDS I/O (Input) tASR V AAAAAAAAAAAAAAA IHAAAA AAAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAAAAAAAAA AAA V AAAA IL AAAAAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAA tDH Valid Data AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA V OH I/O (Output) V OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA HI-Z “H” or “L” WL12 Hidden Refresh Early Write Cycle Semiconductor Group Row 26 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRP V RAS tRASS tRPS IH VIL tRPC tCP V CAS tCRP tCHS tCSR AAAA AAAA A AAAA AAAA A AAAA AAAA A AAAA AAAA A AAAA AAAA AAAAAAAAA A IH VIL tWRP tWRH V WE AAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA VIL V OE AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA IH VIL tCDD V AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tODD IH I/O (Inputs) V IL tOEZ V OH I/O (Outputs) VOL HI-Z tOFF AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL13 Self Refresh (Sleep Mode) Semiconductor Group 27 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM tRC tRP V RAS tRAS tRP IH VIL tRPC tCSR tCP tCHR tRPC V CAS tCRP AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAA AAAA A AAAA AAAA AAAA A AAAA AAAA AAAA AAAAAAAAAAAAA A IH VIL tASR tRAH V AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAA AAA AAAA Address IHAAAA AAAA AAAAAAAA AAAAAAAA AAA AAAA AAA Row AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAA AAA VIL AAAAAAAAAAAAAAAAAAAAAAA AAAAAAA tWTS V WE tWTH AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA VIL AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA V OE AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA IH VIL tODD V IH I/O (Inputs) V IL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA HI-Z tCDD tOEZ V AAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA OHAAA I/O (Outputs) V OL AAA AAAA AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA HI-Z tOFF “H” or “L” WL15 Test Mode Entry Cycle Semiconductor Group 28 HYB3164(5)805AJ/AT(L)-40/-50/-60 8M x 8-DRAM Package Outlines Plastic Package P-SOJ-32-1 (400 mil) (Small Outline J-lead, SMD) Plastic Package P-TSOPII-32-1 (400 mil) (Small Outline J-lead, SMD) Semiconductor Group 29