2M x 8-Bit Dynamic RAM HYB5117800BSJ-50/-60/-70 Advanced Information • 2 097 152 words by 8-bit organization • 0 to 70 °C operating temperature • Performance:: -50 -60 -70 tRAC RAS access time 50 60 70 ns tCAC CAS access time 13 15 20 ns tAA Access time from address 25 30 35 ns tRC Read/Write cycle time 90 110 130 ns tPC Fast page mode cycle time 35 40 45 ns • Single + 5 V (± 10 %) supply • Low power dissipation max. 660 active mW (-50 version) max. 605 active mW (-60 version) max. 550 active mW (-70 version) 11 mW standby (TTL) 5.5. mW standby (CMOS) • Output unlatched at cycle end allows two-dimensional chip selection • Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode • Fast page mode capability • All inputs, outputs and clocks fully TTL-compatible • 2048 refresh cycles / 32 ms • Plastic Package: Semiconductor Group P-SOJ-28-3 400 mil 1 1.96 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM The HYB 5117800BSJ is a 16 MBit dynamic RAM organized as 2097152 words by 8-bits. The HYB 5117800BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5117800BSJ to be packaged in a standard SOJ 28 400 mil plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type Ordering Code Package HYB 5117800BSJ-50 Q67100-Q1092 P-SOJ-28-3 400 mil DRAM (access time 50 ns) HYB 5117800BSJ-60 Q67100-Q1093 P-SOJ-28-3 400 mil DRAM (access time 60 ns) HYB 5117800BSJ-70 Q67100-Q1094 P-SOJ-28-3 400 mil DRAM (access time 70 ns) Pin Names A0 to A10 Row Address Inputs A0 to A9 Column Address Inputs RAS Row Address Strobe OE Output Enable I/O1-I/O8 Data Input/Output CAS Column Address Strobe WE Read/Write Input VCC Power Supply (+ 5 V) VSS Ground (0 V) N.C. not connected Semiconductor Group 2 Descriptions HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM P-SOJ-28-3 (400mil) VCC I/O1 I/O2 I/O3 I/O4 WE RAS N.C. A10 A0 A1 A2 A3 VCC O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Pin Configuration Semiconductor Group 3 VSS I/O8 I/O7 I/O6 I/O5 CAS OE A9 A8 A7 A6 A5 A4 VSS HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM I/O1 I/O2 I/O8 WE . CAS & Data in Buffer 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 No. 2 Clock Generator 8 Column Address Buffer(10) 10 Data out Buffer OE 8 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (11) 8 1024 x8 11 Row 11 RAS Address Buffers(11) Row Decoder 2048 11 No. 1 Clock Generator Voltage Down Generator Block Diagram Semiconductor Group Memory Array 2048x1024x8 4 VCC VCC (internal) HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 °C Storage temperature range.........................................................................................– 55 to 150 ° C Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V Power supply voltage...................................................................................................-1.0V to 7.0 V Power dissipation..................................................................................................................... 1.0 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 Vcc+0.5 V 1) Input low voltage VIL – 0.5 0.8 V 1) Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1) Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1) Input leakage current,any input (0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V) IO(L) – 10 10 µA 1) Average VCC supply current: ICC1 -50 ns version -60 ns version -70 ns version (RAS, CAS, address cycling, tRC = tRC min.) – – – 120 110 100 mA mA mA 2) 3) 4) Standby VCC supply current (RAS = CAS = VIH) ICC2 – 2 mA – Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version (RAS cycling: CAS = VIH, tRC = tRC min.) ICC3 – – – 120 110 100 mA mA mA 2) 4) Semiconductor Group 5 2) 3) 4) 2) 3) 4) 2) 4) 2) 4) HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM DC Characteristics (cont’d) TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Average VCC supply current, ICC4 during fast page mode: -50 ns version -60 ns version -70 ns version (RAS = VIL, CAS, address cycling,tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version ICC6 Limit Values min. max. Unit Test Condition – – – 40 35 30 mA mA mA 2) 3) 4) – 1 mA 1) – – – 120 110 100 mA mA mA 2) 4) _ 1 mA 2) 3) 4) 2) 3) 4) 2) 4) 2) 4) (RAS, CAS cycling, tRC = tRC min.) Average Self Refresh Current ICC7 (CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V) Capacitance TA = 0 to 70 °C,VCC = 5 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A10) CI1 – 5 pF Input capacitance (RAS, CAS, WE, OE) CI2 – 7 pF I/O capacitance (I/O1-I/O8) CIO – 7 pF Semiconductor Group 6 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns Parameter 16F Limit Values Symbol -50 Unit Note -60 -70 min. max. min. max. min. max. common parameters Random read or write cycle time tRC 90 – 110 – 130 – ns RAS precharge time tRP 30 – 40 – 50 – ns RAS pulse width tRAS 50 10k 60 10k 70 10k ns CAS pulse width tCAS 13 10k 15 10k 20 10k ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 8 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 10 – 15 – 15 – ns RAS to CAS delay time tRCD 18 37 20 45 20 50 RAS to column address delay time tRAD 13 25 15 30 15 35 ns RAS hold time tRSH 13 15 – 20 – ns CAS hold time tCSH 50 60 – 70 – ns CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 3 50 3 50 3 50 ns Refresh period tREF – 32 – 32 – 32 ms Access time from RAS tRAC – 50 – 60 – 70 ns 8, 9 Access time from CAS tCAC – 13 – 15 – 20 ns 8, 9 Access time from column address tAA – 25 – 30 – 35 ns 8,10 OE access time – 13 – 15 – 20 ns Column address to RAS lead time tRAL 25 – 30 – 35 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 0 20 ns 12 7 Read Cycle Semiconductor Group tOEA 7 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns Parameter 16F Limit Values Symbol -50 Unit Note -60 -70 min. max. min. max. min. max. Output buffer turn-off delay from OE tOEZ 0 13 0 15 0 20 ns 12 Data to OE low delay tDZO 0 – 0 – 0 – ns 13 CAS high to data delay tCDD 13 – 15 – 20 – ns 14 OE high to data delay tODD 13 – 15 – 20 – ns 14 Write command hold time tWCH 8 – 10 – 10 – ns Write command pulse width tWP 8 – 10 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – 20 – ns Write command to CAS lead time tCWL 13 – 15 – 20 – ns Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 10 – 10 – 15 – ns 16 Data to CAS low delay tDZC 0 – 0 – 0 – ns 13 Read-write cycle time tRWC 126 – 150 – 180 – ns RAS to WE delay time tRWD 68 – 80 – 95 – ns 15 CAS to WE delay time tCWD 31 – 35 – 45 – ns 15 Column address to WE delay time tAWD 43 – 50 – 60 – ns 15 OE command hold time tOEH 13 – 15 – 20 – ns Fast page mode cycle time tPC 35 – 40 – 45 – ns CAS precharge time tCP 10 – 10 – 10 – ns Access time from CAS precharge tCPA – 30 – 35 – 40 ns RAS pulse width tRAS 50 200k 60 200k 70 200k ns CAS precharge to RAS Delay tRHPC 30 – – – Write Cycle 15 Read-Modify-Write Cycle Fast Page Mode Cycle Semiconductor Group 8 35 40 ns 7 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns Parameter 16F Limit Values Symbol -50 min. Unit Note -60 -70 max. min. max. min. max. Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle time tPRWC 71 – 80 – 95 – ns CAS precharge to WE tCPWD 48 – 55 – 65 – ns CAS setup time tCSR 10 – 10 – 10 – ns CAS hold time tCHR 10 – 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – 10 – ns tCPT 35 – 40 – 40 – ns CAS hold time tCHRT 30 – 30 – 30 – ns Write command setup time tWTS 10 – 10 – 10 – ns Write command hold time tWTH 10 – 10 – 10 – ns RAS pulse width tRASS 100k _ 100k _ 100k _ ns 17 RAS precharge time tRPS 95 _ 110 _ 130 _ ns 17 CAS hold time tCHS -50 _ -50 _ -50 _ ns 17 CAS-before-RAS Refresh Cycle CAS-before-RAS Counter Test Cycle CAS precharge time Test Mode Self Refresh Cycle Semiconductor Group 9 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 2 TTL loads and 100 pF. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)Either tDZC or tDZO must be satisfied. 14)Either tCDD or tODD must be satisfied. 15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. Semiconductor Group 10 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRAS tRP V IH RAS VIL tCSH V IH CAS VIL tRAD tASR V Address AAAAAAA AAA IH AAAA AAAAAAA AAAA AAA AAAA AAAAAAA AAA VIL Row tASC tRAH tRAL tCAH AAAAAAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA tCRP tRSH tCAS tRCD tASR AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA Column tRCH tRCS tRRH V WE AAAAAAAAAAAAAAAAAA AAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL V OE I/O (Inputs) AAAAAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAA AAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAA AAAAAAAA AAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA tAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tDZC AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD tODD tDZO V AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tCAC tCLZ V OH I/O (Outputs) V Row Hi Z OL tOFF A AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAA AAAAAAAA AAAA AAAA A AAAAAAAA AAAAAAAA AAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAA tOEZ AAAAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AAAAAA Valid Data Out Hi Z tRAC AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA WL1 “H” or “L” Read Cycle Semiconductor Group 11 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD tRSH tCAS V IH CAS VIL tRAD tASR V Address AAAAAAA AAAA AAA AAAA AAAAAAA AAA IH AAAA AAAAAAA AAA VIL tRAL AAA AAAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA tRAH V WE tASR AAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAA AAAAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA AAAA AAAAAAAA AAAA AA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA . Row tCWL tWCS AAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL tCAH tASC Row tCRP t WP AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA A AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA A AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA A AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWCH tRWL OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDS I/O (Inputs) tDH V IH Valid Data In VIL V OH I/O (Outputs) V Hi Z OL AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA WL2 “H” or “L” Write Cycle (Early Write) Semiconductor Group 12 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD V IH CAS VIL tRAD tASR tCAH tASC V AAAAAAAAA AAAAA IHAAAA AAAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA Row Address V AAAA AAAAAAAA AAAAAAAAA IL AAAAAAAAA tRAL Column tASR AAAA AAAAAAAA AAAA AAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL tRAH V WE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tCRP tRSH tCAS tRWL tWP AA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA . Row AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEH V OE IH AAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAA tODD tDS tOEZ tDZO tDZC I/O (Inputs) V AAAAAAAAA IH AAAA AAAAAAAA AAAAAAAAAAAAA VIL AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA A AAAA AAAA AAAA AAAAA AAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAA tCLZ tOEA V OH I/O (Outputs) V Hi-Z OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAA A AAAA AAAAA A AAAA A AAAAA AAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA “H” or “L” Valid Data AAAAAAAA AAAAAAAAAAA AAAA AAAAAAAA AAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Hi-Z WL3 Write Cycle (OE Controlled Write) Semiconductor Group AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tDH 13 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRWC tRAS tRP V IH RAS tCSH VIL tRSH tCAS tRCD V tCRP IH CAS VIL tRAH tCAH V AA IH AAA AAA AAAA Address AA AAA AAA AAAA VIL Row tASR tASC tASR AAAAAA AA AAAA AAAAAA AA AAAA AA AAAA AAAAAA AAAAAAAA AAAAAAAA AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA t CWL tAWD Column tRAD tCWD tRWL tRWD V WE Row tWP AAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA IH AAA AAAA AAA AAAA AAAAAAAA AAAAAAA AAAAAAAA AAAAAAAA AAA AAAA AAAA AAAA AAA VIL AAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAA AAAAAAAA AAAA AA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAAAAA AAAA AAAAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAA tAA tRCS tOEH tOEA V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OE VIL AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDS tDZO tDZC tDH V I/O (Inputs) AAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAA AAAAAAAA AAAAAAAA AAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA A AAAAA AAAA AAAA AAAA AAAAAAAA A AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAA AAA AAAA AAAAAAA AAA AAAA AAAAAAA AAAAAAA tCLZ Valid Data in AAAAAAA AAAAAAAA AAAA AAA AAAAAAAA AAAAAAAA AAA AAAA AAAAAAAA AAAA AAAAAAA AAAA AAAAAAAA AAAAAAA AAAAAAAA AAAA AAA AAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA tODD tCAC tOEZ V OH AAAA AA AAAA AA Data AAAA AA AAAA AA AAAA AAAAAA AA Out I/O (Outputs) VOL tRAC AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL4 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 14 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRP tRASP V IH RAS VIL tRHCP tRSH tCAS tPC tCAS tCP tCAS tRCD V tCRP IH CAS VIL tCSH tRAH tASR V Address tCAH tASC A A AAAA IH AAAA AAAAAA AAAAA AAAAA Row AAAAAA AAAA AAAA A AAAAAA VIL AAAA AAAAA AAAA tRAD tASC AAAAAA AAAA AA AAAAAAAA AA AAAAAAAA AA Column AAAA AAAAAA AAAAAAAA AAAAAAAAAA Column tRCH WE AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAA AAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA A AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A IH AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA VIL tAA V OE AAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAAAAAAA AAAAAAAA AAAA IH AAAA AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAA V AAAAAAAAAAAAAAAAAAAAAAAAAAA IL V AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAA VIL tCAC tRAC tCLZ V OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAA A AAAAA A AAAA AAAAA AAAAA AAAAA tOFF tOEZ AAAA A AAAA A AAAA A Valid AAAA A AAAA A Data Out AAAA A AAAAA OH I/O (Outputs) V tODD tCAC tCLZ AAAA AA AAAA AA AAAA AA Valid AAAA AA AAAA AA Data Out AAAA AA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAA tCDD tDZO AAA AAAAA AA AAAAA AA AAA AAAAA AAAAA AAAAA tOFF tOEZ tDZC AAAA AAAA AAA AAAA AAAA AAA AAAA AAAA AAAA AAAAAAA AAA AAAA AAAA AAA AAAA AAAA AAA tRRHAAAAAAAAAAA tODD tCAC tCLZ AAAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAA AAAA AA AAAAAAAA AA AAAAAAAA AA AAAAAAAAAA tOFF tOEZ AAAA AA AAAA AA AAAA AA Valid AAAA AA AAAA AA Data Out AAAA AA AAAAAA “H” or “L” FPM1 Fast Page Mode Read Cycle Semiconductor Group A AAAAAAAA AAAAAAAA AAAAA AAAAAAAA AAAA A AAAAAAAA AAAAAAAA AAAAA AAAA AAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAA tDZO tODD Row tRCH tCPA tAA tOEA tDZC tDZC tDZO I/O (Inputs) AAAA A AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A tCPA tAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAA AAAA AAA AAAAAAAA AAA AAAAAAAA AAAA AAA AAAAAAA AAAAAAAA AAAAAAAAAAA tRCS tOEA tOEA tASR tASC AAAAA AAAA A AAAAAAAA A Column AAAAAAAA AAAA A AAAAA AAAAAAAA AAAAAAAAA tRCS tRCS V tCAH tCAH 15 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRP tRAS V IH RAS VIL tRSH tPC tRCD tCAS tCP tCAS tCAS tCRP V IH CAS VIL tRAL tRAH tCAH tASR V Address AAAAA AAAA A AAAA A AAAA AAAAAA IH AAAA AAAAAA VIL Row A AAAA AAAA AA AAAA AAAA A AAAA AAAAAA tASC tCWL tWCS AAAA AAAAAAAA AAAAA A tWP AAA AAAAAAAA AAAAAAAA AAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAA tWCS tWCH AAAA AAAAAAA AAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAA AAAA AAAAAAAA AAAAAAA AAA tWP AAAA AAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAA A AAAA AAAAAAAA AAAAAAAA AAAAA A tCWL tRWL tWCH tWP AAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tDH V AAA AAAAAAA AAAAAAAA AAAAAAAA IH AAAA AAAAAAAAAAAAAAA VIL AAAAAAA AAAAAAAA AAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAAAAAAAA Valid Data In tDH tDH tDS tDS I/O (Inputs) tASR tCAH AAAA AAAAAAAA AAAAAA AA tWCH AAAAAAA AAAAAAAA AAAAAAAAAAA AAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAA V OE AAAA AAAAAAAA AAAAAA AA tCWL V VIL tASC AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAA Column AAAA AAAAAA Column AAAA AAAAA Column Column AAAA AAAA AAAA AAAA AAAA AA AAAA AA AAAAA AAAA AAAA AAAA AA AA A AAAA AAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAA AAAAA tRAD tWCS WE tCAH tASC A AAAAA AAAAAAAA AAAA AAAAA AAAA A AAAAAAAA AAAAA AAAA A AAAAAAAA AAAAAAAAA Valid Data In tDS AAA AAAAAAA AAAAAAAA AAAA AAAAAAA AAAA AAA AAAAAAAA AAAAAAA AAAA AAA AAAAAAAA AAAAAAAAAAA Valid Data In AAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAA AAAAAAAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAA AAA AAAAAAAA AAAAAAAA AAAA AAAAAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA V OH I/O (Outputs) V HI-Z OL AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA “H” or “L” FPM2 Fast Page Mode Early Write Cycle Semiconductor Group 16 17 Data Out tDS tDH tOEZ tDS tDH Data Out tOEZ AAAAAA AA AAAA AAAA AAAAAA AA tDS Data Out “H” or “L” tRAC V OH I/O (Outputs) V AAA AAAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA OL tOEH tODD tOEZ tDH AAAA AA AAAA AAAAAA AA tCAC I/O (Inputs) V IL IH AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA V AAAAAA AAAAAA AAAAAA AAAAAA tAA tCLZ AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA tDZC tCLZ tDZO V IL IH OE V tAA tOEA tAWD V IL IH V AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA tCAC A AAAA AAAAA AAAAA Data In tCPA tDZC tOEA tAWD tWP AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAAAA AAAA AAAAAA tOEH Data In AA AAAA AA AAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA tODD tDZC tCLZ tCPA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA AAAA AAAAA A AAAA A tAA Data In tODD tWP tOEA tWP tCWL tAWD tCPWD tCWD tCPWD tCWD tCWL tRWD tCWD Row V IL V IH AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAAAA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA Address tASR AAAA AA AAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AA AAAA AAAAAA AAAAAA AA AAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAAA A AAAA AAAAA WE tASC Column tCAH tRAH tRAD V IL IH CAS V AA AAAA AAAAAA AA AAAA AA AAAA AAAAAA tRCS tASC Column Address tCAH tCP AA AAAA AA AAAAAA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AA AAAAAA AAAA AAAAAA AAAAAA AAAAAA tCAS tCSH tRCD V IL IH RAS Column tASC tPRWC tCAS tRAS V AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA tRWL tCWL Row tASR tRAL tCAH tCAS tRSH tCRP tRP AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AAAAAA AA AAAA AA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA Fast Page Mode Read-Modify-Write Cycle Semiconductor Group AAAA AAAAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AA AAAA AAAAAA AAAAAA AA tOEH HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRAS tRP V IH RAS VIL tCRP tRPC V CAS AAAAA AAAA A AAAAA AAAAAAAA AAAA A AAAA AAAA AAAA AAAAA A AAAA AAAA AAAAAAAAA IH VIL tRAH tASR tASR V Address AAAA IH AAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAA VIL AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAA Row A AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA A AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OH I/O (Outputs) V HI-Z OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA “H” or “L” WL9 RAS-Only Refresh Cycle Semiconductor Group 18 Row HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRP V RAS tRAS IH VIL tRPC tCSR tCRP tCP tRPC tCHR V CAS tRP AAAAAA AAAAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA IH VIL tWRP tWRH V WE AAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAA VIL AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAA AAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEZ V AA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH OE VIL tCDD V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH I/O (Inputs) V IL tODD V OH I/O (Outputs)VOL HI-Z tOFF AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL10 CAS-Before-RAS Refresh Cycle Semiconductor Group 19 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRC RAS tRP tRAS V tRP tRAS IH VIL tRSH tRCD tCRP tCHR V CAS IH tRAD VIL tWRP tASC tASR Address V AAAAAAA IHAAAA AAA AAAAAAA AAAAAAA AAA VIL AAAA AAA AAAA AAAAAAA tRAH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAA AA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAA Column AAAA AA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA Row AAAA AAAA AAAA AAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row tRRH tRCS WE tASR tWRH tCAH V AAAAAAAAAAAAAAAA AAAAAAAA IHAAAA AAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA VIL AAAA AAAAAAAAAAAA AAAAAAAA AAAA AAAAAA AA AAAA AAAAAA AA AA AAAA AAAAAA AAAAAA tAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEA OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAA VIL AAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC tCDD tDZO V I/O (Inputs) IH VIL AAAA AAAAAAAAAAAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA tODD tCAC tOFF tCLZ tOEZ tRAC V A AAAAA AAAA A AAAA A AAAA AAAA AAAAA A OH I/O (Outputs) V OL AAAA AAA AAAA AAAAAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA Valid Data Out “H” or “L” HI-Z WL11 Hidden Refresh Cycle (Read) Semiconductor Group AAAA AAAAAAAAAAAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAA 20 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRC tRP tRAS V RAS IH tRAS tRP VIL tRCD tRSH tCHR tCRP V CAS IH VIL tRAD tRAH tASC tCAH tASR Address V AAAAAAA IHAAAAAAA AAAA AAAAAAA AAA Row VIL AAAA AAAAAAA AAA AA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAA AAAA AA AAAAAAAA AA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAAAA AAAAAA Column AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWCS tWRP tWRH tWCH tWP V WE AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAA AAA IH AAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAA tDS I/O (Input) tASR V AAAAAAAAAAAAAAA IHAAAA AAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAA AAA AAAAAAAAAAAA AAA AAAA V AAAA IL AAAAAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAAAAAA AAAA AAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAAAAAA AAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA tDH Valid Data AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OH I/O (Output) V OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA HI-Z “H” or “L” WL12 Hidden Refresh Cycle (Early Write) Semiconductor Group Row 21 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRP tRASS tRPS V RAS IH VIL tRPC tCP V CAS tCRP tCHS tCSR A AAAAAAAAA AAAAAAAA A AAAAAAAA A AAAAAAAA AAAAA AAAA A AAAAAAAA AAAAAAAAA IH VIL tWRP tWRH V WE AAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAA AAAAAAA AAAA AAAAAAAAAAAA AAA AAAA IH AAAA AAAAAAAAAAAA AAAAAAAA AAAAAAA AAA VIL V AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAA AA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH OE AAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA A AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tCDD V AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH I/O (Inputs) V IL tODD tOEZ V OH I/O (Outputs) VOL HI-Z tOFF AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA “H” or “L” WL13 CAS before RAS Self Refresh Cycle Semiconductor Group 22 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRAS tRP Read Cycle: RAS V IH V IL tCSR tRSH tCAS tCP tCHR CAS V IH V IL tRAL tASC Address V IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA WE OE I/O (Inputs) I/O (Outputs) AAAAAAAA AAAAAAAAAA V IL AAAA AAAAAAAAAAAA AAAAA tRRH tAA tCAC AAAAAA AAAAAAAA AAAA AA AAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AA AAAA AAAA AAAA AAAA AAAAAA AAAA AAAA AAAA tWRH tDZC AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tODD tDZO VOH VOL Write Cycle: AAAAAAAAAAAA AA AAAA AA AAAAAA AAAA AAAAAA AAAAAA tWCS tWRP AAAAA AAAAAAAA AAAA A AAAAAAAA AAAAAAAA AAAAA AAAA AAAAAAAA AAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAA tCDD tOFF tCLZ tRCH AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tOEA tRCS V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA V IHAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tASR AA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Column tWRP V IHAAAAAAAAAAAAA tCAH tRWL tCWL tWCH AA AAAAAAAA AAAA AA AAAA AAAAAAAA AAAAAA AAAAAAAA AA AAAA AAAA AAAA AAAAAAAAAAAAAA tOEZ Data Out AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA WE V IH AAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA V IL AAAA AAAAAAAAAAAA OE AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA V IH AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA I/O (Inputs) V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWRH tDS I/O (Outputs) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA V IH V IL HI-Z CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 23 tDH Data In AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM tRC tRP tRAS V RAS tRP IH VIL tRPC tCSR tCP tCHR tRPC V CAS tCRP AAAA AAAAAAAA AAAAA A AAAAAAAAAAAA A AAAAAAAA AAAA AAAAAAAA AAAAA A AAAAAAAA AAAAAAAAAAAAA IH VIL tASR tRAH V AAAA AAAAAAAA AAAAAAAA AAA AAA AAAAAAAA AAAA AAAA AAAA AAAA AAA AAA Address IHAAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAA Row AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAA AAA AAA VIL AAAAAAAAAAAAAAAAAAAAAAAA AAA AAA tWTS V WE tWTH A AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA A AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA A AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA A AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA IH AAAA VIL V OE AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAA AAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA IH VIL tODD V IH I/O (Inputs) V IL HI-Z tCDD AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA tOEZ V AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA OHAAA AAAAAAAA AAAAAAAAAAAAAAA AAAAAAAA I/O (Outputs) V AAAA AAAAAAAAAAA AAAA AAAA AAAA AAAAAAAAAAA AAAA AAAA AAAA AAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA OL AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA HI-Z tOFF “H” or “L” WL15 Test Mode Entry Semiconductor Group 24 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM Test Mode As the HYB 5117800BSJ is organized internally as 1M x 16-bits, a test mode cycle using 2:1 compression can be used to improve test time. Note that in the 2M x 8 version the test time is reduced by 1/2 for a N test pattern. In a test mode “write” the data from each I/O pin is written into two 1M blocks simultaneously (all “1” s or all “0” s). In test mode “read” each I/O output is used for indicating the test mode result. If the internal two bits are equal, the I/O would indicate a “1”. If they were not equal, the I/O would indicate a “0”. The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be used. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cylces. Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other addresses are don’t care. Semiconductor Group 25 HYB 5117800BSJ-50/-60/-70 2M x 8-DRAM Package Outlines 0.81max 1.27 0.51 10.16 +0.13 - -0.13 0.18 M 1) 9.4 +- 0.25 0.1 28x 11.18 +0.13 - GPJ05699 28 15 1 14 18.54 -0.25 1) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side Semiconductor Group 0.2 +- 0.1 0.5 30 O 3.75 -0.5 0.8 min. Plastic Package P-SOJ-28-3 (400 mil) (Small Outline J-lead, SMD) 26 0.18 M