HYB3116160BSJ/BST(L)-50/-60/-70 HYB3118160BSJ/BST(L)-50/-60/-70 1M x 16-Bit Dynamic RAM (1k & 4k -Refresh) Advanced Information • • • • • • • • • • • • • 1 048 576 words by 16-bit organization 0 to 70 °C operating temperature Performance: -50 -60 -70 tRAC RAS access time 50 60 70 ns tCAC CAS access time 13 15 20 ns tAA Access time from address 25 30 35 ns tRC Read/Write cycle time 90 110 130 ns tPC Fast page mode cycle time 35 40 45 ns Single + 3.3 V (± 0.3 V) supply Low power dissipation max. 720 active mW ( HYB3118160BSJ/BST-50) max. 648 active mW ( HYB3118160BSJ/BST-60) max. 576 active mW ( HYB3118160BSJ/BST-70) max. 360 active mW ( HYB3116160BSJ/BST-50) max. 324 active mW ( HYB3116160BSJ/BST-60) max. 288 active mW ( HYB3116160BSJ/BST-70) 7.2 mW standby (LV-TTL) 3.6 mW standby (LV-CMOS) 720 µW standby for L-version Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh Fast page mode capability 2 CAS / 1 WE All inputs, outputs and clocks fully LV-TTL-compatible 1024 refresh cycles / 16 ms for HYB 3118160BSJ 4096 refresh cycles / 64 ms for HYB 3116160BSJ Plastic Package: P-SOJ-42-1 400 mil P-TSOPII-50/44-1 400mil Semiconductor Group 1 1.96 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM The HYB 3116(8)160BSJ/BST is a 16 MBit dynamic RAM organized as 1 048 576 words by 16 bits. The HYB 3116(8)160BSJ/BST utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 3116(8)160BSJ/BST to be packaged in standard SOJ-42 and TSOPII-50/44 plastic package with 400mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with highperformance logic device families.The HYB3116160BSTL parts have a very low power „sleep mode“ suppported by Self Refresh. Ordering Information Type Ordering Code Package Descriptions HYB 3116160BSJ-50 on request P-SOJ-42 400 mil DRAM (access time 50 ns) HYB 3116160BSJ-60 on request P-SOJ-42 400 mil DRAM (access time 60 ns) HYB 3116160BSJ-70 on request P-SOJ-42 400 mil DRAM (access time 70 ns) HYB 3118160BSJ-50 on request P-SOJ-42 400 mil DRAM (access time 50 ns) HYB 3118160BSJ-60 on request P-SOJ-42 400 mil DRAM (access time 60 ns) HYB 3118160BSJ-70 on request P-SOJ-42 400 mil DRAM (access time 70 ns) HYB 3116160BST-50 on request P-TSOPII-50/44 400 mil DRAM (access time 50 ns) HYB 3116160BST-60 on request P-TSOPII-50/44 400 mil DRAM (access time 60 ns) HYB 3116160BST-70 on request P-TSOPII-50/44 400 mil DRAM (access time 70 ns) HYB 3118160BST-50 on request P-TSOPII-50/44 400 mil DRAM (access time 50 ns) HYB 3118160BST-60 on request P-TSOPII-50/44 400 mil DRAM (access time 60 ns) HYB 3118160BST-70 on request P-TSOPII-50/44 400 mil DRAM (access time 70 ns) Pin Names A0 to A9 Row Address Inputs for 1k-refresh version HYB3118160BSJ/BST A0 to A9 Column Addess Inputs for 1k-refresh version HYB3118160BSJ/BST A0 to A11 Row Address Inputs for 4k-refresh version HYB3116160BSJ/BST A0 to A7 Column Address Inputs for 4k-refresh version HYB3116160BSJ/BST RAS Row Address Strobe OE Output Enable I/O1-I/O16 Data Input/Output UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe WE Read/Write Input VCC Power Supply (+ 3.3 V) VSS Ground (0 V) N.C. not connected Semiconductor Group 2 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM P-SOJ-42 (400 mil) Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS A11/NC A10/NC A0 A1 A2 A3 Vcc 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 P-TSOPII-50/44 (400mil) Vcc Vss I/O1 I/O16 I/O2 I/O3 I/O15 I/O4 I/O14 Vcc I/O13 I/O5 Vss I/O6 I/O12 I/O7 I/O11 I/O8 I/O10 N.C. I/O9 N.C. LCAS N.C. UCAS N.C. OE WE A9 RAS A11/N.C. A8 A10.N.C. A7 A0 A6 A1 A5 A2 A4 A3 Vss Vcc 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 N.C. 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 Vss *) A11 and A10 are not connected for HYB3118160BSJ/BST (1k-refresh version) Truth Table RAS LCAS UCAS WE OE I/O1-I/O8 I/O9-I/O16 Operation H H H H H High-Z High-Z Standby L H H H H High-Z High-Z Refresh L L H H L Dout High-Z Lower byte read L H L H L High-Z Dout Upper byte read L L L H L Dout Dout Word read L L H L H Din Don't care Lower byte write L H L L H Don't care Din Upper byte write L L L L H Din Din Word write L L L H H High-Z High-Z NOP Semiconductor Group 3 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM I/O1 I/O2 I/O16 WE UCAS LCAS & . . Data in Buffer No. 2 Clock Generator 16 Column Address Buffer(8) 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 8 Data out Buffer 16 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (12) 256 x16 12 Row 12 RAS Address Buffers(12) 12 Row Decoder 4096 No. 1 Clock Generator Block Diagram for HYB 3116160BSJ Semiconductor Group OE 4 Memory Array 4096x256x16 16 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM I/O1 I/O2 I/O16 WE UCAS LCAS . . & Data in Buffer No. 2 Clock Generator 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 16 Column Address Buffer(10) 10 Data out Buffer 16 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (10) 1024 x16 10 Row 10 RAS Address Buffers(10) Row Decoder 1024 10 No. 1 Clock Generator Block Diagram for HYB 3118160BSJ Semiconductor Group OE 5 Memory Array 1024x1024x16 16 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 °C Storage temperature range.........................................................................................– 55 to 150 ° C Soldering time.............................................................................................................................10 s Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage..................................................................................................-0.5 V to 4.6 V Power dissipation..................................................................................................................... 1.0 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics (values in brackets for HYB3116160BSJ) TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.0 Vcc+0.5 V 1) Input low voltage VIL – 0.5 0.8 V 1) TTL Output high voltage (IOUT = – 2 mA) VOH 2.4 – V 1) TTL Output low voltage (IOUT = 2 mA) VOL – 0.4 V 1) CMOS Output high voltage (IOUT = – 100 µA) VOH Vcc-0.2 – V 1) CMOS Output low voltage (IOUT = 100 µA) VOL – 0.2 V 1) Input leakage current,any input (0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V) IO(L) – 10 10 µA 1) Average VCC supply current: ICC1 – – – 200(100) mA 180 (90) mA 160 (80) mA 2) 3) 4) – 2 – -50 ns version -60 ns version -70 ns version 2) 3) 4) 2) 3) 4) (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) ICC2 Semiconductor Group 6 mA HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM DC Characteristics (values in brackets for HYB3116160BSJ) (cont’d) TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version Symbol Limit Values Unit Test Condition min. max. – – – 200(100) mA 180 (90) mA 160 (80) mA – – – 55 (40) 50 (35) 45 (30) mA mA mA 2) 3) 4) ICC3 2) 4) 2) 4) 2) 4) (RAS cycling: CAS = VIH, tRC = tRC min.) Average VCC supply current, during fast page mode: -50 ns version -60 ns version -70 ns version ICC4 2) 3) 4) 2) 3) 4) (RAS = VIL, CAS, address cycling, tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 – 1 mA 1) Standby VCC supply current (L-version) (RAS = CAS = VCC – 0.2 V) ICC5 – 200 µA 1) Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version ICC6 – – – 200(100) mA 180 (90) mA 160 (80) mA _ 1 250 2) 4) 2) 4) 2) 4) (RAS, CAS cycling, tRC = tRC min.) Average Self Refresh Current ICC7 (CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc--0.2V or 0.2V) mA µA L-version Capacitance TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A11) CI1 – 5 pF Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2 – 7 pF I/O capacitance (I/O1-I/O16) CIO – 7 pF Semiconductor Group 7 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter 16F Limit Values Symbol -50 Unit Note -60 -70 min. max. min. max. min. max. common parameters Random read or write cycle time tRC 90 – 110 – 130 – ns RAS precharge time tRP 30 – 40 – 50 – ns RAS pulse width tRAS 50 10k 60 10k 70 10k ns CAS pulse width tCAS 13 10k 15 10k 20 10k ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 8 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 10 – 15 – 15 – ns RAS to CAS delay time tRCD 18 37 20 45 20 50 RAS to column address delay time tRAD 13 25 15 30 15 35 ns RAS hold time tRSH 13 15 – 20 – ns CAS hold time tCSH 50 60 – 70 – ns CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 3 50 3 50 3 50 ns Refresh period for HYB3118160 tREF – 16 – 16 – 16 ms Refresh period for HYB3116160 tREF – 64 – 64 – 64 ms Refresh period for L-versions tREF – 256 – 256 – 256 ms Access time from RAS tRAC – 50 – 60 – 70 ns 8, 9 Access time from CAS tCAC – 13 – 15 – 20 ns 8, 9 Access time from column address tAA – 25 – 30 – 35 ns 8,10 OE access time – 13 – 15 – 20 ns Column address to RAS lead time tRAL 25 – 30 – 35 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 7 Read Cycle Semiconductor Group tOEA 8 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter 16F Limit Values Symbol -50 Unit Note -60 -70 min. max. min. max. min. max. CAS to output in low-Z tCLZ 0 – 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 0 20 ns 12 Output buffer turn-off delay from OE tOEZ 0 13 0 15 0 20 ns 12 Data to OE low delay tDZO 0 – 0 – 0 – ns 13 CAS high to data delay tCDD 13 – 15 – 20 – ns 14 OE high to data delay tODD 13 – 15 – 20 – ns 14 Write command hold time tWCH 8 – 10 – 10 – ns Write command pulse width tWP 8 – 10 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – 20 – ns Write command to CAS lead time tCWL 13 – 15 – 20 – ns Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 10 – 10 – 15 – ns 16 Data to CAS low delay tDZC 0 – 0 – 0 – ns 13 Read-write cycle time tRWC 126 – 150 – 180 – ns RAS to WE delay time tRWD 68 – 80 – 95 – ns 15 CAS to WE delay time tCWD 31 – 35 – 45 – ns 15 Column address to WE delay time tAWD 43 – 50 – 60 – ns 15 OE command hold time tOEH 13 – 15 – 20 – ns Fast page mode cycle time tPC 35 – 40 – 45 – ns CAS precharge time tCP 10 – 10 – 10 – ns Access time from CAS precharge tCPA – 30 – 35 – 40 ns RAS pulse width tRAS 50 200k 60 Write Cycle 15 Read-Modify-Write Cycle Fast Page Mode Cycle Semiconductor Group 9 200k 70 200k ns 7 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter 16F Limit Values Symbol -50 CAS precharge to RAS Delay tRHPC Unit Note -60 -70 min. max. min. max. min. max. 30 – 35 – 40 – ns Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle time tPRWC 71 – 80 – 95 – ns CAS precharge to WE tCPWD 48 – 55 – 65 – ns CAS setup time tCSR 10 – 10 – 10 – ns CAS hold time tCHR 10 – 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – 10 – ns tCPT 35 – 40 – 40 – ns RAS pulse width tRASS 100k _ 100k _ 100k _ ns 17 RAS precharge time tRPS 95 _ 110 _ 130 _ ns 17 CAS hold time tCHS -50 _ -50 _ -50 _ ns 17 CAS-before-RAS Refresh Cycle CAS-before-RAS Counter Test Cycle CAS precharge time Self Refresh Cycle Semiconductor Group 10 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 100 pF and at Voh=2.0 V (Ioh = -2mA) , Vol=0.8V (Iol=2mA). 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)Either tDZC or tDZO must be satisfied. 14)Either tCDD or tODD must be satisfied. 15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. Semiconductor Group 11 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRC tRAS tRP V IH RAS VIL tCSH V IH UCAS LCAS VIL tRAD tASR Address AAAAAAAA AAAA IH AAAA AAAAAAAA VIL AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAA AAAA AAAAAAA AAAAAAA Row tRAH tRAL tCAH tASC V tCRP tRSH tCAS tRCD tASR AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA tRCH Column tRCS tRRH V WE AAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAA AAAA IH AAAA AAAAAAAA AAAAAAAA AA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AA AAAA AAAA AAAAAA V AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAA tAA IL OE tOEA V AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAA IHAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAA AAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAA VIL AAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCDD tDZC I/O (Inputs) tODD tDZO V AAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tCAC tCLZ V OH I/O (Outputs) V Row Hi Z OL tOFF AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA A AAAA A AAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAA tOEZ AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AA AAAA AAAAAA AAAAAA Valid Data Out Hi Z tRAC AAAA AAAAAAA AAA AAAA AAA AAAAAAA AAAAAAA AAAA AAAAAAA AAA WL1 “H” or “L” Read Cycle Semiconductor Group 12 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD tRSH tCAS V IH UCAS LCAS VIL tRAD tASR V Address AAAAAAA AAAA AAA AAAA AAAAAAA AAA IH AAAA AAAAAAA AAA VIL tRAL AAA AAAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA tRAH V WE tASR AAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAA AAAAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA AAAA AAAAAAAA AAAA AA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA . Row tCWL tWCS AAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL tCAH tASC Row tCRP t WP AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA A AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA A AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA A AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWCH tRWL OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDS I/O (Inputs) tDH V IH Valid Data In VIL V OH I/O (Outputs) V Hi Z OL AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA WL2 “H” or “L” Write Cycle (Early Write) Semiconductor Group 13 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD V IH UCAS LCAS VIL tRAD tASR tCAH tASC V AAAAAAAAA AAAAA IHAAAA AAAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA Row Address V AAAA AAAAAAAA AAAAAAAAA IL AAAAAAAAA tRAL Column tASR AAAA AAAAAAAA AAAA AAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL tRAH V WE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tCRP tRSH tCAS tRWL tWP AA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA . Row AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEH V OE IH AAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAA tODD tDS tOEZ tDZO tDZC I/O (Inputs) V AAAAAAAAA IH AAAA AAAAAAAA AAAAAAAAAAAAA VIL AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA A AAAA AAAA AAAA AAAAA AAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAA tCLZ tOEA V OH I/O (Outputs) V Hi-Z OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAA A AAAA AAAAA A AAAA A AAAAA AAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA “H” or “L” Valid Data AAAAAAAA AAAAAAAAAAA AAAA AAAAAAAA AAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Hi-Z WL3 Write Cycle (OE Controlled Write) Semiconductor Group AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tDH 14 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRWC tRAS tRP V IH RAS tCSH VIL tRSH tCAS tRCD V tCRP IH UCAS LCAS VIL tRAH tCAH V AA IH AAA AAA AAAA Address AA AAA AAA AAAA VIL Row tASR tASC tASR AAAAAA AA AAAA AAAAAA AA AAAA AA AAAA AAAAAA AAAAAAAA AAAAAAAA AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA t CWL tAWD Column tRAD tCWD tRWL tRWD V WE Row tWP AAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA IH AAA AAAA AAA AAAA AAAAAAAA AAAAAAA AAAAAAAA AAAAAAAA AAA AAAA AAAA AAAA AAA VIL AAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAA AAAAAAAA AAAA AA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAAAAA AAAA AAAAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAA tAA tRCS tOEH tOEA V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OE VIL AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDS tDZO tDZC tDH V I/O (Inputs) AAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAA AAAAAAAA AAAAAAAA AAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA A AAAAA AAAA AAAA AAAA AAAAAAAA A AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAAAAAA AAA AAAA AAAAAAA AAA AAAA AAAAAAA AAAAAAA tCLZ Valid Data in AAAAAAA AAAAAAAA AAAA AAA AAAAAAAA AAAAAAAA AAA AAAA AAAAAAAA AAAA AAAAAAA AAAA AAAAAAAA AAAAAAA AAAAAAAA AAAA AAA AAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA tODD tCAC tOEZ V OH AAAA AA AAAA AA Data AAAA AA AAAA AA AAAA AAAAAA AA Out I/O (Outputs) VOL tRAC AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL4 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 15 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRP tRASP V IH RAS VIL tRHCP tRSH tCAS tPC tCAS tCP tCAS tRCD V tCRP IH UCAS LCAS VIL tCSH tRAH tASR V Address tCAH tASC tASC AAAA AA IH AAAA AAAA AAAAAA AAAA AA Row AAAA A AAAA AAAA A AAAAAAA VIL AAAA AAAAA AAAA tRAD AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA Column AAAAAAAA AAAAAAAAAA AA Column tRCH WE AAAAAAAAAAAAAAA AAAAAAA AAAAAAAA AAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAAAAAAAA A AAAA AAAAA A AAAA AAAAA A AAAA AAAAA AAAAA AAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAA VIL tAA V OE AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA VIL AAAAAAAA AAAAAAA AAAAAAAAAAAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAA V AAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAA VIL AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tCAC tRAC tCLZ V OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAA A AAAA AAAAA A AAAA AAAAA AAAAA A AAAA tOFF tOEZ AAAAA AAAAA AAAAA Valid AAAAA AAAAA Data Out AAAAA AAAAA OH I/O (Outputs) V tODD tCAC tCLZ AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA AAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAA AAAA tCDD tDZO AAAAA AA AAA AAAAA AA AAA AAAAA AAAAA AA AAA tOFF tOEZ tDZC AAAAAAA AAAA AAA AAAAAAAA AAAAAAA AAAA AAA AAAAAAAA AAAAAAA AAAA AAAAAAAAAAA tRRHAAAAAAAAAAA tODD tCAC tCLZ AA AAAAAAAA AAAAAA AAAA AA AAAAAAAA AA AAAA AAAA AA AAAAAAAA AA AAAAAA AAAAAAAA AAAA tOFF tOEZ AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA “H” or “L” FPM1 Fast Page Mode Read Cycle Semiconductor Group AAAAAAAAAAAAA AAAA AAAAAAAA A AAAAAAAA AAAAAAAA AAAA AAAA A AAAAAAAA AAAA A AAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAA A tDZO tODD Row tRCH tCPA tAA tOEA tDZC tDZC tDZO I/O (Inputs) A AAAA AAAAA A AAAA AAAAA A AAAA AAAAA AAAAA tCPA tAA AAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAA AAAA AAAA AAA AAAA AAAA AAA AAAA AAAA AAAAAAA AAA AAAA AAAAAAAA AAA AAAAAAAAAAA tRCS tOEA tOEA tASR tASC AAAA AAAA A AAAA AAAA A AAAA AAAA AAAAA A Column AAAA AAAAAAAA A AAAAAAAAA tRCS tRCS V tCAH tCAH 16 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRP tRAS V IH RAS VIL tRSH tPC tRCD tCAS tCP tCAS tCAS tCRP V IH CAS VIL tRAL tRAH tCAH tASR V Address AAAAA AAAA A AAAA A AAAA AAAAAA IH AAAA AAAAAA VIL Row A AAAA AAAA AA AAAA AAAA A AAAA AAAAAA tASC tCWL tWCS AAAA AAAAAAAA AAAAA A tWP AAA AAAAAAAA AAAAAAAA AAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAA tWCS tWCH AAAA AAAAAAA AAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAA AAAA AAAAAAAA AAAAAAA AAA tWP AAAA AAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAA A AAAA AAAAAAAA AAAAAAAA AAAAA A tCWL tRWL tWCH tWP AAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tDH V AAA AAAAAAA AAAAAAAA AAAAAAAA IH AAAA AAAAAAAAAAAAAAA VIL AAAAAAA AAAAAAAA AAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAAAAAAAA Valid Data In tDH tDH tDS tDS I/O (Inputs) tASR tCAH AAAA AAAAAAAA AAAAAA AA tWCH AAAAAAA AAAAAAAA AAAAAAAAAAA AAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAA V OE AAAA AAAAAAAA AAAAAA AA tCWL V VIL tASC AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAA Column AAAA AAAAAA Column AAAA AAAAA Column Column AAAA AAAA AAAA AAAA AAAA AA AAAA AA AAAAA AAAA AAAA AAAA AA AA A AAAA AAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAA AAAAA tRAD tWCS WE tCAH tASC A AAAAA AAAAAAAA AAAA AAAAA AAAA A AAAAAAAA AAAAA AAAA A AAAAAAAA AAAAAAAAA Valid Data In tDS AAA AAAAAAA AAAAAAAA AAAA AAAAAAA AAAA AAA AAAAAAAA AAAAAAA AAAA AAA AAAAAAAA AAAAAAAAAAA Valid Data In AAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAA AAAAAAAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAA AAA AAAAAAAA AAAAAAAA AAAA AAAAAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA V OH I/O (Outputs) V HI-Z OL AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA “H” or “L” FPM2 Fast Page Mode Early Write Cycle Semiconductor Group 17 18 Data Out tDS tDH tOEZ tDS tDH Data Out tOEZ AAAAAA AA AAAA AAAA AAAAAA AA tDS Data Out “H” or “L” tRAC V OH I/O (Outputs) V AAA AAAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA OL tOEH tODD tOEZ tDH AAAA AA AAAA AAAAAA AA tCAC I/O (Inputs) V IL IH AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA V AAAAAA AAAAAA AAAAAA AAAAAA tAA tCLZ AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA tDZC tCLZ tDZO V IL IH OE V tAA tOEA tAWD V IL V IH AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA tCAC A AAAA AAAAA AAAAA Data In tCPA tDZC tOEA tAWD tWP AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAAAA AAAA AAAAAA tOEH Data In AA AAAA AA AAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA tODD tDZC tCLZ tCPA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA AAAA AAAAA A AAAA A tAA Data In tODD tWP tOEA tWP tCWL tAWD tCPWD tCWD tCPWD tCWD tCWL tRWD tCWD Row V IL V IH AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAAAA Address tASR AAAA AA AAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AA AAAA AAAAAA AAAAAA AA AAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAAA A AAAA AAAAA WE tASC Column tCAH tRAH tRAD V IL IH UCAS LCAS V AA AAAA AAAAAA AA AAAA AA AAAA AAAAAA tRCS tASC Column Address tCAH tCP AA AAAA AA AAAAAA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AA AAAAAA AAAA AAAAAA AAAAAA AAAAAA tCAS tCSH tRCD V IL IH RAS Column tASC tPRWC tCAS tRAS V AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA tRWL tCWL Row tASR tRAL tCAH tCAS tRSH tCRP tRP AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AAAAAA AA AAAA AA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA Fast Page Mode Read-Modify- Write Cycle Semiconductor Group AAAA AAAAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA AA AAAA AA AAAA AAAAAA AAAAAA AA tOEH HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRC tRAS tRP V IH RAS VIL tCRP tRPC V CAS AAAAA AAAA A AAAAA AAAAAAAA AAAA A AAAA AAAA AAAA AAAAA A AAAA AAAA AAAAAAAAA IH VIL tRAH tASR tASR V Address AAAA IH AAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAA VIL AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAA Row A AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA A AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OH I/O (Outputs) V HI-Z OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA “H” or “L” WL9 RAS-Only Refresh Cycle Semiconductor Group 19 Row HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRC tRP V RAS tRAS IH VIL tRPC tCSR tCRP tCP tRPC tCHR V UCAS LCAS tRP AAAAAA AAAAAA AAAAAA AAAAAA AA AAAA AAAAAA AAAAAA IH VIL tWRP tWRH V WE AAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAA VIL AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAA AAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEZ V AA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH OE VIL tCDD V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH I/O (Inputs) V IL tODD V OH I/O (Outputs)VOL HI-Z tOFF AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL10 CAS-Before-RAS Refresh Cycle Semiconductor Group 20 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRC tRC RAS tRP tRAS V tRP tRAS IH VIL tRSH tRCD tCRP tCHR V UCAS LCAS IH tRAD VIL tWRP tASC tASR Address V AAAAAAA IHAAAA AAA AAAAAAA AAAAAAA AAA VIL AAAA AAA AAAA AAAAAAA tRAH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAA AA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAA Column AAAA AA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA Row AAAA AAAA AAAA AAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row tRRH tRCS WE tASR tWRH tCAH V AAAAAAAAAAAAAAAA AAAAAAAA IHAAAA AAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA VIL AAAA AAAAAAAAAAAA AAAAAAAA AAAA AAAAAA AA AAAA AAAAAA AA AA AAAA AAAAAA AAAAAA tAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tOEA OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAA VIL AAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC tCDD tDZO V I/O (Inputs) IH VIL AAAA AAAAAAAAAAAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA tODD tCAC tOFF tCLZ tOEZ tRAC V A AAAAA AAAA A AAAA A AAAA AAAA AAAAA A OH I/O (Outputs) V OL AAAA AAA AAAA AAAAAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA Valid Data Out “H” or “L” HI-Z WL11 Hidden Refresh Cycle (Read) Semiconductor Group AAAA AAAAAAAAAAAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAA 21 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRC tRC tRP tRAS V RAS IH tRAS tRP VIL tRCD tRSH tCHR tCRP V UCAS LCAS IH VIL tRAD tRAH tASC tCAH tASR Address V AAAAAAA IHAAAAAAA AAAA AAAAAAA AAA Row VIL AAAA AAAAAAA AAA AA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAA AAAA AA AAAAAAAA AA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAAAA AAAAAA Column AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWCS tWRP tWRH tWCH tWP V WE AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAA AAA IH AAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAA AAA AAAAAAAA AAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAA tDS I/O (Input) tASR V AAAAAAAAAAAAAAA IHAAAA AAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAA AAA AAAAAAAAAAAA AAA AAAA V AAAA IL AAAAAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAAAAAA AAAA AAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAAAAAA AAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA tDH Valid Data AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OH I/O (Output) V OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA HI-Z “H” or “L” WL12 Hidden Refresh Cycle (Early Write) Semiconductor Group Row 22 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRP tRASS tRPS V RAS IH VIL tRPC tCP V CAS A AAAAAAAA AAAAA AAAA AAAAA AAAA A AAAA AAAA AAAA AAAAA A AAAA AAAAAAAA AAAAA IH VIL tCRP tCHS tCSR tWRP tWRH V WE AAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAA VIL AAA AAAAAAAA AAAA AAAA AAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAA V AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH OE AAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA A AAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA A AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA A AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL tCDD V AAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAA IH I/O (Inputs) V IL tODD tOEZ V OH I/O (Outputs) V OL HI-Z tOFF AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL13 CAS before RAS Self Refresh Cycle Semiconductor Group 23 HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM tRP tRAS Read Cycle: RAS V IH V IL tRSH tCAS tCP tCHR tCSR CAS V IH V IL Address tRAL V IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tASC AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA WE OE I/O (Inputs) I/O (Outputs) AAAAAAAAAAAAA AAAAAAAAAAAAA V IL AAAAAAAAAAAAA tWRH tDZC AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tODD tDZO tCLZ VOH VOL AA AAAAAA AAAA AAAAAA AA AAAA AAAAAA tWCS tWRP Write Cycle: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA V IL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAA V IL AAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA tRCH AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAA tOEA tRCS V IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAA V IHAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAAAAAA A AAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAA Row tRRH tAA tCAC AAAAAA AAAAAAAA AAAA AA AAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAA tASR AAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Column tWRP AAAAAAAAA V IHAAAA AAAAAAAAAAAAA tCAH tRWL tCWL tOEZ tCDD AA AAAA AAAA AAAA AAAA AAAAAA AAAA AAAA AA AAAA AAAA AAAA AA AAAA AAAA AA AAAAAAAA AAAAAAAA AAAAAA tOFF AAAA Data Out AAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA WE V IH AAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA V IL AAAA AAAAAAAAAAAA OE AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA V IH AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA V IL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA I/O (Inputs) V IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA V IL AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA I/O (Outputs) V IH V IL tWRH tDS HI-Z CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group tWCH 24 tDH Data In AAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA HYB3116(8)160BSJ/BST(L)-50/-60/-70 3.3V 1M x 16-DRAM Package Outlines 0.81 max. 1.27 0.43 + - 0.1 0.18 1) 10.3 -0.3 9.4 0.08 A 42x +- 0.25 11.2 + - 0.15 25.4 42 22 1 GPJ05853 21 1) 27.43 -0.25 A Index marking 1) does not include plastic or metal protusion of 0.15 max per side Plastic Package P-TSOPII-50/44 (400 mil) (Thin Small Outline, SMD, 0.8 mm lead pitch) Semiconductor Group 25 B 0.2 +0.12 -0.05 0.8 min. 2.08 min. 3.75 max. Plastic Package P-SOJ-42 (400 mil) (Small Outline J-lead, SMD) 0.18 B