4M x 16-Bit Dynamic RAM HYB 3164165AT(L) -40/-50/-60 HYB 3165165AT(L) -40/-50/-60 HYB 3166165AT(L) -40/-50/-60 (8k, 4k & 2k Refresh, EDO-Version) Advanced Information • • • • • • • • • • • 4 194 304 words by 16-bit organization 0 to 70 °C operating temperature Hyper Page Mode - EDO - operation Performance: -40 -50 -60 tRAC RAS access time 40 50 60 ns tCAC CAS access time 10 13 15 ns tAA Access time from address 20 25 30 ns tRC Read/write cycle time 69 84 104 ns tHPC Hyper page mode (EDO) cycle time 16 20 25 ns Single + 3.3 V (± 0.3V) power supply Low power dissipation: -40 -50 -60 HYB3166165AT(L) 1008 612 450 mW HYB3165165AT(L) 756 504 360 mW HYB3164165AT(L) 612 324 324 mW 7.2 mW standby (TTL) 3.24 mW standby (MOS) 720 µA standby for L-version Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and Self Refresh (L-version only 2 CAS / 1 WE byte control 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165AT) 4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165AT) 2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165AT) 256ms refresh period for L-versions Plastic Package: P-TSOPII-50 400 mil Semiconductor Group 1 6.97 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM This device is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated on an advanced first generation 64Mbit 0,35 µm CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)165AT operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB3164(5/6)165AT to be packaged in 400mil wide TSOPII-50 package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB3164(5/6)165ATL parts have a very low power „sleep mode“ supported by Self Refresh. Ordering Information Type Ordering Code Package Descriptions 8k-refresh versions: HYB 3164165AT-40 P-TSOPII-50 400 mil EDO-DRAM (access time 40 ns) HYB 3164165AT-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns) HYB 3164165AT-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns) HYB 3164165ATL-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns) HYB 3164165ATL-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns) HYB 3165165AT-40 P-TSOPII-50 400 mil EDO-DRAM (access time 40 ns) HYB 3165165AT-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns) HYB 3165165AT-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns) HYB 3165165ATL-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns) HYB 3165165ATL-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns) HYB 3166165AT-40 P-TSOPII-50 400 mil EDO-DRAM (access time 40 ns) HYB 3166165AT-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns) HYB 3166165AT-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns) HYB 3166165ATL-50 P-TSOPII-50 400 mil EDO-DRAM (access time 50 ns) HYB 3166165ATL-60 P-TSOPII-50 400 mil EDO-DRAM (access time 60 ns) 4k-refresh versions: 2k-refresh versions: Semiconductor Group 2 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM Pin Configuration P-TSOPII-50 (400 mil) O VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 N.C. VCC WE RAS N.C. N.C. N.C. N.C. A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 . 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 N.C. VSS . LCAS UCAS OE N.C. N.C. A12/N.C. * A11/N.C.** A10 A9 A8 A7 A6 VSS * Pin 33 is A12 for HYB 3164165AT(L) and N.C. for HYB 3165(6)165AT(L) ** Pin 32 is A11 for HYB 3164(5)165AT(L) and N.C. for HYB 3166165AT(L) Pin Names A0-A12 Address Inputs for 8k-refresh version HYB 3164165T(L) A0-A11 Address Inputs for 4k-refresh version HYB 3165165T(L) A0-A10 Address Inputs for 2k-refresh version HYB 3166165T(L) RAS Row Address Strobe OE Output Enable I/O1-I/O16 Data Input/Output UCAS, LCAS Column Address Strobe WE Read/Write Input Vcc Power Supply ( + 3.3V) Vss Ground Semiconductor Group 3 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM TRUTH TABLE RAS LCAS UCAS WE OE ROW ADD COL ADD I/O1I/O16 Standby H H-X H-X X X X X High Impedance Read:Word L L H H L ROW COL Data Out Read:Lower Byte L L H H L ROW COL Lower Byte:Data Out Upper-Byte:High-Z Read:Upper Byte L H L H L ROW COL Lower Byte:High-Z Upper Byte:Data Out Write:Word (Early-Write) L L L L X ROW COL Data In Write:Lower Byte (Early-Write) L L H L X ROW COL Lower Byte:Data Out Upper-Byte:High-Z Write:Upper Byte (Early Write) L H L L X ROW COL Lower Byte:High-Z Upper Byte:Data Out Read-ModifyWrite L L L H-L L - H ROW COL Data Out, Data In Hyper Page Mode 1st Read (Word) Cycle L H-L H-L H L ROW COL Data Out Hyper Page Mode 2nd Read (Word) Cycle L H-L H-L H L n/a COL Data Out Hyper Page Mode 1st Early Write(Word) Cycle L H-L H-L L X ROW COL Data In Hyper Page Mode 2nd Early Write(Word) Cycle L H-L H-L L X n/a COL Data In Hyper Page Mode 1st RMW Cycle L H-L H-L H-L L - H ROW COL Data Out, Data In Hyper Page Mode 2st RMW Cycle L H-L H-L H-L L - H n/a COL Data Out, Data In RAS only refresh L H H X X ROW n/a High Impedance CAS-before-RAS refresh H-L L L H X X n/a High Impedance Test Mode Entry H-L L L L X X n/a High Impedance Hidden Refresh (Read) L-H- L L L H L ROW COL Data Out Hidden Refresh (Write) L-H- L L L L X ROW COL Data In Self Refresh (L-version only) H-L H X X X X High Impedance FUNCTION Semiconductor Group L 4 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM I/O1 I/O2 I/O16 WE UCAS LCAS & . . Data in Buffer No. 2 Clock Generator 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 16 Column Address Buffer(9) 9 Data out Buffer 16 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (13) 512 x16 13 Row 13 RAS Address Buffers(13) Row Decoder 8192 13 No. 1 Clock Generator Block Diagram for HYB 3164165AT(L) Semiconductor Group OE 5 Memory Array 8192x512x16 16 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM I/O1 I/O2 I/O16 WE UCAS LCAS & . . Data in Buffer No. 2 Clock Generator 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 16 Column Address Buffer(10) 10 Data out Buffer 16 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (12) 1024 x16 12 Row 12 RAS Address Buffers(12) Row Decoder 4096 12 No. 1 Clock Generator Block Diagram for HYB 3165165AT(L) Semiconductor Group OE 6 Memory Array 4096x1024x16 16 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM I/O1 I/O2 I/O16 WE UCAS LCAS & . . Data in Buffer No. 2 Clock Generator 11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 16 Column Address Buffer(11) 11 Data out Buffer 16 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (11) 2048 x16 11 Row 11 RAS Address Buffers(11) Row Decoder 2048 11 No. 1 Clock Generator Block Diagram for HYB3166165AT(L) Semiconductor Group OE 7 Memory Array 2048x2048x16 16 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 °C Storage temperature range.........................................................................................– 55 to 150 °C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.3 W Data out current (short circuit)..................................................................................................50 mA Note Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. DC Characteristics TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Note Input high voltage VIH 2.0 Vcc+0.3 V 1) Input low voltage VIL – 0.3 0.8 V 1) Output high voltage (LVTTL) Output „H“ level voltage (Iout = -2mA) VOH 2.4 – V Output low voltage (LVTTL) Output „L“level voltage (Iout = +2mA) VOL – 0.4 V Output high voltage (LVCMOS) Output „H“ level voltage (Iout = -100uA) VOH Vcc-0.2 - V Ouput low voltage (LVCMOS) Output „L“ level voltage (Iout = +100uA) VOL - 0.2 V Input leakage current,any input II(L) –2 2 µA IO(L) –2 2 µA (0 V < Vin < Vcc , all other pins = 0 V Output leakage current (DO is disabled, 0 V < Vout < Vcc ) Semiconductor Group 8 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM DC-Characteristics (cont’d) TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V Parameter Symbol refresh version 2k 4k Unit Note 8k ICC1 Operating Current -40 ns version -50 ns version -60 ns version 280 230 185 170 140 115 125 100 85 mA mA mA 2) 3) 4) 2 2 2 mA – 280 230 185 170 140 115 125 100 84 mA mA mA 2) 4) 140 105 85 140 105 85 140 105 85 mA mA mA 2) 3) 4) ICC5 900 900 900 µA – ICC5 200 200 200 µA – CAS Before RAS Refresh Current ICC6 -40 ns version -50 ns version -60 ns version 280 230 185 170 140 115 170 140 115 mA mA mA 2) 4) 400 400 400 µA - (RAS, CAS, address cycling: tRC = tRC min.) Standby Current (RAS=CAS= Vih) ICC2 RAS Only Refresh Current: - ICC3 -40 ns version -50 ns version -60 ns version (RAS cycling: CAS = VIH: tRC = tRC min.) Hyper Page Mode (EDO) Current: ICC4 -40 ns version -50 ns version -60 ns version (RAS = VIL, CAS, address cycling: tHPC=tHPC min.) Standby Current (RAS=CAS= Vcc-0.2V) Standby Current (L-Version) (RAS=CAS= Vcc-0.2V) (RAS, CAS cycling: tRC = tRC min.) Self Refresh Current (L-version only) ICC7 (CBR cycle with tRAS>TRASSmin, CAS held low, WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V) Capacitance TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A11,A12) CI1 – 5 pF Input capacitance (RAS, CAS, WE, OE) CI2 – 7 pF I/O capacitance (I/O1-I/O16) CIO – 7 pF Semiconductor Group 9 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns Parameter AC64-2E Limit Values Symbol - 40 - 50 Unit Note - 60 min. max. min. max. min. max. Common Parameters Random read or write cycle time tRC 69 – 84 – 104 – ns RAS pulse width tRAS 40 100k 50 100k 60 100k ns CAS pulse width tCAS 6 100k 8 100k 10 100k ns RAS precharge time tRP 25 – 30 – 40 – ns CAS precharge time tCP 6 – 8 – 10 – ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 5 – 7 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 5 – 7 – 10 – ns RAS to CAS delay time tRCD 9 30 11 37 14 45 ns RAS to column address delay time tRAD 7 20 9 25 12 30 ns RAS hold time tRSH 6 – 8 10 – ns CAS hold time tCSH 32 – 40 48 – ns CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 1 50 1 50 1 50 ns Refresh period for 8k-refresh-version tREF – 128 – 128 – 128 ms Refresh period for 4k-refresh version tREF – 64 – 64 – 64 ms Refresh period for L-versions tREF – 256 – 256 – 256 ms Access time from RAS tRAC – 40 – 50 – 60 ns 8, 9 Access time from CAS tCAC – 10 – 13 – 15 ns 8, 9 Access time from column address tAA – 20 – 25 – 30 ns 8,10 OE access time tOEA – 10 – 13 – 15 ns Column address to RAS lead time tRAL 20 – 25 – 30 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 7 Read Cycle Semiconductor Group 10 11 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns Parameter AC64-2E Limit Values Symbol - 40 - 50 Unit Note - 60 min. max. min. max. min. max. Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 10 0 13 0 15 ns 12 Output buffer turn-off delay from OE tOEZ 0 10 0 13 0 15 ns 12 Data to CAS low delay tDZC 0 – 0 – 0 – ns 13 Data to OE low delay tDZO 0 – 0 – 0 – ns 13 CAS high to data delay tCDD 10 – 13 – 15 – ns 14 OE high to data delay tODD 10 – 13 – 15 – ns 14 Write command hold time tWCH 5 – 7 – 10 – ns Write command pulse width tWP 5 – 7 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns Write command to RAS lead time tRWL 6 – 8 – 10 – ns Write command to CAS lead time tCWL 6 – 8 – 10 – ns Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 5 – 7 – 10 – ns 16 Read-write cycle time tRWC 89 – 109 – 133 – ns RAS to WE delay time tRWD 52 – 65 – 77 – ns 15 CAS to WE delay time tCWD 22 – 28 – 32 – ns 15 Column address to WE delay time tAWD 32 – 40 – 47 – ns 15 OE command hold time tOEH 5 – 7 – 10 – ns Hyper page mode (EDO) cycle time tHPC 16 – 20 – 24 – ns Access time from CAS precharge tCPA – 22 – 27 – 32 ns Output data hold time tCOH 3 – 5 – 5 – ns Write Cycle 15 Read-modify-Write Cycle Hyper Page Mode (EDO) Cycle Semiconductor Group 11 7 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns Parameter AC64-2E Limit Values Symbol - 40 - 50 Unit Note - 60 min. max. min. max. min. max. RAS pulse width in hyper page mode tRAS 40 200k 50 200k 60 200k ns CAS precharge to RAS Delay tRHPC 22 – 27 – 32 – ns OE pulse width tOEP 5 – 5 – 5 – ns OE hold time from CAS high tOEHC 5 – 5 – 5 – ns Output buffer turn-off delay from WE tWEZ 0 10 0 13 0 15 ns OE setup time prior to CAS tOES 5 – 5 – 5 – ns Hyper page mode (EDO) read-write cycle time tPRWC 44 – 54 – 63 – ns CAS precharge to WE tCPWD 34 – 42 – 49 – ns CAS setup time tCSR 5 – 5 – 5 – ns CAS hold time tCHR 5 – 5 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – 5 – ns Write to RAS precharge time tWRP 5 – 5 – 10 – ns Write hold time referenced to RAS tWRH 5 – 5 – 10 – ns 100k _ 100k _ ns 17 Hyper Page Mode (EDO) Readmodify-Write Cycle CAS before RAS Refresh Cycle Self Refresh Cycle (L-versions only) RAS pulse width tRASS 100k RAS precharge time tRPS 69 – 84 – 104 – ns 17 CAS hold time tCHS -50 – -50 – -50 – ns 17 Semiconductor Group 12 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM Notes: 1) All voltages are referenced to VSS. Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. 2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a Hyper page mode cycle ( thpc). 5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh. If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh Semiconductor Group 13 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRAS tRP V IH RAS VIL tCSH UCAS LCAS V IH VIL tRAD tASR V Address AAA AAAAAAA IH AAAA AAAAAAA AAAA AAAAAAA AAA AAAAAAA VIL Row tRAL tCAH tASC AAAAAAA AAAAAAA AAAAAAA AAAA AAAAAAA AAA AAAAAAA tCRP tRSH tCAS tRCD tASR AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAA Column tRCH tRAH tRCS tRRH V WE OE I/O (Inputs) Row AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tAA tOEA IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA tCDD tDZC tODD tDZO V AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tCAC tCLZ V OH I/O (Outputs) V Hi Z OL tOFF AAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA tOEZ AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA Valid Data Out Hi Z tRAC AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA WL1 “H” or “L” Read Cycle Semiconductor Group 14 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD UCAS LCAS V IH VIL tRAD tASR V Address IH VIL AAAA AAAAAAA AAA AAAA AAAAAAA AAA AAAA AAAAAAA AAA V AAAA AAAAAAA AAA AAAA AAAAAAA AAA AAAA AAAAAAA AAA tASR AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAA Column AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA . Row tCWL tWCS AAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL tCAH tASC Row tCRP tRAL tRAH WE tRSH tCAS t WP AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA tWCH tRWL OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA tDS I/O (Inputs) tDH V IH Valid Data In VIL V OH I/O (Outputs) V Hi Z OL AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA WL2 “H” or “L” Write Cycle (Early Write) Semiconductor Group 15 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD UCAS LCAS V IH VIL tRAD tASR tCAH tASC V AAAAAAAAA IHAAAA AAAAAAAA AAAAA A AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA Address V AAAA AAAAAAAA AAAAA A Row AAAAAAAAA IL AAAAAAAAA tRAL Column tASR AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tCWL tRAH V WE tCRP tRSH tCAS AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA VIL AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tRWL tWP AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA . Row AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tOEH V OE IH AAAAAAAAAAAAAAAAAAAAAAA VIL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA tODD tDS tOEZ tDZO tDZC I/O (Inputs) V IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA VIL AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AA tCLZ tOEA V OH I/O (Outputs) V Hi-Z OL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” Valid Data AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAA Hi-Z WL3 Write Cycle (OE Controlled Write) Semiconductor Group AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tDH 16 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRWC tRAS tRP V IH RAS tCSH VIL UCAS LCAS tRSH tCAS tRCD V IH VIL tRAH tCAH V IH AAA AAAA A AAAA Address VIL AAAA AAA AAAA A Row tASR tASC tASR AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tCWL tAWD Column tRAD tCWD tRWL tWP tRWD V WE tCRP AAAAAAAAAAAAAAAAAAA IH AAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA VIL AAA AAAAAAAAAAAAAAAAAAA AAAA Row AAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAA AA tAA tRCS tOEH tOEA V OE IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tDS tDZO tDZC tDH V I/O (Inputs) AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAA AAAA AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AA IH AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA tCLZ Valid Data in AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAA AAA tODD tCAC tOEZ V OH AAAA AA AAAA AA Data AAAA AAAAAA AA AAAA AAAAAA AA Out I/O (Outputs) VOL tRAC AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL4 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 17 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRP tRAS V tRHCP tRCD IH RAS VIL tRSH tHPC tCRP UCAS LCAS tCAS tCAS V IH VIL tCSH tRAH tASC tASR Address tCP tCAS tCRP V AAAAA IH AAAAA VIL AAAAA A AAAA AAAA AAAAA A tRAL tCAH tASC tCAH tASC tCAH AAA AAA AAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAA AAAAAA AA Column 2 AAAA AAAAAAAA AAAAAA AA Column N AAAA AAAAAAAA AAAAAA AAA Column 1 AAAA Row AAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA tRAD tRRH tRCH tRCS WE VIH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A VIL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tOES V OE OH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA V OL tCAC tAA tCAC tAA tCPA tCPA tOEA AAAAAAAA AAAAAA AA AAAA AAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAAAAAAAA AA tOFF AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAAAAAAAAAAAAA AAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA tRAC tAA tCAC tOEZ tCOH tCOH tCLZ V AAAA AAAA AAAA AAAA AAAA AAAA AAAA I/O IH (Output) V IL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA Data Out 1 Data Out 2 AAA AAA AAA AAA AAA AAA AAA Data Out N WL5 “H” or “L” Hyper Page Mode (EDO) Read Cycle Semiconductor Group AAAA AAAA AAAA AAAA AAAA AAAA AAAA 18 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRP tRAS V tRCD IH RAS tRHCP VIL tRSH tHPC tCRP tCAS tCP tCAS tCRP tCAS V IH UCAS LCAS VIL tCSH tRAH tASC tASR Address V AAAAA IH AAAAA VIL AAAA AAAAA A AAAA AAAAA A AAA tRAL AAA AAA Column 1 Row AAA AAA AAA tASC tCAH tASC tCAH tCAH AAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAAAAAAAA AA AAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAA AAAAAAAAAA AAAAAAAAA Column 2 AAAA AAAAAAAA AAAAAA AA Column N AAAA AAAAAAAA AAAAAA AAAAAAAAAA AAAAAAAAA tRAD tRRH tRCH tRCS WE VIH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A VIL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA tCAC OE t V AAAAAAAA AAAA AAAA AAAA AAAA AAAA AA OEA AAAA AAAA AAAA AAAA AAAA AAAA OH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA V OL tCPA tRAC tAA tCAC tCLZ V AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AA AAAA AAAA AAAAAA tOEP tOEHC AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAAAAAAAAAAAAA AAA tOEP tOEA tOEA tOEZ tOEZ Data Out 1 tOEZ AAA AAA AAA AAA AAA AAA AAA Data Out 2 AAA AAA AAA AAA AAA AAA AAA Data Out N WL6 “H” or “L” Hyper Page Mode (EDO) Read Cycle (OE Control) Semiconductor Group tOFF tCPA tOEHC AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA I/O IH (Output) V IL tAA tAA tOES AAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAA AA AAAA tCAC 19 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRP tRAS V tRCD IH RAS tRHCP VIL tRSH tHPC tCRP tCAS tCP tCAS tCRP tCAS V IH UCAS LCAS VIL tCSH tRAH tASC tASR Address V AAAAA IH AAAA AAAAA A VIL AAAAA A AAAA AAAA AAAAA A tRAL AAA AAA AAAAAAAAAA AAAA AAAAAAAA AAAAAA AA AAAAAAAAAA AAAA AAAAAAAA AAAAAA AA AAAAAAAAA AAAA AAAAAAAA AAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA Column 1 AAAA AAAAAAAA AAAAAA AA Column 2 AAAA AAAAAAAA AAAAAA AA Column N AAAA AAAAAAAA AAAAAA Row AAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA tRAD tRCS WE tAA tRCH tRRH tRCH tRCH tRCS AAAAAAAAA AAAAAAAA AAAAAA AAAA AAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAA AAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tWPZ tOES V OE tAA tRCS AAAAAAAAAAAAA VIH AAAA AAAAAAAAAAAAAAAAA VIL tASC tCAH tASC tCAH tCAH OH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA tCAC tCPA tWPZ tCAC tOFF tCPA tOEA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAAAAA AAA AAAA AAAA AAAAAAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA V AAAA AAAA AAAA AAAA AAAA AAAA AAAA OL tRAC tAA tCAC tOEZ tWEZ tWEZ tCLZ V AAAA AAAAAAA AAAA AAAA AA AAAA AAAA AAAAAA I/O IH (Output) V IL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA Data Out 1 Data Out 2 AAAA AAAA AAAA AAAA AAAA AAAA AAAA Data Out N WL7 “H” or “L” Hyper Page Mode (EDO) Read Cycle (WE Control) Semiconductor Group AAA AAA AAA AAA AAA AAA AAA 20 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRP tRAS V tRCD IH RAS tRHCP VIL tCRP tCAS tCRP tRSH tHPC tCP tCAS tCAS V IH UCAS LCAS VIL tCSH tASR Address tRAH tASC V AAAAA IHAAAAA Row AAAA AAAAA A Addr VIL AAAA AAAAA A AAA AAA AAA AAA AAA AAA tRAL AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAA Column 1 AAAA AAAAAAAA AAAAAA AA Column 2 AAAA AAAAAAAA AAAAAA Column N AAAA AAAA AA AAAA AAAAAAAAAA AAAAAAAA AAAAAA tRAD tWCS WE AAAAAAAAAAAAAAAA VIH AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA VIL tASC tCAH tASC tCAH tCAH tCWL tCWL tWCH tWCS tWCH tWP tWP AAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAAAAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA tRWL tCWL tWCS AAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAA tWCH tWP AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAA AA V OE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAA AAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAA A V OL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA OH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tDS V AAAAAAAAAAAAAAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAAAAAAAAAAAAA AAA IH AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA I/O (Input) V IL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA tDH tDS AAAAAAAAAA AAAAAAAA AA AAAA AA AAAA AAAA AA Data In 2 Data In 1 AAAA AAAA AAAA AAAAAAAAAA AA “H” or “L” tDS AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA tDH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A Data In N AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAA A WL8 Hyper Page Mode (EDO) Early Write Cycle Semiconductor Group tDH 21 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRP tRAS V tRCD IH RAS VIL tRSH tHPC tCRP tCAS tCP tCAS tCP tCRP tCAS V IH UCAS LCAS VIL tCSH V IH AAAA AAAAA A VIL AAAA AAAAA A AAAA AAAAA A tCAH tRAH tASC tASR Address tRAL tASC tCAH tASC tCAH AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAA Column 1 AAAA AAAAAAAA AAAAAA AA Column 2 AAAA AAAAAAAA AAAAAA AA Column N AAAA AAAAAAAA AAAAAA Row AAA AAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA tRAD tCWL tCWL tCWL tRWL tRCS tRCS WE OE tRCS VIH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A VIL AAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAA AA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA V AAAAAAAA AAA OH AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA tWP tWP tWP tOEH tOEH tOEH AAAA A AAAA AAAAAA AAAA AAAAAAA AAAA AAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AAA V AAAA AAAA AAAA AAA OL AAAAAAAAAAAAAAA AAAA A AAAA AAAAAA AAAA AAAAAAA AAAA AAAAA tODD tDS tDH AAA AAAA AAAA AAAA AAAA A AAA AAAA AAAA AAAA AAAA A AAA AAAA AAAA AAAA AAAA A AAA AAAA AAAA AAAA AAAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAA A tODD tDS tDS tDH tDH tODD I/O (Input) V AAAA A AAAA A AAAA A AAAA AAAAA A AAAA AAAAA A IH VIL AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA Data In 1 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Data In N WL16 “H” or “L” Hyper Page Mode (EDO) Late Write Cycle Semiconductor Group Data In 2 22 23 tDH tDS Data Out tCAC tAA tDS Data Out tOEZ tDS Data Out V OH I/O (Outputs) V tRAC OL tODD tOEZ tDH tOEH AAAA AA AAAA AA AAAA AAAAAA AA tCAC AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AAAAAA AA IH tDZC tCLZ tDZO V IH AAAA AAAAAA AA AAAA AAAAAA AA tAA tCLZ Data In AAAAAA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA I/O (Inputs) V IL OE V V IL AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AAAAAA AA tDH Data In tODD AAAAA AAAA AAAAAA tCPA AAAAAA AAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAAAA AA AAAA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA tOEH tCLZ tCPA tDZC AAAAAA AAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA tDZC tOEA tOEA tAWD tAA V V IL WE IH AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AA AAAA AAAAAA AA AAAA AA AAAA AAAAAA AA Hyper Page Mode (EDO) Read-Modify-Write Cycle Semiconductor Group Data In tODD tWP tOEA tWP tAWD tWP tCWL tRWD tCWD Row IH Address V V IL AAAA A AAAA AAAAA A AAAA A AAAA AAAAA A tASR V IL UCAS LCAS IH V tCWL tCPWD tCWD tASC Column tCAH tRAH tRAD tRCD AAAA A AAAA A AAAA A AAAA AAAAA A AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AAAAA AAAAA AAAA AAAAAA tRCS tASC Column tCAH tCP AAAAA AAAAA AAAA A AAAA AAAAA A AAAA AAAAA A AAAA AAAAA A AAAA A AAAA AAAAA A AAAA AAAAA A AAAA A AAAA A AAAA A AAAA A AAAA AAAAA A tCAS tCSH V IL IH RAS tAWD tCPWD tCWD Column tASC AAAA A AAAA AAAAA A AAAA AAAAA A AAAA AAAAA A AAAA A AAAA AAAAA A AAAA AAAAA A AAAA AAAAA A AAAA AAAAA A AAAA AAAAA A AAAA AAAAA A tCAS tPRWC tRASP V tRWL tCWL Row tASR tRAL tCAH tCAS tRSH tCRP tRP AAAAA AAAAA AAAAA AAAA AAAAA A AAAAA AAAA AAAAA A AAAAA AAAA AAAAA A AAAAA AAAAA AAAA AAAAA A AAAAA AAAAA AAAA AAAAA A AAAAA AAAA AAAAA A AAAAA AAAAA AAAAA A AAAA AAAAA AAAAA AAAA AAAAA A AAAAA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA AAAAAA AAAA AAAAAA AA AAAAAA tOEH HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM WL17 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRAS tRP V IH RAS VIL tCRP tRPC UCAS LCAS V AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA IH VIL tRAH tASR tASR V Address IH AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA VIL AAAAAAAA AAAAAAAA AAAA Row AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA V OH I/O (Outputs) V HI-Z OL AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA “H” or “L” WL9 RAS Only Refresh Cycle Semiconductor Group 24 Row HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRP tRAS tRP V RAS IH VIL tRPC tCSR tCRP tCP UCAS LCAS tRPC tCHR V AAAA AAAAAA AAAAA AAAAA AAAA AAAAAA AAAAA IH VIL tWRP tWRH WE V AAAAAAAAAAAAAAAA VIL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA IH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tOEZ V AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA IH OE VIL tCDD V AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA IH I/O (Inputs) V IL tODD V OH I/O (Outputs)VOL HI-Z tOFF AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL10 CAS-before-RAS Refresh Cycle Semiconductor Group 25 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRC RAS tRP tRAS V tRP tRAS IH VIL tRSH tRCD tCRP tCHR V UCAS LCAS IH tRAD VIL tWRP tASC tASR Address V AAAAAAA IHAAAA AAAAAAA AAA AAAAAAA AAA VIL AAAA AAAA AAAAAAA AAA tRAH AAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA Row AAAA AAAAA AAAAAAAA AAAA AAAA AAAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA Row tRRH tRCS WE tASR tWRH tCAH V AAAAAAAAAAAAAAAA IHAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA VIL AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAA AAAA AAAAAA AA AAAA AAAAAA AA AAAA AAAAAA AA tAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tOEA OE V AAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A VIL AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tDZC tCDD tDZO V I/O (Inputs) IH VIL AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAA A tODD tCAC tOFF tCLZ tOEZ tRAC V AAAA AA AAAA AAAA AA AAAA AAAA AAAAAA OH I/O (Outputs) V OL AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAA AAAA AAAAAAA AAA Valid Data Out “H” or “L” HI-Z WL11 Hidden Refresh Read Cycle Semiconductor Group AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAA 26 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRC tRC tRP tRAS V RAS IH tRAS tRP VIL tRCD tRSH tCHR tCRP V UCAS LCAS IH VIL tRAD tRAH tASC tCAH tASR Address V AAAAAAA IHAAAAAAA AAAAAAA AAAA AAAA AAAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAAAAA Row AAAA AAAAA A Column AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA VIL AAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AA tWCS tWRP tWRH tWCH tWP V WE AAAAAAAAAAAAAAAAAAA IH AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA VIL AAAA AAAAAAAAAAAAAAAAAAA AAA tDS I/O (Input) tASR V AAAAAAAAAAAAAAA IHAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA V AAAA IL AAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA tDH Valid Data AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA V OH I/O (Output) V OL AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAA HI-Z “H” or “L” WL12 Hidden Refresh Early Write Cycle Semiconductor Group Row 27 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM tRP tRASS tRPS V RAS IH VIL tRPC tCP V UCAS LCAS tCRP tCHS tCSR AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAA AAAAAAAA AAAAAA AAAAAAAAA IH VIL tWRP tWRH V WE AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAAAAAAAAAA IH AAAA AAAAAAAAAAAAAAAAAAA VIL V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA IH OE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A VIL tCDD V AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tODD IH I/O (Inputs) V IL tOEZ V OH I/O (Outputs) VOL HI-Z tOFF AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA “H” or “L” WL13 Self Refresh (Sleep Mode) Semiconductor Group 28 HYB3164(5/6)165AT(L)-40/-50/-60 4M x 16 EDO-DRAM Package Outlines Plastic Package P-TSOPII-50 (400 mil) (Thin Small Outline, SMD) Semiconductor Group 29