STMICROELECTRONICS STM8S105XX

STM8S103xx
STM8S105xx
Access line, STM8S 8-bit MCU, up to 32 Kbytes Flash,
10-bit ADC, timers, USART, SPI, I²C
Preliminary Data
Features
Core
■
Max fCPU: up to 16 MHz
Advanced STM8 core with Harvard
architecture and 3-stage pipeline
■ Extended instruction set
■
LQFP48 7x7
LQFP44 10x10
Memories
■
Program memory: Up to 32 Kbytes Flash; data
retention 20 years at 85°C after 1 kcycles
■ RAM: Up to 2 Kbytes
Clock, reset and supply management
■
3.0 to 5.5 V operating voltage
■
Flexible clock control, 4 master clock sources:
– Low power crystal resonator oscillator
– External clock input
– Internal 16 MHz RC
– Internal low power 128 kHz RC
■ Clock security system with clock monitor
■ Power management:
– Low power modes (Wait, Active-halt, Halt)
– Switch-off peripheral clocks individually
■ Permanently active, low consumption poweron and power-down reset
Interrupt management
LQFP32 7x7
Timers
■
■
■
■
■
■
USART or LINUART with clock output for
synchronous operation, smartcard mode, IrDA
mode, LIN master mode
■ SPI synchronous serial interface up to 8 Mbit/s
2
■ I C interface up to 400 Kbit/s
Analog to digital converter (ADC)
■
10-bit, ±1 LSB ADC with up to 10 multiplexed
channels, scan mode and analog watchdog
I/Os
■
Up to 38 I/Os on a 48-pin package including 9
high sink outputs
■ Highly robust I/O design, immune against
current injection
Table 1.
Device summary
Reference
Root part number
STM8S103xx
STM8S103K3
STM8S105xx
STM8S105C6, STM8S105C4,
STM8S105K6, STM8S105K4,
STM8S105S6, STM8S105S4,
2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
2 watchdog timers: Window watchdog and
independent watchdog
June 2008
VFQFN32 5x5
Communications interfaces
■
Nested interrupt controller with 32 interrupts
■ Up to 37 external interrupts on 6 vectors
TSSOP20
Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/56
www.st.com
1
Contents
STM8S103xx, STM8S105xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
4.1
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 11
4.3
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8
Auto wake-up counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.9
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.10
TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.11
TIM2- 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.12
TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.13
Analog/digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.14
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.14.1
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.2
LINUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.3
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.4
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.1
6
2/56
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM8S103xx, STM8S105xx
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1
8
Contents
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3.1
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3.2
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1.1
LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1.2
QFN package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.1.3
TSSOP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1
Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.2
Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3
11
10.2.1
STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2.2
C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3/56
List of tables
STM8S103xx, STM8S105xx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
4/56
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8S103/105 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STM8 TIM timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin description for STM8S105 MCUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin description for STM8S103 MCUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM8S103x alternate function remapping bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
32-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . . 50
TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data . . . . . . . . . . . . . . . . . . . . 51
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
STM8S103xx, STM8S105xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
STM8S105 access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM8S103 access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash memory organization (STM8S105) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory organisation (STM8S103) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM8S105 LQFP/VQFN 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM8S103 LQFP/VQFN 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Typical pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 40
Typical pull-up current Ipu vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typ. VOL @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typ. VDD - VOH @ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Typ. VDD - VOH @ VDD = 5.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . 45
Typical NRST pull-up current Ipu vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 45
Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
32-lead very thin fine pitch quad flat no-lead package (5 x 5) . . . . . . . . . . . . . . . . . . . . . . 50
TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM8S103/105 access line ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . 52
5/56
Introduction
1
STM8S103xx, STM8S105xx
Introduction
This datasheet contains the description of the STM8S103/105 access line features, pinout,
electrical characteristics, mechanical data and ordering information.
6/56
●
For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016)
●
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051)
●
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470)
●
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044)
STM8S103xx, STM8S105xx
2
Description
Description
The STM8S103/105 access line 8-bit microcontrollers offer from 8 Kbytes up to 32 Kbytes of
program memory.
All devices of the STM8S103/105 access line provide the following benefits:
●
Reduced system cost
–
●
Performance and robustness
–
●
16 MHz CPU clock frequency
–
Robust I/O, independent watchdogs with separate clock source
–
Clock security system
Short development cycles
●
–
Applications scalability across a common family product architecture with
compatible pinout, memory map and and modular peripherals.
–
Full documentation and a wide choice of development tools
Product longevity
–
Advanced core and peripherals made in a state-of-the art technology
–
A family of products for applications with 3.0 V to 5.5 V operating supply
12 10
12 10
11 9
11 9
11 7
11 7
STM8S103K3 32 28(2) 28
7
10
7
32K
16K
32K
16K
32K
16K
8
RAM (bytes)
9
9
8
8
8
8
48
48
44
44
32
32
Flash Program memory
(bytes)
Timer PWM channels
37
37
31
31
23
23
STM8S105C6
STM8S105C4
STM8S105S6
STM8S105S4
STM8S105K6
STM8S105K4
A/D Converter channels
Timer CAPCOM channels
38(1)
38(1)
34(1)
34(1)
25(1)
25(1)
Device
Pin count
Ext. Interrupt pins
STM8S103/105 access line features
No. of maximum GPIO
(I/O)
Table 2.
High system integration level with internal clock oscillators, watchdog and brownout reset
Peripheral set
2K LINUART + extended
2K features (synchronous
2K
comm. smartcard
2K
mode, IrdA mode),
2K
PWM timer (TIM3)
2K
Multipurpose timer (TIM1),
PWM timer (TIM2),
8-bit timer (TIM4),
SPI,
I2C
USART with full
Window WDG,
features (synchronous Independent WDG,
1K
comm. smartcard
ADC + extended features
mode, IrdA mode and
single wire mode)
1. 9 high sink outputs
2. 8 high sink outputs
7/56
Block diagram
3
STM8S103xx, STM8S105xx
Block diagram
Figure 1.
STM8S105 access line block diagram
Reset block
XTAL 1-16 MHz
Clock controller
Reset
Reset
RC int. 16 MHz
Detector
POR
BOR
RC int. 128 kHz
Clock to peripherals and core
Window WDG
STM8 CORE
Independent WDG
Debug/SWIM
Master/slave
autosynchro
LIN master
SPI emul.
LINUART
+ extended features
400 Kbit/s
I2C
10 Mbit/s
SPI
Up to 32 Kbytes
program
Flash
Address and data bus
Single wire
debug interf.
Up to 2 Kbytes
RAM
Boot ROM
16-bit advanced control
timer (TIM1)
16-bit general purpose
timers (TIM2, TIM3)
Up to 10 channels
1/2/4 kHz
beep
8/56
10-bit ADC
+ extended features
Beeper
8-bit basic timer
(TIM4)
AWU timer
Up to
9 CAPCOM
channels
STM8S103xx, STM8S105xx
Figure 2.
Block diagram
STM8S103 access line block diagram
Reset block
XTAL 1-16 MHz
Clock controller
Reset
Reset
RC int. 16 MHz
Detector
POR
BOR
RC int. 128 kHz
Clock to peripherals and core
Window WDG
STM8 CORE
Independent WDG
400 Kbit/s
I2C
8 Mbit/s
SPI
LIN master
SPI emul.
Up to 8 Kbytes
program
Flash
Debug/SWIM
USART
Address and data bus
Single wire
debug interf.
1 Kbytes
RAM
Boot ROM
16-bit advanced control
timer (TIM1)
16-bit general purpose
timer (TIM2)
Up to 7 channels
1/2/4 kHz
beep
10-bit ADC
+ extended features
Beeper
Up to
7 CAPCOM
channels
8-bit basic timer
(TIM4)
AWU timer
9/56
Product overview
4
STM8S103xx, STM8S105xx
Product overview
The following section intends to give an overview of the basic features of the
STM8S103/105 access line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
●
Harvard architecture
●
3-stage pipeline
●
32-bit wide program memory bus - single cycle fetching for most instructions
●
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
●
8-bit accumulator
●
24-bit program counter - 16-Mbyte linear memory space
●
16-bit stack pointer - access to a 64 K-level stack
●
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
●
20 addressing modes
●
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
●
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
10/56
●
80 instructions with 2-byte average instruction size
●
Standard data movement and logic/arithmetic functions
●
8-bit by 8-bit multiplication
●
16-bit by 8-bit and 16-bit by 16-bit division
●
Bit manipulation
●
Data transfer between stack and accumulator (push/pop) with direct stack access
●
Data transfer using the X and Y registers or direct memory-to-memory transfers
STM8S103xx, STM8S105xx
4.2
Product overview
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module and permit non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.
4.3
4.4
●
R/W to RAM and peripheral registers in real-time
●
R/W access to all resources by stalling the CPU
●
Breakpoints on all program-memory instructions (software breakpoints)
●
2 advanced breakpoints, 23 predefined configurations
Interrupt controller
●
Nested interrupts with 3 software priority levels
●
32 interrupt vectors with hardware priority
●
Up to 37 external interrupts on 6 vectors including TLI
●
Trap and reset interrupts
Flash program memory
●
Up to 32 Kbytes of program single voltage Flash memory
●
User option byte area
11/56
Product overview
STM8S103xx, STM8S105xx
Write protection (WP)
Write protection of Flash is provided to avoid unintentional overwriting of memory that could
result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (Memory Access
Security System). MASS is always enabled and protects the main Flash program memory
and option bytes.
To perform In-Application Programming (IAP), this write protection can be removed by
writing a MASS key sequence in a control register. This allows the application to modify the
contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to Figure 3.
The size of the UBC is programmable through the UBC option byte (Table 8.), in increments
of 1 page, by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
●
Main program memory: Up to 32 Kbytes minus UBC
●
User-specific boot code (UBC): Configurable up to 32 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 3.
Flash memory organization (STM8S105)
UBC area
Remains write protected during IAP
Up to
32 Kbytes
Flash
program
memory
Program memory area
Write access possible for IAP
12/56
Programmable area from 0.5 Kbytes
(2 first pages) up to 32 Kbytes
(1 page steps)
STM8S103xx, STM8S105xx
Figure 4.
Product overview
Flash memory organisation (STM8S103)
UBC area
Remains write protected during IAP
Programmable area from 128 bytes
(2 first pages) up to 8 Kbytes
(1 page steps)
Up to
8 Kbytes
Flash
program
memory
Program memory area
Write access possible for IAP
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory in debug
mode. Once the read-out protection is activated, any attempt to toggle its status triggers a
global erase of the program and data memory. Even if no protection can be considered as
totally unbreakable, the feature provides a very high level of protection for a general purpose
microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
●
Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
●
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
●
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
●
Master clock sources: 4 different clock sources can be used to drive the master clock:
–
1-16 MHz High Speed External crystal (HSE)
–
Up to 16 MHz High Speed user-external clock (HSE user-ext)
–
16 MHz High Speed Internal RC oscillator (HSI)
–
128 kHz Low Speed Internal RC (LSI)
●
Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
●
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
13/56
Product overview
STM8S103xx, STM8S105xx
and an interrupt can optionally be generated.
●
4.6
Configurable main clock output (CCO): This outputs an external clock for use by the
application. Available frequencies are 8 MHz, 4 MHz or 1 MHz.
Power management
For efficent power management, the application can be put in one four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
4.7
●
Wait mode: in this mode, the CPU is stopped, but peripherals are kept running. The
wake-up is performed by an internal or external interrupt or reset.
●
Fast active halt mode: in this mode, the CPU and peripheral clocks are stopped. An
internal wake-up is generated at programmable intervals by the auto wake up unit
(AWU). The main voltage regulator is kept powered on, so current consumption is more
than in slow active halt mode, but the wake-up time is faster. Wake-up is triggered by
the internal AWU interrupt, external interrupt or reset.
●
Slow active halt mode: this mode is the same as fast active halt except that the main
voltage regulator is powered off, so the wake up time is slower.
●
Halt mode: in this mode the microcontroller uses the least power, CPU and peripheral
clocks are stopped, the main voltage regulator is powered off. Wake-up is triggered by
external interrupt or reset.
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
The WDG timer activity is controlled by option bytes. Once activated the watchdog can not
be disabled by the user program without reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1.
Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2.
Refresh out of window: The downcounter is refreshed before its value is lower then the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
14/56
STM8S103xx, STM8S105xx
Product overview
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8
4.9
Auto wake-up counter
●
Used for auto wake-up from active halt mode
●
Clock source: internal 128 kHz internal low frequency RC oscillator or external clock
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
4.11
4.12
●
16-bit up, down and up/down autoreload counter with 16-bit prescaler
●
4 independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse
mode output
●
Synchronization module to control the timer with external signal
●
Break input to force the timer outputs into a defined state
●
3 complementary outputs with adjustable dead time
●
Encoder mode
●
Interrupt sources: x input capture/output compare, 1 x overflow/update, 1 x break
TIM2- 16-bit general purpose timer
●
16-bit autoreload (AR) up-counter
●
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
●
Timers with 3 or 2 individually configurable capture/compare channels
●
PWM mode
●
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
TIM4 - 8-bit basic timer
●
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
●
Clock source: CPU clock
●
Interrupt source: 1 x overflow/update
15/56
Product overview
Table 3.
STM8S103xx, STM8S105xx
STM8 TIM timer feature comparison
Timer
Counter
size
(bits)
Prescaler
TIM1
16
Any integer from 1 to 65536
Up/down
4
3
Yes
TIM2
16
Any power of 2 from 1 to 32768
Up
3
0
No
TIM3
16
Any power of 2 from 1 to 32768
Up
2
0
No
TIM4
8
Any power of 2 from 1 to 128
Up
0
0
No
Ext.
Counting CAPCOM Complem.
trigger
mode
channels outputs
Timer
synchronization/
chaining
Yes
16/56
STM8S103xx, STM8S105xx
4.13
Product overview
Analog/digital converter (ADC)
●
STM8S103/105 access line products contain a 10-bit successive approximation A/D
converter with up to 10 multiplexed input channels and the following general features:
–
Input voltage range: 0 to VDDA
–
Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices
–
Conversion time: 14 clock cycles
–
Single and continuous conversion modes
–
External trigger input
–
Trigger from TIM1 TRGO (STM8S105) or TIM2 TRGO (STM8S103)
–
End of conversion (EOC) interrupt
ADC extended features
●
4.14
STM8S103/105 access line products contain a 10-bit successive approximation A/D
converter with the following features:
–
Up to 10 (STM8S105x) or 7 (STM8S103x) multiplexed input channels
–
Single, continuous and buffered continuous conversion on a selected channel
–
Scan mode for single and continuous conversion of a sequence of channels
–
Analog watchdog capability with programmable upper and lower thresholds
–
Internal reference voltage on channel AIN7 (STM8S103 only)
–
Analog watchdog interrupt
Communication interfaces
The following communication interfaces are implemented:
●
●
USART:
–
STM8S105: no USART
–
STM8S103: full feature UART, single wire mode, LIN2.1 master capability
LINUART:
–
STM8S105: LIN2.1 master/slave capability, full feature UART, synchronous mode,
SPI master mode, Smartcard mode, IrDA mode
–
STM8S103: No LINUART
●
SPI - full and half-duplex, 8 Mbit/s
●
I²C - up to 400 Kbit/s
17/56
Product overview
4.14.1
STM8S103xx, STM8S105xx
USART
Main features
●
1 Mbit/s full duplex SCI
●
LIN master capable
●
SPI emulation
●
High precision baud rate generator
●
Smartcard emulation
●
IrDA SIR encoder decoder
●
Single wire half duplex mode
Asynchronous communication (UART mode)
●
Full duplex communication - NRZ standard format (mark/space)
●
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
●
Separate enable bits for transmitter and receiver
●
2 receiver wakeup modes:
–
Address bit (MSB)
–
Idle line (interrupt)
●
Transmission error detection with interrupt generation
●
Parity control
LIN master capability
●
Emission: Generates 13-bit synch break frame
●
Reception: Detects 11-bit break frame
Synchronous communication
4.14.2
●
Full duplex synchronous transfers
●
SPI master operation
●
8-bit data communication
●
Max. speed: 1 Mbit/s at 16 MHz (fCPU/16)
LINUART
Main features
●
LIN master/slave rev. 2.1 compliant
●
Auto-synchronization in LIN slave mode
●
High precision baud rate generator
●
1 Mbit full duplex SCI
LIN master
18/56
●
Emission: Generates 13-bit synch break frame
●
Reception: Detects 11-bit break frame
STM8S103xx, STM8S105xx
Product overview
LIN slave
●
Autonomous header handling - one single interrupt per valid message header
●
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
●
Synch delimiter checking
●
11-bit LIN synch break detection - break detection always active
●
Parity check on the LIN identifier field
●
LIN error management
●
Hot plugging support
Asynchronous communication (UART mode)
●
Full duplex, asynchronous communications - NRZ standard format (mark/space)
●
Independently programmable transmit and receive baud rates up to 500 Kbit/s
●
Programmable data word length (8 or 9 bits)
●
Low-power standby mode - 2 receiver wake-up modes:
–
Address bit (MSB)
–
Idle line
●
Muting function for multiprocessor configurations
●
Overrun, noise and frame error detection
●
6 interrupt sources
●
Tx, Rx parity control
Note:
In STM8S105, the LINUART also supports IrDA mode, Smartcard mode and synchronous
communication (SPI master mode).
4.14.3
SPI
●
Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
●
Full duplex synchronous transfers
●
Simplex synchronous transfers on 2 lines with a possible bidirectional data line
●
Master or slave operation - selectable by hardware or software
●
CRC calculation
●
1 byte Tx and Rx buffer
●
Slave/master selection input pin
19/56
Product overview
4.14.4
I2C
●
●
20/56
STM8S103xx, STM8S105xx
I2C master features:
–
Clock generation
–
Start and stop generation
I2C
slave features:
–
Programmable I2C address detection
–
Stop bit detection
●
Generation and detection of 7-bit/10-bit addressing and general call
●
Supports different communication speeds:
–
Standard speed (up to 100 kHz),
–
Fast speed (up to 400 kHz)
STM8S103xx, STM8S105xx
Pinouts and pin description
5
Pinouts and pin description
5.1
Package pinouts
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CC1/BEEP
PD3 (HS)/TIM2_CC2/ADC_ETR
PD2 (HS)/TIM3_CC1
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CC2
PE0/CLK_CCO
PE1/I2C_SCL
PE2/I2C_SDA
PE3/TIM1_BKIN
LQFP 48-pin pinout
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
TIM2_CC3/PA3
PA4
PA5
PA6
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
3
34
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 2223 24
VDDA
VSSA
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_NCC3/AIN2/PB2
TIM1_NCC2/AIN1/PB1
TIM1_NCC1/AIN0/PB0
AIN8/PE7
AIN9/PE6
Figure 5.
PG1
PG0
PC7/SPI_MISO
PC6/SPI_MOSI
VDDIO_2
VSSIO_2
PC5/SPI_SCK
PC4 (HS)/TIM1_CC4
PC3 (HS)/TIM1_CC3
PC2 (HS)/TIM1_CC2
PC1 (HS)/TIM1_CC1/LINUART_CK
PE5/SPI_NSS
(HS) high sink capability
21/56
Pinouts and pin description
LQFP 44-pin pinout
PD7/TLI/TIM1_CC4
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CC1/BEEP
PD3 (HS)/TIM2_CC2/ADC_ETR
PD2 (HS)/TIM3_CC1/TIM2_CC3
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CC2/TIM1_BRK
PE0/CLK_CCO
PE1/I2C_SCL
PE2/I2C_SDA
Figure 6.
STM8S103xx, STM8S105xx
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
PG1
PG0
PC7/SPI_MISO
PC6/SPI_MOSI
VDDIO_2
VSSIO_2
PC5/SPI_SCK
PC3 (HS)/TIM1_CC3
PC2 (HS)/TIM1_CC2
PC1 (HS)/TIM1_CC1/LINUART_CK
PE5/SPI_NSS
VDDA
VSSA
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_NCC3/AIN2/PB2
TIM1_NCC2/AIN1/PB1
TIM1_NCC1/AIN0/PB0
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
PA4
PA5
PA6
(HS) high sink capability
22/56
STM8S103xx, STM8S105xx
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CC1/BEEP
PD3 (HS)/TIM2_CC2/ADC_ETR
PD2 (HS)/TIM3_CC1/TIM2_CC3
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CC2/CLK_CCO/TIM1_BRK
STM8S105 LQFP/VQFN 32-pin pinout
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
VDDIO
AIN12/PF4
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 1516
PC7/SPI_MISO
PC6/SPI_MOSI
PC5/SPI_SCK
PC4 (HS)/TIM1_CC4
PC3 (HS)/TIM1_CC3
PC2 (HS)/TIM1_CC2
PC1 (HS)/TIM1_CC1/LINUART_CK
PE5/SPI_NSS
VDDA
VSSA
I2C_SDA/AIN5/PB5
I2C_SCL/AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_NCC3/AIN2/PB2
TIM1_NCC2/AIN1/PB1
TIM1_NCC1/AIN0/PB0
Figure 7.
Pinouts and pin description
(HS) high sink capability
23/56
Pinouts and pin description
STM8S103 LQFP/VQFN 32-pin pinout
PD7(HS)/TLI/TIM1_CC4
PD6/AIN5/USART_RX
PD5/AIN4/USART_TX
PD4 (HS)/TIM2_CC1/BEEP /USART_CK
PD3 (HS)/AIN4/TIM2_CC2/ADC_ETR
PD2 (HS)/AIN3/TIM2_CC3
PD1 (HS)/SWIM
PD0 (HS)/TIM1_BKIN/CLK_CCO
Figure 8.
STM8S103xx, STM8S105xx
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 1516
PC7(HS)/SPI_MISO
PC6(HS)/SPI_MOSI
PC5(HS)/SPI_SCK/TIM2_CC1
PC4(HS)/AIN2/TIM1_CC4
PC3 (HS)/TIM1_CC3/TLI/USART_CK
PC2 (HS)/TIM1_CC2
PC1 (HS)/TIM1_CC1
PE5(HS)/SPI_NSS
PB7
PB6
I2C_SDA/PB5
I2C_SCL/PB4
TIM1_ETR/PB3
TIM1_NCC3/(HS)PB2
TIM1_NCC2/AIN1/(HS)PB1
TIM1_NCC1/AIN0/(HS)PB0
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
SPI_NSS/TIM2_CC3/(HS)PA3
PF4
Figure 9.
(HS) high sink capability
TSSOP20 pinout
PD4 (HS)/TIM2_CC1/BEEP /USART_CK
PD3 (HS)/AIN4/TIM2_CC2/ADC_ETR
PD2(HS)/AIN3/TIM2_CC3
USART_TX/AIN5/PD5
1
20
USART_RX/AIN6/PD6
2
19
NRST
3
18
OSCIN/PA1
4
17
PD1 (HS)/SWIM
OSCOUT/PA2
5
16
PC7(HS)/SPI_MISO
VSS
6
15
PC6(HS)/SPI_MOSI
VCAP
VDD
7
14
PC5 (HS)/TIM2_CC1/SPI_SCK
8
13
PC4(HS)/AIN2/TIM1_CC4/CLK_CCO
SPI_NSS/TIM2_CC3/(HS)PA3
9
12
PC3(HS)/TLI/TIM1_CC3/USART_CK
10
11
PB4/I2C_SCL
I2C_SDA/PB5
(HS) high sink capability
24/56
STM8S103xx, STM8S105xx
5.2
Pinouts and pin description
Pin description
Table 4.
Legend/abbreviations
Type
I= input, O = output, S = power supply
Level
Input
CM = CMOS
Output
HS = High sink
Output speed
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control Input
configuration
Output
float = floating, wpu = weak pull-up
T = true open drain, OD = open drain, PP = push pull
Reset state is shown in bold.
Pin number
X
2
2
2 PA1/OSCIN
I/O X
X
3
3
3 PA2/OSCOUT
I/O X
X
4
4
- VSSIO_1
S
I/O ground
5
5
4 VSS
S
Digital ground
6
6
5 VCAP
S
1.8 V regulator capacitor
7
7
6 VDD
S
Digital power supply
8
8
7 VDDIO_1
S
I/O power supply
-
-
8 PF4/AIN12
I/O X
X
9
-
- PA3/TIM2_CC3
I/O X
X
10
9
- PA4
I/O X
11 10
- PA5
12 11
- PA6
13 12
9 VDDA
S
Analog power supply
14 13 10 VSSA
S
Analog ground
15 14
- PB7/AIN7
PP
I/O
OD
1 NRST
Speed
1
wpu
1
Pin name
floating
LQFP32
Alternate
Default alternate function after
function
remap
[option bit]
LQFP44
High sink
Output
LQFP48
Type
Input
Main function
(after reset)
Pin description for STM8S105 MCUs
Ext. interrupt
Table 5.
Reset
X
O1 X
X Port A1
Resonator/
crystal in
O1 X
X Port A2
Resonator/ crystal
out
O1 X
X
X
O1 X
X Port A3 Timer 2 - channel3
X
X
O3 X
X Port A4
I/O X
X
X
O3 X
X Port A5
I/O X
X
X
O3 X
X Port A6
I/O X
X
X
O1 X
Port F4 Analog input 12
TIM3_CC1
[AFR1]
X Port B7 Analog input 7
25/56
Pinouts and pin description
Pin description for STM8S105 MCUs (continued)
Pin number
Alternate
Default alternate function after
function
remap
[option bit]
X
X
O1 X
X Port B5 Analog input 5
I2C_SDA
[AFR6]
18 17 12 PB4/AIN4
I/O X
X
X
O1 X
X Port B4 Analog input 4
I2C_SCL
[AFR6]
19 18 13 PB3/AIN3
I/O X
X
X
O1 X
X Port B3 Analog input 3
TIM1_ETR
[AFR5]
20 19 14 PB2/AIN2
I/O X
X
X
O1 X
X Port B2 Analog input
TIM1_NCC3
[AFR5]
21 20 15 PB1/AIN1
I/O X
X
X
O1 X
X Port B1 Analog input 1
TIM1_NCC2
[AFR5]
22 21 16 PB0/AIN0
I/O X
X
X
O1 X
X Port B0 Analog input 0
TIM1_NCC1
[AFR5]
23
- PE7/AIN8
I/O X
X
X
O1 X
X
Port E7 Analog input 8
PE6/AIN9
I/O X
X
X
O1 X
X
Port E7 Analog input 9
I/O X
X
X
O1 X
X
Port E5
PC1/TIM1_CC1/
LINUART_CK
I/O X
X
X HS O3 X
Timer 1 - channel 1
X Port C1 / LINUART
synchronous clock
27 25 19 PC2/TIM1_CC2
I/O X
X
X HS O3 X
X Port C2 Timer 1- channel 2
28 26 20 PC3/TIM1_CC3
I/O X
X
X HS O3 X
X Port C3 Timer 1 - channel 3
29
I/O X
X
X HS O3 X
X Port C4 Timer 1 - channel 4
I/O X
X
X
X Port C5 SPI clock
-
24 22
25 23 17 PE5/SPI_NSS
26 24 18
-
21 PC4/TIM1_CC4
30 27 22 PC5/SPI_SCK
O3 X
PP
I/O X
OD
17 16 11 PB5/AIN5
Speed
X Port B6 Analog input 6
High sink
O1 X
floating
X
Pin name
Type
X
16 15
LQFP32
I/O X
LQFP44
- PB6/AIN6
LQFP48
Ext. interrupt
Output
wpu
Input
Main function
(after reset)
Table 5.
STM8S103xx, STM8S105xx
SPI master/slave
select
31 28
- VSSIO_2
S
I/O ground
32 29
- VDDIO_2
S
I/O power supply
33 30 23 PC6/SPI_MOSI
I/O X
X
X
O3 X
X Port C6
SPI master out/
slave in
34 31 24 PC7/SPI_MISO
I/O X
X
X
O3 X
X Port C7
SPI master in/
slave out
35 32
- PG0
I/O X
X
O1 X
X Port G0
36 33
- PG1
I/O X
X
O1 X
X Port G1
37
- PE3/TIM1_BKIN
I/O X
X
X
O1 X
X
- PE2/I2C_SDA
I/O X
X
X
O1 T(1) X
-
38 34
26/56
Port E3
Timer 1 - break
input
Port E2 I2C data
STM8S103xx, STM8S105xx
Pin description for STM8S105 MCUs (continued)
Pin number
Alternate
Default alternate function after
function
remap
[option bit]
- PE0/CLK_CCO
I/O X
X
X
O3 X
Port E0
PP
40 36
OD
Port E1 I2C clock
Speed
O1 T(1) X
High sink
X
floating
X
Pin name
Type
I/O X
LQFP32
- PE1/I2C_SCL
LQFP44
39 35
LQFP48
Ext. interrupt
Output
wpu
Input
Main function
(after reset)
Table 5.
Pinouts and pin description
X
Configurable clock
output
41 37 25 PD0/TIM3_CC2
I/O X
X
X HS O3 X
TIM1_BKIN
[AFR3]/
X Port D0 Timer 3 - channel 2
CLK_CCO
[AFR2]
42 38 26 PD1/SWIM
I/O X
X
X HS O4 X
X Port D1
43 39 27 PD2/TIM3_CC1
I/O X
X
X HS O3 X
X Port D2 Timer 3 - channel 1
TIM2_CC3
[AFR1]
44 40 28 PD3/TIM2_CC2
I/O X
X
X HS O3 X
X Port D3 Timer 2 - channel 2
ADC_ETR
[AFR0]
PD4/TIM2_CC1/BEE
I/O X
P
X
X HS O3 X
X Port D4 Timer 2 - channel 1
BEEP output
[AFR7]
45 41 29
SWIM data
interface
46 42 30 PD5/ LINUART_TX
I/O X
X
X
O1 X
X Port D5
LINUART data
transmit
47 43 31 PD6/ LINUART_RX
I/O X
X
X
O1 X
X Port D6
LINUART data
receive
48 44 32 PD7/TLI
I/O X
X
X
O1 X
X Port D7 Top level interrupt
TIM1_CC4
[AFR4]
1. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented)
27/56
Pinouts and pin description
Pin description for STM8S103 MCUs
Pin
number
Alternate
function
Default alternate
after
function
remap
[option
bit]
PA1/OSCIN
I/O X
X
X
O1 X
X Port A1
Resonator/
crystal in
3
5
PA2/OSCOUT
I/O X
X
X
O1 X
X Port A2
Resonator/ crystal
out
4
6
VSS
S
Digital ground
5
7
VCAP
S
1.8 V regulator capacitor
6
8
VDD
S
Digital power supply
7
9
PA3/TIM2_CC3/SPI_NSS
I/O X
X
X HS O3 X
SPI
X Port A3 Timer 2 channel 3 master/sla
ve select
8
-
PF4
I/O X
X
X
O1 X
X
9
-
PB7
I/O X
X
X
O1 X
X Port B7
10
-
PB6
I/O X
X
X
O1 X
X Port B6
PP
4
OD
2
Speed
X
High sink
I/O
Ext. interrupt
NRST
wpu
3
floating
1
Pin name
Type
TSSOP20
Output
VQFN/LQFP32
Input
Main function
(after reset)
Table 6.
STM8S103xx, STM8S105xx
Reset
(1)
Port F4
X Port B5 I2C data
11
10 PB5/I2C_SDA
I/O X
X
X
O1 T
12
11 PB4/I2C_SCL
I/O X
X
X
O1 T(1) X Port B4 I2C clock
13
-
PB3/TIM1_ETR
I/O X
X
X HS O3 X
X Port B3
Timer 1 external
trigger
14
-
PB2/TIM1_NCC3
I/O X
X
X HS O3 X
X Port B2
Timer 1 - inverted
channel 3
15
-
PB1/AIN1/TIM1_NCC2
I/O X
X
X HS O3 X
Analog input 1/
X Port B1 Timer 1 - inverted
channel 2
16
-
PB0/AIN0/TIM1_NCC1
I/O X
X
X HS O3 X
Analog input 0/
X Port B0 Timer 1 - inverted
channel 1
17
-
PE5/SPI_NSS
I/O X
X
X HS O3 X
X
Port E5
SPI master/slave
select
18
-
PC1/TIM1_CC1
I/O X
X
X HS O3 X
X Port C1
Timer 1 - channel
1
19
-
PC2/TIM1_CC2
I/O X
X
X HS O3 X
X Port C2
Timer 1 - channel
2
20
12
PC3/TLI/TIM1_CC3/
USART_CK
I/O X
X
X HS O3 X
Top level interrupt
USART
X Port C3 Timer 1 - channel
clock
3
28/56
STM8S103xx, STM8S105xx
Pin description for STM8S103 MCUs (continued)
Pin
number
Alternate
function
Default alternate
after
function
remap
[option
bit]
X
X HS O3 X
X Port C5
Timer 2 - channel
SPI clock
1
23
15 PC6/SPI_MOSI
I/O X
X
X HS O3 X
X Port C6
SPI master out/
slave in
24
16 PC7/SPI_MISO
I/O X
X
X HS O3 X
X Port C7
SPI master in/
slave out
X
X HS O3 X
Timer 1 - break
X Port D0
input
25
-
PD0/TIM1_BKIN/CLK_CCO I/O X
PP
I/O X
OD
14 PC5/TIM2_CC1/SPI_SCK
Speed
22
High sink
X HS O3 X
Ext. interrupt
X
wpu
I/O X
ConAnalog input 2 /
figurable
X Port C4 Timer 1 - channel
clock
4
output
floating
21
PC4/AIN2/TIM1_CC4/
13
CLK_CCO
Pin name
Type
TSSOP20
Output
VQFN/LQFP32
Input
Main function
(after reset)
Table 6.
Pinouts and pin description
Configurable
clock
output
SWIM data
interface
26
17 PD1/SWIM
I/O X
X
X HS O4 X
X Port D1
27
18 PD2/AIN3/TIM2_CC3
I/O X
X
X HS O3 X
Analog input 3 /
X Port D2 Timer 2 - channel
3
28
19
PD3/AIN4/TIM2_CC2/ADC_
I/O X
ETR
X
X HS O3 X
Analog input 4 /
ADC
X Port D3 Timer 2 - channel external
2
trigger
29
PD4/TIM2_CC1/BEEP/
20
USART_CK
I/O X
X
X HS O3 X
USART
Timer 2 - channel clock/
X Port D4
BEEP
1
output
30
1
PD5/AIN5/USART_TX
I/O X
X
X
O1 X
X Port D5 Analog input 5
USART
data
transmit
31
2
PD6/AIN6/USART_RX
I/O X
X
X
O1 X
X Port D6 Analog input 6
USART
data
receive
32
-
PD7/TLI/TIM1_CC4
I/O X
X
X HS O3 X
Top level interrupt/
X Port D7 Timer 1 - channel
4
1. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented)
29/56
Pinouts and pin description
5.2.1
STM8S103xx, STM8S105xx
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of 8 AFR (alternate function remap)
option bits. Refer to Section 6: Option bytes on page 29. When the remapping option is
active, the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see GPIO
section of the family reference manual, RM0016).
30/56
STM8S103xx, STM8S105xx
6
Option bytes
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the address shown in
Table 7: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be toggled in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 7.
Addr.
Option bytes
Option
name
Option
byte
no.
Option bits
7
6
5
4
3
2
1
0
Factory
default
setting
4800h
Read-out
protection
(ROP)
OPT0
ROP[7:0]
00h
4801h
User boot
code(UBC)
OPT1
UBC[7:0]
00h
4802h
4803h
4804h
4805h
NOPT1
Alternate
function
remapping
(AFR)
Watchdog
option
4806h
4807h
Clock option
4808h
4809h
HSE clock
startup
480Ah
480Bh
Reserved
480Ch
480Dh
Flash wait
states
480Eh
487Eh
487Fh
Bootloader
NUBC[7:0]
FFh
OPT2
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
00h
NOPT2
NAFR7
NAFR6
NAFR5
NAFR4
NAFR3
NAFR2
NAFR1
NAFR0
FFh
OPT3
Reserved
LSI
_EN
IWDG
_HW
WWDG
_HW
WWDG
_HALT
00h
NOPT3
Reserved
NLSI
_EN
NIWDG_
HW
NWWDG
_HW
NWWG
_HALT
FFh
OPT4
Reserved
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
00h
NOPT4
Reserved
NEXT
CLK
NCKAWUS
EL
NPR
SC1
NPR
SC0
FFh
OPT5
HSECNT[7:0]
00h
NOPT5
NHSECNT[7:0]
FFh
OPT6
Reserved
00h
NOPT6
Reserved
FFh
OPT7
Reserved
Wait state
00h
NOPT7
Reserved
Nwait state
FFh
OPTBL
BL[7:0]
00h
NOPTBL
NBL[7:0]
FFh
31/56
Option bytes
STM8S103xx, STM8S105xx
Table 8.
Option byte description
Option byte no.
OPT0
ROP[7:0] Memory readout protection (ROP)
AAh: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on Flash
memory readout protection for details.
OPT1
UBC[7:0] User boot code area
For STM8S105 (page size 128 bytes):
00h: no UBC, no write-protection
01h: Page 0 and 1 defined as UBC, memory write-protected
02h to FFh: Pages 2 to 255 defined as UBC, memory write-protected
For STM8S103 (page size 64 bytes):
00h: no UBC, no write-protection
01h: Page 0 and 1 defined as UBC, memory write-protected
02h to 7Fh: Pages 2 to 127 defined as UBC, memory write-protected
Note: Refer to the family reference manual (RM0016) section on Flash
write protection for more details.
OPT2
Note : This remapping applies to STM8S105. For STM8S103 alternate
function remapping refer to Table 9 on page 34.
AFR7Alternate function remapping option 7
0: Port D4 alternate function = TIM2_CC1
1: Port D4 alternate function = BEEP
AFR6 Alternate function remapping option 6
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I2C_SDA, port B4 alternate function =
I2C_SCL
AFR5 Alternate function remapping option 5
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_NCC3, port B1 alternate function = TIM1_NCC2, port B0 alternate
function = TIM1_NCC1
AFR4 Alternate function remapping option 4
0: Port D7 alternate function = TLI
1: Port D7 alternate function = TIM1_CC4
AFR3 Alternate function remapping option 3
0: Port D0 alternate function = TIM3_CC2
1: Port D0 alternate function = TIM1_BKIN
AFR2 Alternate function remapping option 2
0: Port D0 alternate function = TIM3_CC2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
OPT2 (cont’d)
32/56
Description
AFR1 Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CC3, port D2 alternate function
TIM3_CC1
1: Port A3 alternate function = TIM3_CC1, port D2 alternate function
TIM2_CC3
AFR0 Alternate function remapping option 0
0: Port D3 alternate function = TIM2_CC2
1: Port D3 alternate function = ADC_ETR
STM8S103xx, STM8S105xx
Table 8.
Option bytes
Option byte description (continued)
Option byte no.
Description
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
OPT3
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
OPT4
CKAWUSEL: Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
00: Reserved
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
OPT5
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilisation time to 0, 16, 256, 4096 HSE cycles.
OPT6
Reserved
OPT7
Reserved
OPTBL
BL[7:0] Bootloader option byte
This option is checked by the boot ROM code after reset. Depending on
content of addresses 487Eh, 487Fh and 8000h (reset vector) the CPU
jumps to the bootloader or to the reset vector.
Refer to STM8S bootloader manual for more details.
33/56
Option bytes
STM8S103xx, STM8S105xx
Table 9.
STM8S103x alternate function remapping bits.
Option byte no.
OPT2
34/56
Description
AFR7Alternate function remapping option 7
0: TBD
1: TBD
AFR6 Alternate function remapping option 6
0: TBD
1: TBD
AFR5 Alternate function remapping option 5
0: TBD
1: Reserved
AFR4 Alternate function remapping option 4
0: TBD
1: TBD
AFR3 Alternate function remapping option 3
0: TBD
1: TBD
AFR2 Alternate function remapping option 2
0: TBD
1: TBD
AFR1 Alternate function remapping option 1
0: TBD
1: TBD
AFR0 Alternate function remapping option 0
0: TBD
1: TBD
STM8S103xx, STM8S105xx
Electrical characteristics
7
Electrical characteristics
7.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
7.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3 Σ).
7.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5.0 V. They are
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
7.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
7.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Figure 10. Pin loading conditions
STM8 PIN
50pF
35/56
Electrical characteristics
7.1.5
STM8S103xx, STM8S105xx
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 11. Pin input voltage
STM8 PIN
VIN
7.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 10.
Symbol
VDDx - VSS
VIN
Voltage characteristics
Ratings
Min
Max
-0.3
6.5
Input voltage on true open drain pins (PE1, PE2)(2)
VSS - 0.3
6.5
Input voltage on any other pin(2)
VSS - 0.3
VDD + 0.3
Supply voltage (including VDDA and VDDIO)(1)
|VDDx - VSS| Variations between different power pins
50
|VSSx - VSS| Variations between all the different ground pins
50
Unit
V
mV
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
36/56
STM8S103xx, STM8S105xx
Table 11.
Electrical characteristics
Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into VDD power lines (source)(1)
60
IVSS
Total current out of VSS ground lines (sink)(1)
60
Output current sunk by any I/O and control pin
20
IIO
IINJ(PIN)(2)(3)
ΣIINJ(PIN)(2)
Output current source by any I/Os and control pin
- 20
Injected current on NRST pin
±4
Injected current on OSCIN pin
±4
Injected current on any other pin(4)
±4
Total injected current (sum of all I/O and control pins)(4)
± 20
Unit
mA
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
3. Negative injection disturbs the analog performance of the device.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 12.
Thermal characteristics
Symbol
Ratings
Value
TSTG
Storage temperature range
-65 to +150
TJ
Maximum junction temperature
150
Unit
°C
37/56
Electrical characteristics
7.3
STM8S103xx, STM8S105xx
Operating conditions
Table 13.
General operating conditions(1)
Symbol
Parameter
Conditions
fCPU
Internal CPU clock frequency
VDD/VDD_IO Standard operating voltage
PD
Power dissipation at
TA= 85° C for suffix 6
or TA= 125° C for suffix 3
TJ
Max
Unit
0
16
MHz
3.0
5.5
V
LQFP48
TBD
LQFP44
TBD
LQFP32
TBD
VFQFN32
TBD
TSSOP20
TBD
Ambient temperature for 6
suffix version
Maximum power dissipation
Ambient temperature for 3
suffix version
85
°C
-40
105
°C
Maximum power dissipation
-40
125
°C
Low power dissipation (2)
-40
TBD
°C
6 suffix version
-40
105
°C
3 suffix version
-40
TBD
°C
dissipation(2)
Junction temperature range
1. TBD = to be determined.
2. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax
Figure 12. fCPUmax versus VDD
fCPU [MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
16
FUNCTIONALITY
GUARANTEED
@ TA -40 to 125 °C
12
8
4
0
3.0
4.0
5.0
SUPPLY VOLTAGE [V]
38/56
mW
-40
Low power
TA
Min
5.5
STM8S103xx, STM8S105xx
7.3.1
Electrical characteristics
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 14.
Symbol
I/O static characteristics(1)
Parameter
VIL
Input low level
voltage
VIH
Input high level
voltage
Vhys
Hysteresis(2)
Rpu
Pull-up resistor
tR, tF
Rise and fall time
(10% - 90%)
Conditions
VDD = 5.0 V
Min
Typ
Max
Unit
-0.3 V
TBD
V
0.7 x VDD
VDD + 0.3 V
V
700
60
kΩ
Fast I/Os
Load = 50 pF
20 (3)
ns
Standard and high sink I/Os
Load = 50 pF
125 (3)
ns
Input leakage
current,
analog and digital
VSS≤VIN≤VDD
±1 (3)
µA
Ilkg ana
Analog input
leakage current
VSS≤VIN≤VDD
±250 (3)
nA
Ilkg(inj)
Leakage current in
adjacent I/O(3)
Injection current ±4 mA
±1(3)
µA
Ilkg
VDD = 5 V, VIN=VSS
30
45
mV
1. TBD = to be determined.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
3. Data based on characterization results, not tested in production.
39/56
Electrical characteristics
STM8S103xx, STM8S105xx
Figure 13. Typical VIL and VIH vs VDD @ 4 temperatures
6
-40°C
25°C
5
85°C
VIL / V IH [V]
4
125°C
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 14. Typical pull-up resistance RPU vs VDD @ 4 temperatures
60
Pull-Up resistance [k ohm]
55
50
45
-40°C
40
25°C
85°C
35
125°C
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 15. Typical pull-up current Ipu vs VDD @ 4 temperatures
140
Pull-Up current [µA]
120
100
80
-40°C
60
25°C
40
85°C
125°C
20
0
0
1
2
3
VDD [V]
Note: The pull-up is a pure resistor (slope goes through 0).
40/56
4
5
6
STM8S103xx, STM8S105xx
Table 15.
Symbol
VOL
VOH
Electrical characteristics
Output driving current (standard ports)
Parameter
Conditions
Min
Max
Output low level with 4 pins sunk
IIO = 4 mA,VDD = 3.3 V
1000(1)
Output low level with 8 pins sunk
IIO= 10 mA,VDD = 5.0 V
2000
Output high level with 4 pins sourced
IIO = 4 mA, VDD = 3.3 V
2.1(1)
Output high level with 8 pins sourced
IIO = 10 mA, VDD = 5.0 V
2.8
Unit
mV
V
1. Data based on characterization results, not tested in production
Table 16.
Symbol
Output driving current (true open drain ports)
Parameter
Conditions
Min
Output low level with 2 pins sunk
Unit
(1)
IIO = 10 mA, VDD = 3.3 V
VOL
Max
1500
IIO = 10 mA, VDD = 5.0 V
1000
IIO = 20 mA, VDD = 5.0 V
TBD(1)
mV
1. Data based on characterization results, not tested in production
Table 17.
Symbol
VOL
VOH
Output driving current (high sink ports)
Parameter
Conditions
Min
Max
Output low level with 4 pins sunk
IIO = 10 mA,VDD = 3.3 V
1000(1)
Output low level with 8 pins sunk
IIO = 10 mA,VDD = 5.0 V
800
Output low level with 4 pins sunk
IIO = 20 mA,VDD = 5.0 V
1500(1)
Output high level with 4 pins sourced
IIO = 10 mA, VDD = 3.3 V
2.1(1)
Output high level with 8 pins sourced
IIO = 10 mA, VDD = 5.0 V
4.0
Output high level with 4 pins sourced
IIO = 20 mA, VDD = 5.0 V
3.3(1)
Unit
mV
V
1. Data based on characterization results, not tested in production
41/56
Electrical characteristics
STM8S103xx, STM8S105xx
Figure 16. Typ. VOL @ VDD = 3.3 V (standard
ports)
Figure 17. Typ. VOL @ VDD = 5.0 V (standard
ports)
-40°C
1.5
-40°C
1.5
25°C
25°C
85°C
1.25
85°C
1.25
125°C
125°C
1
VOL [V]
VOL [V]
1
0.75
0.75
0.5
0.5
0.25
0.25
0
0
0
1
2
3
4
5
6
7
0
2
4
6
IOL [mA]
Figure 18. Typ. VOL @ VDD = 3.3 V (true open
drain ports)
25°C
1.75
85°C
125°C
1.5
125°C
1.25
VOL [V]
VOL [V]
85°C
1.5
1.25
1
0.75
1
0.75
0.5
0.5
0.25
0.25
0
0
0
2
4
6
8
10
12
14
0
5
10
IOL [mA]
25°C
85°C
85°C
1.25
125°C
125°C
1
1
VOL [V]
VOL [V]
25
-40°C
1.5
25°C
1.25
20
Figure 21. Typ. VOL @ VDD = 5.0 V (high sink
ports)
-40°C
1.5
15
IOL [mA]
Figure 20. Typ. VOL @ VDD = 3.3 V (high sink
ports)
0.75
0.75
0.5
0.5
0.25
0.25
0
0
0
2
4
6
8
IOL [mA]
42/56
12
-40°C
2
25°C
1.75
10
Figure 19. Typ. VOL @ VDD = 5.0 V (true open
drain ports)
-40°C
2
8
IOL [mA]
10
12
14
0
5
10
15
IOL [mA]
20
25
STM8S103xx, STM8S105xx
Electrical characteristics
Figure 22. Typ. VDD - VOH @ VDD = 3.3 V
(standard ports)
Figure 23. Typ. VDD - VOH @ VDD = 5.0 V
(standard ports)
-40°C
2
1.75
125°C
85°C
125°C
1.5
1.25
VDD - V OH [V]
VDD - V OH [V]
25°C
1.75
85°C
1.5
-40°C
2
25°C
1
0.75
1.25
1
0.75
0.5
0.5
0.25
0.25
0
0
0
1
2
3
4
5
6
7
0
2
4
6
IOH [mA]
Figure 24. Typ. VDD - VOH @ VDD = 3.3 V (high
sink ports)
125°C
85°C
125°C
1.5
1.25
VDD - V OH [V]
VDD - V OH [V]
25°C
1.75
85°C
1.5
12
-40°C
2
25°C
1.75
10
Figure 25. Typ. VDD - VOH @ VDD = 5.0 V (high
sink ports)
-40°C
2
8
IOH [mA]
1
0.75
1.25
1
0.75
0.5
0.5
0.25
0.25
0
0
0
2
4
6
8
IOH [mA]
10
12
14
0
5
10
15
20
25
IOH [mA]
43/56
Electrical characteristics
7.3.2
STM8S103xx, STM8S105xx
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 18.
NRST pin characteristics(1)
Symbol
Parameter
Conditions
Typ
Min
Max
1)
VIL(NRST)
NRST Input low level voltage (2)
VSS
TBD
VIH(NRST)
NRST Input high level voltage (2)
TBD
VDD
VOL(NRST)
NRST Output low level voltage (2)
RPU(NRST)
NRST Pull-up resistor (3)
IOL=TBD mA
30
40
60
kΩ
VF(NRST)
NRST Input filtered pulse (4)
TBD
ns
VNF(NRST)
NRST Input not filtered pulse (4)
TBD
µs
2. Data based on characterization results, not tested in production.
3. The RPU pull-up equivalent resistor is based on a resistive transistor
Data guaranteed by design, not tested in production.
Figure 26. Typical NRST VIL and VIH vs VDD @ 4 temperatures
-40°C
6
25°C
85°C
5
125°C
VIL / V IH [V]
4
3
2
1
0
2.5
3
3.5
4
4.5
VDD [V]
44/56
V
TBD
1. TBD = to be determined.
4.
Unit
5
5.5
6
STM8S103xx, STM8S105xx
Electrical characteristics
Figure 27. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures
-40°C
60
NRST Pull-Up resistance [k ohm]
25°C
55
85°C
125°C
50
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 28. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures
140
NRST Pull-Up current [µA]
120
100
80
60
-40°C
25°C
40
85°C
20
125°C
0
0
1
2
3
VDD [V]
4
5
6
The reset network shown in Figure 29 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 14. Otherwise the reset is not taken into account internally.
Figure 29. Recommended reset pin protection
STM8
VDD
RPU
External
reset
circuit
NRST
Filter
Internal reset
0.01µF
45/56
Package characteristics
8
STM8S103xx, STM8S105xx
Package characteristics
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK® specifications are available at www.st.com.
46/56
STM8S103xx, STM8S105xx
Package characteristics
8.1
Package mechanical data
8.1.1
LQFP package mechanical data
Figure 30. 48-pin low profile quad flat package (7 x 7)
A
D
A2
D1
A1
b
e
E1
E
c
L1
L
Table 19.
θ
48-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
C
0.09
Max
0.0630
0.15
0.0020
0.0059
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.20
0.0035
0.0079
D
9.00
0.3543
D1
7.00
0.2756
E
9.00
0.3543
E1
7.00
0.2756
e
0.50
0.0197
q
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
1.00
0.0394
1. Values in inches are converted from mm and rounded to 4 decimal digits
47/56
Package characteristics
STM8S103xx, STM8S105xx
Figure 31. 44-pin low profile quad flat package (10 x 10)
A
D
A2
D1
A1
b
e
E1
E
c
L1
L
h
Table 20.
44-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
1.60
A1
0.05
A2
1.35
b
0.30
C
0.09
Max
0.0630
0.15
0.0020
0.0059
1.40
1.45
0.0531
0.0551
0.0571
0.37
0.45
0.0118
0.0146
0.0177
0.20
0.0035
0.0079
D
12.00
0.4724
D1
10.00
0.3937
E
12.00
0.4724
E1
10.00
0.3937
e
0.80
0.0315
q
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
1.00
1. Values in inches are converted from mm and rounded to 4 decimal digits
48/56
Typ
0.0394
STM8S103xx, STM8S105xx
Package characteristics
Figure 32. 32-pin low profile quad flat package (7 x 7)
D
A
A2
D1
A1
e
b
E1 E
c
L1
L
h
Table 21.
32-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.30
C
0.09
Max
0.0630
0.15
0.0020
0.0059
1.40
1.45
0.0531
0.0551
0.0571
0.37
0.45
0.0118
0.0146
0.0177
0.20
0.0035
0.0079
D
9.00
0.3543
D1
7.00
0.2756
E
9.00
0.3543
E1
7.00
0.2756
e
0.80
0.0315
q
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
1.00
0.0394
1. Values in inches are converted from mm and rounded to 4 decimal digits
49/56
Package characteristics
8.1.2
STM8S103xx, STM8S105xx
QFN package mechanical data
Figure 33. 32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
E2
E
b
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
Table 22.
42_ME
32-lead very thin fine pitch quad flat no-lead package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A
0.80
0.90
1.00
0.0315
0.0354
0.0394
A1
0
0.02
0.05
0.0008
0.0020
A3
0.20
0.0079
b
0.18
0.25
0.30
0.0071
0.0098
0.0118
D
4.85
5.00
5.15
0.1909
0.1969
0.2028
D2
3.20
3.45
3.70
0.1260
E
4.85
5.00
5.15
0.1909
0.1969
0.2028
E2
3.20
3.45
3.70
0.1260
0.1358
0.1457
e
L
0.50
0.30
ddd
0.40
0.0197
0.50
0.0118
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits
1. TBD = to be determined.
50/56
0.1457
0.0157
0.0197
0.0031
STM8S103xx, STM8S105xx
8.1.3
Package characteristics
TSSOP package mechanical data
Figure 34. TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch
D
20
11
c
E1
1
E
10
α
L
A1
A
A2
L1
CP
b
e
TSSOP20-M
Table 23.
TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.2
A1
0.05
A2
0.8
b
0.19
1
CP
0.0472
0.15
0.002
1.05
0.0315
0.3
0.0075
0.0059
0.0394
0.09
D
6.4
E
0.0413
0.0118
0.1
c
Max
0.0039
0.2
0.0035
6.5
6.6
0.252
0.2559
0.2598
6.2
6.4
6.6
0.2441
0.252
0.2598
E1
4.3
4.4
4.5
0.1693
0.1732
0.1772
e
-
0.65
-
-
0.0256
-
L
0.45
0.6
0.75
0.0177
0.0236
0.0295
L1
a
1
0°
0.0079
0.0394
8°
0°
8°
1. Values in inches are converted from mm and rounded to 4 decimal digits
51/56
Ordering information
9
STM8S103xx, STM8S105xx
Ordering information
Figure 35. STM8S103/105 access line ordering information scheme
Example:
STM8
S
103
F
3
P
6
B
Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type
105 = intermediate peripheral set
103 = small peripheral set
Pin count
F = 20 pins
K = 32 pins
S = 44 pins
C = 48 pins
R = 64 pins
Program memory size
2 = 4 Kbytes
3 = 8 Kbytes
4 = 16 Kbytes
6 = 32 Kbytes
Package type
P = TSSOP
U = VFQFPN
T = LQFP
Temperature range
6 = -40 °C to 85 °C
Package pitch
no character = 0.5 mm
B = 0.65 mm
C = 0.8 mm
Packing
no character = tray or tube
TR = tape and reel
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please go to www.st.com or contact the ST Sales
Office nearest to you.
52/56
STM8S103xx, STM8S105xx
10
STM8 development tools
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
10.1
Emulation and in-circuit debugging tools
The STM8 tool line includes the full-featured STice emulation system offering a complete
range of emulation and in-circuit debugging features on a platform that is designed for
versatility and cost-effectiveness. In addition, STM8 application development is supported
by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including profiling and coverage to help detect
and eliminate bottlenecks in application execution and dead code when fine tuning an
application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
STice key features
●
Occurrence and time profiling and code coverage (new features)
●
Advanced breakpoints with up to 4 levels of conditions
●
Data breakpoints
●
Program and data trace recording up to 128 K records
●
Read/write on the fly of memory during emulation
●
In-circuit debugging/programming via SWIM protocol
●
8-bit probe analyzer
●
1 input and 2 output triggers
●
Power supply follower managing application voltages between 1.62 to 5.5 V
●
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements
●
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8
53/56
STM8 development tools
10.2
STM8S103xx, STM8S105xx
Software tools
STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer
(STVP) software interface. STVD provides seamless integration of the cosmic C compiler for
STM8, which is available in a free version that outputs up to 16 Kbytes of code.
10.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST visual develop – Full-featured integrated development environment from ST, featuring
●
Seamless integration of C and ASM toolsets
●
Full-featured debugger
●
Project management
●
Syntax highlighting editor
●
Integrated programming interface
●
Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash memory. STVP also offers project
mode for saving programming configurations and automating programming sequences.
10.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
10.3
●
Cosmic C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.cosmic-software.com.
●
Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
●
ST7/STM8 assembler linker – Free assembly toolchain included in the ST7/STM8
toolset, which allows you to assemble and link your application source code.
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
54/56
STM8S103xx, STM8S105xx
11
Revision history
Revision history
Table 24.
Document revision history
Date
Revision
Changes
05-Jun-2008
1
Initial release.
23-Jun-2008
2
Corrected number of high sink outputs to 9 in I/Os on page 1.
Updated part numbers in Table 2: STM8S103/105 access line
features on page 7.
55/56
STM8S103xx, STM8S105xx
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2008 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
56/56