Data Sheet, V1.0, Aug. 1999 FOA3251B1 High Speed Clock and Data Recovery for Fiber Optic Applications ICs for Communications N e v e r s t o p t h i n k i n g . FOA3251B1 S1028C1 Revision History: 1999-08 V1.0 Previous Version: Page Subjects (major changes since last revision) Document’s layout has been changed: 2002-Sep. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com. ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG. Edition 1999-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2002. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life-support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. FOA3251B1 S1028C1 Preface The transceiver IC FOA3251 is designed for fibre optic application in the data bit range of 2.5 GBit. The FOA3251 fulfills the jitter requirements specified in ITU G958 and Bellcore GR253. Organization of this Document This Data Sheet is divided into 8 chapters. It is organized as follows: • Chapter 1, Overview Gives a general description of the product , lists the key features, and presents some typical applications. • Chapter 2, Functional Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. Blockdiagram and block description. • Chapter 3, Operational Description • Chapter 4, Electrical Characteristics DC and AC Characteristics, Power consumption, interface specification. • Chapter 5, External Components Application notes and recommended suppliers • Chapter 6, Measurement Results • Chapter 7, Package Outlines Data Sheet 3 V1.0, 1999-08 FOA3251B1 S1028C1 Table of Contents Page 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 2.1 2.2 2.3 2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating States of Delay Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 4.1 4.2 4.3 4.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data Sheet 4 6 6 7 9 9 12 12 12 13 13 V1.0, 1999-08 High Speed Clock and Data Recovery for Fiber Optic Applications FOA3251B1 S1028C1 BIPOLAR 1 Overview The transceiver IC FOA3251 is designed for fibre optic application in the data bit range of 2.5 GBit. The FOA3251 fulfills the jitter requirements specified in ITU G958 and Bellcore GR253. 1.1 Features P-LQFP-48-1 • Data rate up to 2.633 Gb/s P-LQFP-48-1 • All jitter data meet ITU-T G958 and GR-253-Core requirements • Supply range from +3.0 V to 5.0 V • Supply current < 210 mA • Input sensitivity < 5 mVpp differential (BER = 10-12) • Loss of signal (LOS) detection • Programmable delay element to adjust clock- to data output • Lock indication 1.2 Applications • Fibre optic communication systems • SDH / SONET / ATM applications Type Ordering Code FOA3251B1 Data Sheet Package P-LQFP-48-1 5 V1.0, 1999-08 FOA3251B1 S1028C1 Functional Description 2 Functional Description The FOA3251 consists of a clock and data recovery block (CDR), a clock multiplier unit (CMU) and a programmable delay line. Pin Configuration (top view) VEE VCC alarm LOL LOS RESET XTAL IN XTAL OUT VCC VCC DELAY2 DELAY1 DELAY0 2.1 36 35 34 33 32 31 30 29 28 27 26 25 LLOS 37 24 N2V5 38 23 VCC DATA IN VCC DATA IN VCC VF01 VCC PLL1 UP PLL1 DN TEST 39 22 40 21 41 20 42 19 P-LQFP-48-1 43 18 44 17 45 16 46 15 47 14 48 13 VCC VCC VCC CLK TR CLK TR VCC DATA TR DATA TR VCC VCC VEE VEE Figure 1 Data Sheet VEELC VCCLC VCC VCC VCC VCC VCC PLL2 DN PLL2 UP VF02 TESTLOS TESTCLK 1 2 3 4 5 6 7 8 9 10 11 12 ITP11416 Pin Configuration 6 V1.0, 1999-08 FOA3251B1 S1028C1 Functional Description 2.2 Pin Definition and Function 7 Table 1 Pin Definition and Function Pin Symbol Input (I) Function Output (O) 1 TESTCLK In 2 TESTLOS In 3 VCC 4 VCC Can be open. 5 VCC Can be open. 6 VCC 7 VCC In Can be open. 8 PLL2 DN Out Inverted down signal from PLL2 9 PLL2 UP Out Inverted up signal from PLL2 10 VF02 In Control voltage for VCO2 11 VCCLC VCC VCO2 12 VEELC VEE VCO2 13 VEE 14 VEE 15 VCC 16 VCC 17 DATA TR Out Inverted recovered data signal 18 DATA TR Out Recovered data signal 19 VCC 20 CLK TR Out Recovered clock signal 21 CLK TR Out Inverted recovered clock signal 22 VCC 23 VCC 24 VCC 25 DELAY0 In Delay select bit 0. (See Table 2) 26 DELAY1 In Delay select bit 1. (See Table 2) 27 DELAY2 In Delay select bit 2. (See Table 2) 28 VCC Data Sheet Clock signal for test mode only 7 V1.0, 1999-08 FOA3251B1 S1028C1 Functional Description Table 1 Pin Definition and Function (cont’d) Pin Symbol Input (I) Function Output (O) 29 VCC 30 XTAL OUT Out Crystal 31 XTAL IN In Crystal 32 RESET In Reset for test mode only 33 LOS Out Loss of signal (ESD only to VEE) 34 LOL Out Loss of Lock 35 VCC alarm 36 VEE 37 LLOS In Adjustment for Level LOS 38 N2V5 In Negative supply voltage for VCO1 39 VCC 40 DATA IN In Inverted data input (no ESD) 41 VCC 42 DATA IN In Data input (no ESD) 43 VCC 44 VF01 In Control voltage VCO1 45 VCC 46 PLL1 UP Inverted up signal PLL1 47 PLL1 DN Inverted down signal PLL1 48 TEST Data Sheet VCC alarm supply. Max. 5 V, Min 0 V = VCC (no ESD) In Test mode on/off 8 V1.0, 1999-08 FOA3251B1 S1028C1 Functional Description 2.3 Functional Block Diagram LOL Delay Line FWD REFCLK TRCLK CDR VCO VCO Loop Filter Recovered Clock PFD CMU Loop Filter Postamp DATA PD Recovered DATA 2.4 D TRDATA ITB11417 LOS Figure 2 C Block Diagram Functional Block Description The clock and data recovery block (CDR) consists of a bang-bang phase detector (PD), a frequency window detector (FWD) and a VCO. The PD also provides a kind of statistical BER signal that is used to generate a loss of signal (LOS) signal. The FWD moves the VCO in the right frequency range. The frequency window is about 10000 ppm of the center frequency. When the frequency is out of range a los of lock signal (LOL) is generated. The center frequency is given by a reference clock signal which is (signal frequency)/128. The VCO is a 3 stage ring oscillator type. The clock multiplier unit (CMU) consist of a phase frequency detector (PFD), a VCO and a retiming Flip-Flop. The PFD is type 4 phase and frequency detector. The low pass filtered PFD signal as a function of the phase error is shown in Figure 3. Data Sheet 9 V1.0, 1999-08 FOA3251B1 S1028C1 Functional Description Vpfd Kd2π -4π -2π 2π 4π υe -Kd2π ITD11418 Figure 3 PFD Characteristic The VCO is a LC type with a center frequency of 2.5 GHz. The measured tuning range is shown in Figure 4. ITD11419 3 GHz Frequency 2.8 2.6 m25 Center Freq. [GHz] 20 Center Freq. [GHz] 85 Center Freq. [GHz] 2.4 2.2 2 0 -2 -1 V -3 Tuning Voltage Figure 4 Tuning Range LC VCO The delay line is programmable in 8 steps of about 50 ps. The clock signal is adjustable over 1 period (400 as) and can be easily adapted to different applications. Data Sheet 10 V1.0, 1999-08 FOA3251B1 S1028C1 Operational Description 3 Operational Description 3.1 Operating States of Delay Line For clock to data output adjustment a adjustable delay line is available. The clock output signal is adjustable by the signals DELAY0..2. Table 2 Truth Table Delay Line DELAY0 DELAY1 DELAY2 Delta LOW LOW LOW 0 ps LOW HIGH LOW 50 ps LOW LOW HIGH 100 ps LOW HIGH HIGH 150 ps HIGH LOW LOW 200 ps HIGH HIGH LOW 250 ps HIGH LOW HIGH 300 ps HIGH HIGH HIGH 350 ps Data Sheet 11 V1.0, 1999-08 FOA3251B1 S1028C1 Electrical Characteristics 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Table 3 Absolute Maximum Ratings Parameter Symbol Limit Values min. IC supply voltage (VCC - VEE) Unit max. 6 Voltage on any pin VS -0.4 V VDDP + 0.4 Maximum junction temperature 125 Storage temperature Tstg -40 150 Protection supply voltage VDDP VEE - 0.5 VCC ESD robustness HBM: 1.5 kΩ, 100 pF VESD,HBM °C V 500 Lead temperature range Package The RF Pin 40, 42 are not ESD protected. The high frequency performance prohibits the use of a adequate protective structure. Pin 33 is only protected to VEE. 4.2 Table 4 Operating Range Operating Range Parameter Symbol Limit Values min. max. Unit Ambient temperature TA -40 85 °C Supply voltage VDD 3.0 5 V Data Sheet 12 V1.0, 1999-08 FOA3251B1 S1028C1 Electrical Characteristics 4.3 DC Characteristics Table 5 DC Characteristics Parameter Symbol Limit Values min. Control and Test inputs Unit max. VIL VIH VCC - 1 Output current CML Pin 17, 18, 20, 21 Ioc 8 0.45 mA Supply current IEE (AV) 200 TBD mA 4.4 V VCC AC Characteristics Table 6 Electrical Characteristics Parameter Condition Limit Values min. typ. Unit max. Quantisizer DC Characteristics1) Pin or Nin 2) VEE +2.5 -12 Input Voltage Range Pin-Nin, BER < 10 Input Sensitivity, Vsense Pin-Nin, BER < 10-12 Input Overdrive, Vod VCC 10 V mV V 2 Input Offset Voltage mV 10 µA Input Current Input RMS Noise BER < 10-12 TBD Input Pk-Pk Noise BER < 10-12 TBD µV Quantisizer AC Characteristics Upper -3 dB Bandwidth extern) Input Resistance Package 2.5 GHz 50 Ω 0.8 pF Input Capacitance Pulse Width Distortion VSWR Data Sheet 2.5 13 V1.0, 1999-08 FOA3251B1 S1028C1 Electrical Characteristics Table 6 Electrical Characteristics (cont’d) Parameter Condition Limit Values min. typ. Unit max. Level Detect Response Time AC coupled Hysteresis (Electrical)3) 1 ALM Output Logic High4) VCC alarm = 5 V 4.5 ALM Output Logic Low VEE alarm = GND 1 ALM Output Logic High VCC alarm = GND -0.5 ALM Output Logic Low VEE alarm = -5 V -4 95 µs 3 db V Phase-Locked Loop 2.48832 Nominal Center Frequency f0 Capture Range5) Tracking Range 6) Static Phase Error 7) Phase drift GHz -0.2% x f0 +0.2% x f0 GHz -0.2% x f0 +0.2% x f0 -3.6 +3.6 100 deg. Bit Jitter SONET STS-48 Frame (with Scrambler 2E7-1) and 2E23-1 PRN Sequence ITU-T G958 and Gr-253-Core objective < 0.005 UIrms (2ps) Jitter Tolerance SONET STS-48 Frame (with Scrambler 2E7-1) and 2E23-1 PRN Sequence ITU-T G958 and Gr-253-Core Jitter Transfer SONET STS-48 Frame (with Scrambler 2E7-1) and 2E23-1 PRN Sequence ITU-T G958 and Gr-253-Core Open collector output Referenced to VCC Voltage levels Output logic High, Voh 0 V Output logic Low, Vol 400 V Symmetry (Duty Cycle) Recovered Clock Output Data Sheet 46 14 54 V1.0, 1999-08 FOA3251B1 S1028C1 Electrical Characteristics Table 6 Electrical Characteristics (cont’d) Parameter Condition Limit Values min. typ. Unit max. Output Rise/Fall Times Clock Output Rise Time 20% - 80%, 50 Ω 100 ps Fall Time 20% - 80%, 50 Ω 100 ps Rise Time 20% - 80%, 50 Ω 120 ps Fall Time 20% - 80%, 50 Ω 120 ps Control and test inputs8) Referenced to VCC Input logic High, Vih 0 V Input logic Low, Vil -1 V Output logic High, Vih 0 V Output logic Low, Vil -1 V Data Output Control and test outputs Referenced to VCC Power Supply Voltage 3 Power Supply Current9) 5 5.8 V 210 mA Operating Temperature Package Ambient -40 +85 °C Bare Chip Ambient -40 +100 °C Bare Chip Size < 3.0 mm x 3.0 mm 1) 2) 3) 4) 5) 6) 7) 8) 9) Min value Pin, Nin: VCC-Pin, Nin < 800 mV Voltage (Pin-Nin) = 4 mVpp @Pin = -23 dBm Hysteresis can be installed by a combination of Signal LOS and LLOS. Open Collector Output type, I = 2 mA. Datarate depends on output load. Termination with pullup resistor > 4.7 kΩ No skipping clock cycles allowed down to < 10-3 BER External adjustable. Clock drift with no input 25 MHz The alarm shall be asserted before 500 ns of phase shift on the RX clock is realized. Consecutive identical bits 72 bits. Supply current = IEE ( current without ECL output current). Data Sheet 15 V1.0, 1999-08 FOA3251B1 S1028C1 External Components 5 External Components Crystal Integrator Integrator Infineon - FOA3251B1 2.488 Gb/s Transceiver and Clock/Data Recovery Data IN Reference Voltage Data OUT Clock OUT ITS11420 Figure 5 External Components Required for Operation of FOA3251B1 Table 7 External Devices Device Number Recommended Types Remark Reference Voltage 1-2 TL 431 2.5 V VCO Supply Operational Amplifier 1 Burr Brown OPA2353 Burr Brown OPA2350 Integrator Capacitor 10 5 Integrator, Blocking Resistor 14 Integrator, Reference voltage Crystal Oscillator 1 Toyocom TSX-2 19.44 MHz Ferrite Bead Inductor 2 muRata BLM11B601S VEE blocking to GND (VCC) The external circuits are shown in Figure 6, Figure 7, Figure 8 and Figure 9. Data Sheet 16 V1.0, 1999-08 FOA3251B1 S1028C1 External Components 2.5 V Referenz Voltage VCC 1 TL431 10 µF 2, 3 6, 7 5 N2V5 56 Resistor has to be adapted to supply voltage. 3.3 V 56 5.0 V 80 VEE Figure 6 ITS11421 Reference Voltage for VCO (Ring Oscillator). FOA3251 VCC VCC 100 100 pF 800 100 nF 100 pF 100 nF 800 100 nF 1k PLL1 DN 100 VF01 PLL1 UP 1k 100 100 nF Figure 7 Data Sheet ITS11422 Loop Filter PLL1 (CDR) 17 V1.0, 1999-08 FOA3251B1 S1028C1 External Components FOA3251 VCC VCC 1.5 k 10 pF 800 10 pF 470 fF 800 47 nF PLL2 UP 6.8 k 100 VF02 PLL2 DN 6.8 k 1.5 k 47 nF Figure 8 ITS11423 Loop Filter PLL2 (CMU) TSX-2 XTAL IN XTAL OUT 33 pF 56 pF ITS11424 VCC Figure 9 Data Sheet Crystal Oscillator 18 V1.0, 1999-08 FOA3251B1 S1028C1 Measurement Results 6 Measurement Results All measurements were done with 50 mVpp input swing and a 2E23 bit sequence. Temperature was 25°C, supply voltage was 3.3 V. ITD11425 102 101 100 10-1 101 102 103 104 105 106 Hz 107 Modulation Frequency Figure 10 STM 16 Jitter Tolerance ITD11426 10 0 -10 -20 -30 101 102 103 104 105 106 Hz 107 Modulation Frequency Figure 11 Data Sheet STM 16 Jitter Transfer 19 V1.0, 1999-08 FOA3251B1 S1028C1 Measurement Results Jitter Generation Results Cutoff Frequency = 12.000 kHz 16.281 mUI p-p 2.516 mUI rms Figure 12 Data Sheet ITD11427 Gitter Generation Results 20 V1.0, 1999-08 FOA3251B1 S1028C1 Package Outlines 7 Package Outlines 0.5 H 7˚ MAX. 0.125 +0.075 -0.035 0.1 ±0.05 1.4 ±0.05 1.6 MAX. P-LQFP-48-1 (Plastic Low Profile Quad Flat Package) 0.6 ±0.15 C 5.5 0.22 ±0.05 2) 0.08 0.08 M A-B D C 48x 9 0.2 A-B D 48x 7 1) 0.2 A-B D H 4x 1.76 x 45˚ D 9 B 7 1) A 3.96 ±0.05 48 Heatslug 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. per side GPP09269 Figure 13 You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 21 Dimensions in mm V1.0, 1999-08 Infineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher www.infineon.com Published by Infineon Technologies AG FOA3251B1 S1028C1 Variables Target Specification Variable Name Variable Definition Business Unit ICs for Communications Dev_NameLong1 High Speed Clock and Data Recovery for Fiber Optic Applications Description Long product name Dev_NameLong2 Dev_NameLong3 Dev_NameLong4 <Dev_NameLong4> Dev_NameShort1 FOA3251B1 Dev_NameShort2 <Dev_NameShort2> Dev_NameShort3 <Dev_NameShort3> Dev_NameShort4 <Dev_NameShort4> Dev_Package1 P-LQFP-48-1 Dev_Package2 <Dev_Package2> Dev_Package3 <Dev_Package3> Dev_Package4 <Dev_Package4> Dev_Version1 <Dev_Version1> Dev_Version2 <Dev_Version2> Dev_Version3 <Dev_Version3> Dev_Version4 <Dev_Version4> Device1 FOA3251B1 Device2 <Device2> Device3 <Device3> Device4 <Device4> Doc_Author <Author> Short product name Package type Marketing/sales name Author of the document Doc_ConfidentialStatus Data Sheet Device version „CONFIDENTIAL“, “PRELIMINARY” or left blank 23 V1.0, 1999-08 FOA3251B1 S1028C1 Variable Name Variable Definition Doc_Distribution Description "Distribution with NDA" or "Distribution by marketing only" or "Distribution with NDA by marketing only" or left blank Doc_IssueDate 1999-08 Complete date of releasing the document Doc_State V1.0 Revision state of the document Doc_TopRight1 FOA3251B1 Doc_TopRight2 S1028C1 Defines the expression appearing on the top right of the page layout Document type Doc_Type Data Sheet Document type Doc_Type_Cover Data Sheet Document type Modification Date Short Status Technologie BIPOLAR Title_IssueDate Aug. 1999 Data Sheet Issue date of the document appearing on the upper right corner of the 1st cover page 24 V1.0, 1999-08 FOA3251B1 S1028C1 Instructions Defining all variables 1. Double-Click on the Variable Definiton that you want to define. 2. Choose “Edit Definition” 3. In the variable dialog box redefine the user variable in the “Definition” box. If this variable should not be defined, enter a blank. 4. Click on “Change”. 5. Click “Done” to return to the variable dialog box. 6. Click “Done” again. Importing the variables into the FrameMaker document/book 1. Make certain that both documents (your FrameMaker file/book and file variables.fm) are open. 2. From the “File” menu, click on “Import”. 3. Select “Format”. 4. From the “Import from File” (document) pop-up list, choose “variables.fm”. 5. From the “Import and Update” box, make sure that only the “Variable Definition” check box is selected. Click on “Import” to finish. Data Sheet 25 V1.0, 1999-08