Supervisory Devices Complementary Parts Guide for Altera FPGAs Multivoltage Supervisors for Altera FPGAs ADI Multivoltage Monitors Altera FPGAs Altera FPGA Family Core Voltage (V) I/O Voltage (V) 0.9 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 0.9 or 1.1 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Stratix II GX 1.2 1.2, 1.5, 1.8, 2.5, 3.3 Stratix II 1.2 1.2, 1.5, 1.8, 2.5, 3.3 Stratix GX 1.5 1.5, 1.8, 2.5, 3.3 VOLTAGE Stratix 1.5 1.5, 1.8, 2.5, 3.3 CORE VOLTAGE Arria™ GX 1.2 1.2, 1.5, 1.8, 2.5, 3.3 Cyclone® III 1.2 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Cyclone II 1.2 1.5, 1.8, 2.5, 3.3 Cyclone 1.5 1.5, 1.8, 2.5, 3.3 Advanced fabrication techniques and smaller process geometries are resulting in a trend towards lower core voltages. This trend, coupled with legacy I/O standards, results in FPGA‑based designs with multiple voltage rails. To ensure system reliability, each of these rails should be supervised. Analog Devices offers an extensive portfolio of voltage supervisors, from simple single channel reset generators to multivoltage supervisors offering industry-leading threshold accuracy (±0.8%). As core voltages decrease, the importance of high threshold accuracy becomes increasingly important. Stratix® IV E/GX Stratix III The core and I/O voltage requirements of each Altera® FPGA family are listed in the Multivoltage Supervisors for Altera FPGAs selection table. Core voltages range from 0.9 V to 1.5 V, while the I/0 voltage levels are between 1.2 V and 3.3 V. High Accuracy Is Critical When Monitoring Low Voltage –5% TOLERANCE OUT1 INDUSTRY’S BEST ð0.8% THRESHOLD ACCURACY TIME FPGA CORE VOLTAGE FPGA CORE VOLTAGE I/O SUPPLY I/O SUPPLY I/O SUPPLY VIN2 VDD ADM13305 MR 1 ADM8616, ADM809, ADM6319 2 ADM13305 3 ADM13307 3 or 4 ADM6710 4 ADM1184 ADM13307 RESET FPGA WDI ADM6710 VIN1 ADM1184 VCC, IN2 VDD SENSE2 Part Number –3% SUPPLY REGULATION 2% RANGE FOR UV MONITORING SENSE1 Number of Voltages Monitored SENSE1 SENSE2 RESET FPGA SENSE3 FOUR VOLTAGE RAILS LOGIC RESET FPGA FOUR VOLTAGE RAILS VIN3 VIN2 OUT2 VIN3 VIN4 0.62V VREF ADM13307: ±0.8% accurate triple processor supervisor in 8-lead, narrow-body SOIC package. OUT1 VIN4 MR ADM13305: ±0.8% accurate dual processor supervisor with watchdog in 8-lead, narrow-body SOIC package. VIN1 ADM6710: ±1.5% accurate triple/quad voltage microprocessor supervisor in 6-lead SOT-23 package. INTERNAL LOGIC OUT3 PWRGD 0.60V REF ADM1184: ±0.8% accurate quad voltage monitor in 10-lead MSOP package. www.analog.com/power 82359_Altera.indd 1 8/28/08 9:50:34 AM Power Supply Sequencing FET Drive/Enable Programming Method Outputs Part Number Voltage Monitoring Accuracy (∙%) Sequence 1: cascadable ADM1085, ADM1086, ADM1087 <7 Up Enable R’s, C’s 6‑lead SC70 2: cascadable ADM6819, ADM6820 <2.6 Up FET drive R’s, C’s 6‑lead SOT‑23 4: cascadable ADM1184, ADM1185 <0.8 Up Enable R’s, C’s 10‑lead MSOP 4: cascadable ADM1186‑1 <0.8 Up, down Enable R’s, C’s 20‑lead QSOP 4 ADM1186‑2 <0.8 Up, down Enable R’s, C’s 16‑lead QSOP ADM1060 <2.5 Programmable logic Both SMBus 28‑lead TSSOP Number of Supplies Monitored 7: cascadable 8: cascadable ADM1068 <1 Programmable state machine Both SMBus VCC Package VCC VIN GND <1 Programmable state machine Both SMBus 40‑lead LFCSP, 32‑lead LQFP 10: cascadable ADM1062, ADM1063, ADM1064, ADM1065, ADM1067 <1 Programmable state machine Both SMBus 40‑lead LFCSP, 48‑lead TQFP 12: cascadable ADM1066 <1 Programmable state machine Both SMBus 40‑lead LFCSP, 48‑lead TQFP EN ADM1085 OUT 1.8V 3.3V V CtEN1 DC-TO-DC OUT CONVERTER OUT 12V IN 12V OUT 5V IN 5V OUT 3V IN 3V OUT MUX 1.2V ADP1706 OUT 2.5V VCC OUT1 OUT2 OUT3 VIN1 VIN2 VIN3 VIN4 PWRGD OUT3 PWRGD 3V OUT 190ms ADM1185 Timing Diagram INPUTS 1.8V OUT ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Printed in the U.S.A. G07477-5-8/08 2.5V OUT IN DC-DC EN OUT 1.8V OUT OUTPUTS EN IN LDO OUT 190ms SIGNAL VALID POWER ON 3.3V OUT RESET 190ms 0.9V OUT POWER GOOD 0.9V OUT IN INTERNAL/EXTERNAL TEMP SENSING DN ADM1184/ADM1185: ±0.8% accurate quad monitor and sequencer. SEQUENCING ENGINE OUT2 PWRGD 3.3V OUT IN DC-DC EN OUT 1.2V OUT VIN1 OUT3 IN DC-DC EN OUT 3.3V OUT 3.3V OUT 2.5V OUT OUT1 SMBus INTERFACE, 12-BIT ADC CONTROL LOGIC, AND EEPROM 5V OUT OUT2 FPGA IN EN OUT1 5V 1.8V Power-up sequencing with the ADM1085/ADM1086/ADM1087. VIN1 ADP1821 EN EN ENABLE CONTROL ADM1184 Timing Diagram IN 82359_Altera.indd 2 VIN ENOUT ADM1062 ADP2107 GND 3.3V DC-TO-DC OUT CONVERTER R PULLUP 5V IN Analog Devices, Inc. Worldwide Headquarters Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062‑9106 U.S.A. Tel: 781.329.4700 (800.262.5643, U.S.A. only) Fax: 781.461.3113 CEXT ENIN/ENIN EN IN 3.3V ADM1184/ ADM1185 ENOUT/ ENOUT PMOS PULL-UP ON ADM1086 ONLY 5V IN ADM1069 CAPACITOR ADJUSTABLE TIMEOUT - 32‑lead LQFP 8: cascadable EN + 0.6V 6 8-BIT DACS DP ADM1062: monitor and sequencer. EN OUT DC-DC TRIM SYSTEM RESET 1.2V OUT Analog Devices, Inc. Europe Headquarters Analog Devices, Inc. Wilhelm‑Wagenfeld‑Str. 6 80807 Munich Germany Tel: 49.89.76903.0 Fax: 49.89.76903.157 Analog Devices, Inc. Japan Headquarters Analog Devices, KK New Pier Takeshiba South Tower Building 1‑16‑1 Kaigan, Minato‑ku, Tokyo, 105‑6891 Japan Tel: 813.5402.8200 Fax: 813.5402.1064 Analog Devices, Inc. Southeast Asia Headquarters Analog Devices 22/F One Corporate Avenue 222 Hu Bin Road Shanghai, 200021 China Tel: 86.21.2320.8000 Fax: 86.21.2320.8222 www.analog.com/power 8/28/08 9:50:34 AM