BSS84 P-channel enhancement mode vertical DMOS transistor Rev. 06 — 16 December 2008 Product data sheet 1. Product profile 1.1 General description P-channel enhancement mode vertical Diffusion Metal-Oxide Semiconductor (DMOS) transistor in a small Surface-Mounted Device (SMD) plastic package. Table 1. Product overview Type number[1] BSS84 Package NXP JEDEC SOT23 TO-236AB BSS84/DG [1] /DG: halogen-free 1.2 Features n Low threshold voltage n High-speed switching n Direct interface to CMOS and Transistor-Transistor Logic (TTL) n No secondary breakdown 1.3 Applications n Line current interrupter in telephone sets n Relay, high-speed and line transformer drivers 1.4 Quick reference data n VDS ≤ −50 V n RDSon ≤ 10 Ω n ID ≤ −130 mA n Ptot ≤ 250 mW BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor 2. Pinning information Table 2. Pinning Pin Symbol Description 1 G gate 2 S source 3 D drain Simplified outline Graphic symbol 3 1 D 2 G SOT23 (TO-236AB) S 001aaa025 3. Ordering information Table 3. Ordering information Type number[1] Package Name BSS84 Description Version TO-236AB plastic surface-mounted package; 3 leads SOT23 BSS84/DG [1] /DG: halogen-free 4. Marking Table 4. Marking codes Type number[1] Marking code[2] BSS84 13* BSS84/DG ZV* [1] /DG: halogen-free [2] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China BSS84_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 16 December 2008 2 of 11 BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 150 °C - −50 V VGS gate-source voltage ID drain current - ±20 V Tsp = 25 °C; VGS = −10 V; see Figure 1 - −130 mA Tsp = 100 °C; VGS = −10 V - −75 mA - −520 mA - 250 mW IDM peak drain current Tsp = 25 °C; tp ≤ 10 µs; see Figure 1 Ptot total power dissipation Tsp = 25 °C; see Figure 2 Tstg storage temperature −65 +150 °C Tj junction temperature −65 +150 °C [1] [1] Device mounted on a Printed-Circuit Board (PCB). mld251 −103 tp = 10 µs 100 µs 1 ms (1) ID (mA) −102 10 ms 100 ms DC −10 −1 −1 −102 −10 VDS (V) Tsp = 25 °C (1) RDSon limitation Fig 1. Safe operating area; continuous and peak drain currents as a function of drain-source voltage BSS84_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 16 December 2008 3 of 11 BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor mld199 300 Ptot (mW) 200 100 0 0 Fig 2. 50 100 150 200 Tamb (°C) Power derating curve 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient see Figure 3 [1] [1] Min Typ Max Unit - - 500 K/W Mounted on a PCB, vertical in still air. mld250 103 Rth(j-a) (K/W) δ = 0.75 0.5 102 0.2 0.1 0.05 0.02 10 0.01 δ= P tp T 1 0 t tp T 10−1 10−6 Fig 3. 10−5 10−4 10−3 10−2 10−1 1 10 102 tp (s) 103 Transient thermal impedance from junction to ambient as a function of pulse duration BSS84_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 16 December 2008 4 of 11 BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor 7. Characteristics Table 7. Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit −50 - - V Tj = 25 °C −0.8 - −2 V Tj = −55 °C - - −1.8 V - - −100 nA Tj = 25 °C - - −10 µA Tj = 125 °C - - −60 µA Static characteristics V(BR)DSS drain-source breakdown ID = −10 µA; VGS = 0 V voltage VGS(th) gate-source threshold voltage IDSS drain leakage current ID = −1 mA; VDS = VGS; see Figure 8 VDS = −40 V; VGS = 0 V Tj = 25 °C VDS = −50 V; VGS = 0 V IGSS gate leakage current VGS = +20 V; VDS = 0 V - - 100 nA VGS = −20 V; VDS = 0 V - - 100 nA RDSon drain-source on-state resistance VGS = −10 V; ID = −130 mA; see Figure 5 and 7 - 6 10 Ω Dynamic characteristics |Yfs| transfer admittance VDS = −25 V; ID = −130 mA 50 - - mS Ciss input capacitance VGS = 0 V; VDS = −25 V; f = 1 MHz; see Figure 9 - 25 45 pF - 15 25 pF - 3.5 12 pF Coss output capacitance Crss reverse transfer capacitance ton turn-on time VDS = −40 V; VGS = 0 V to −10 V; ID = −200 mA; see Figure 10 and 11 - 3 - ns toff turn-off time VDS = −40 V; VGS = −10 V to 0 V; ID = −200 mA; see Figure 10 and 11 - 7 - ns BSS84_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 16 December 2008 5 of 11 BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor mld197 −600 VGS = −10 V −7.5 V ID −6 V mld198 60 VGS = −2.5 V −3 V −4 V −5 V RDSon (Ω) (mA) −400 40 −5 V −4 V −200 20 −7.5 V −3 V −2.5 V 0 0 −2 −4 −6 −8 −10 V 0 −1 −10 −12 VDS (V) Tj = 25 °C Fig 4. −10 −102 ID (mA) −103 Tj = 25 °C Output characteristics: drain current as a function of drain-source voltage; typical values Fig 5. mld196 −600 Drain-source on-state resistance as a function of drain current; typical values mld194 1.8 (1) ID (mA) RDSon RDSon(25°C) (2) −400 1.4 −200 1.0 0 0 −2 −4 −6 −8 0.6 −10 VGS (V) Tj = 25 °C; VDS = −10 V −50 0 50 100 Tj (°C) 150 (1) ID = −130 mA; VGS = −10 V (2) ID = −20 mA; VGS = −2.4 V Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 7. Normalized drain-source on-state resistance factor as a function of junction temperature BSS84_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 16 December 2008 6 of 11 BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor mld195 1.2 mld191 80 C (pF) VGSth VGSth(25°C) 60 1.0 40 Ciss 0.8 20 Coss Crss 0 0.6 −50 0 50 100 0 150 ID = −1 mA; VDS = VGS Fig 8. −10 −20 Tj (°C) VDS (V) −30 VGS = 0 V; f = 1 MHz Gate-source threshold voltage as a function of junction temperature Fig 9. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 8. Test information 10 % VDS = −40 V INPUT 90 % 10 % OUTPUT 0V ID −10 V 90 % 50 Ω ton mld189 Fig 10. Switching time test circuit mbb690 Fig 11. Input and output waveforms BSS84_6 Product data sheet toff © NXP B.V. 2008. All rights reserved. Rev. 06 — 16 December 2008 7 of 11 BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor 9. Package outline Plastic surface-mounted package; 3 leads SOT23 D E B A X HE v M A 3 Q A A1 1 2 e1 bp c w M B Lp e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max. bp c D E e e1 HE Lp Q v w mm 1.1 0.9 0.1 0.48 0.38 0.15 0.09 3.0 2.8 1.4 1.2 1.9 0.95 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 OUTLINE VERSION SOT23 REFERENCES IEC JEDEC JEITA TO-236AB EUROPEAN PROJECTION ISSUE DATE 04-11-04 06-03-16 Fig 12. Package outline SOT23 (TO-236AB) BSS84_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 16 December 2008 8 of 11 BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor 10. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes BSS84_6 20081216 Product data sheet - BSS84_5 Modifications: • Table 5 “Limiting values”: Ptot figure reference updated BSS84_5 20081209 Product data sheet - BSS84_4 BSS84_4 20070717 Product data sheet - BSS84_3 BSS84_3 20030804 Product specification - BSS84_2 BSS84_2 19970618 Product specification - BSS84_1 BSS84_1 19950407 Product specification - - BSS84_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 16 December 2008 9 of 11 BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor 11. Legal information 11.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 11.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 11.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 12. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] BSS84_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 16 December 2008 10 of 11 BSS84 NXP Semiconductors P-channel enhancement mode vertical DMOS transistor 13. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 11.1 11.2 11.3 11.4 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 December 2008 Document identifier: BSS84_6