IDT Dual-Port RAM Datasheet

IDT70V05S/L
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
Low-power operation
– IDT70V05S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V05L
Active: 380mW (typ.)
Standby: 660µW (typ.)
IDT70V05 easily expands data bus width to 16 bits or more
◆
◆
◆
◆
◆
◆
◆
◆
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OEL
OER
CEL
CER
R/WR
R/WL
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
BUSYL(1,2)
A12L
A0L
BUSYR(1,2)
Address
Decoder
MEMORY
ARRAY
13
CEL
OEL
R/WL
SEML
INTL(2)
Address
Decoder
A12R
A0R
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CER
OER
R/WR
SEMR
INTR(2)
2941 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
MARCH 2000
1
©2000 Integrated Device Technology, Inc.
DSC 2941/6
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port
SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bitor-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM
approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 400mW of power.
The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
I/O1L
I/O0L
N/C
OE L
R/W L
SEML
CE L
N/C
N/C
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
Pin Configurations(1,2,3)
12
13
14
58
57
56
15
16
IDT70V05J
J68-1(4)
55
17
68-Pin PLCC
Top View(5)
53
52
18
54
19
20
51
50
21
22
49
48
23
24
47
46
I/O7R
N/C
OE R
R/WR
SEM R
CE R
N/C
N/C
GND
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
45
25
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A5L
A4L
A3L
A2L
A1L
A0L
INT L
BUSY L
GND
M/S
BUSY R
INTR
A0R
A1R
A2R
A3R
A4R
,
2941 drw 02
N/C
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
A5L
2 1 68 67 66 65 64 63 62 61
60
59
SEML
CEL
6 5 4 3
OEL
10
11
R/WL
9 8 7
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O1L
I/O0L
INDEX
6.42
2
4
5
6
51
50
49
54
53
52
32
26
27
28
29
30
31
23
24
25
A4L
47
46
A3L
A2L
A1L
A0L
40
39
38
37
N/C
GND
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
SEMR
CER
OER
R/WR
20
21
22
64-Pin TQFP
Top View(5)
17
18
19
48
45
44
43
42
41
70V05PF
PN-64(4)
7
8
9
10
11
12
13
14
15
16
56
55
59
58
57
61
60
1
2
3
I/O6R
I/O7R
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
64
63
62
INDEX
36
35
34
33
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
2941 drw 03
,
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
51
11
A5L
50
A4L
48
A2L
46
44
42
40
38
A0L BUSYL M/S INTR A1R
36
A3R
49
A3L
47
A1L
45
35
A4R
34
A5R
53
A7L
52
10
55
A9L
54
09
A8L
32
A7R
33
A6R
08
56
57
A11L A10L
30
A9R
31
A8R
07
58
59
VCC A12L
28
A11R
29
A10R
06
60
61
N/C
N/C
26
GND
27
A12R
24
N/C
25
N/C
22
23
20
21
R/WR
SEML
41
39
37
A2R
IDT70V05G
G68-1(4)
68-Pin PGA
Top View(5)
CEL
64
65
04
43
INTL GND BUSYR A0R
62
63
05
A6L
OEL
SEMR
R/WL
03
67
66
I/O0L N/C
02
1
3
68
I/O1L I/O2L I/O4L
OER
2
4
I/O3L I/O5L
01
A
B
CER
5
7
9
11
13
15
GND I/O7L GND I/O1R VCC I/O4R
18
19
I/O7R
N/C
6
17
I/O6R
8
I/O6L
C
D
10
12
14
16
VCC I/O0R I/O2R I/O3R I/O5R
E
F
G
H
J
K
,
L
INDEX
2941 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking.
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enable
R/ WL
R/ WR
Read/Write Enable
OEL
OER
Output Enable
A 0L - A12L
A0R - A12R
Address
I/O0L - I/O7L
I/O0R - I/O7R
Data Input/Output
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/ S
Master or Slave Select
V CC
Power
GND
Ground
2941 tbl 01
6.42
3
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table: Non-Contention Read/Write Control
Inputs(1)
Outputs
CE
R/W
OE
SEM
I/O0-7
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATAIN
Write to Memory
L
H
L
H
DATAOUT
X
X
H
X
High-Z
Mode
Read Memory
Outputs Disabled
2941 tbl 02
NOTE:
1. A0L — A12L≠ A0R — A 12R
Truth Table II: Semaphore Read/Write Control(1)
Inputs(1)
Outputs
CE
R/W
OE
SEM
I/O0-7
H
H
L
L
DATAOUT
Read Data in Semaphore Flag
H
↑
X
L
DATAIN
Write I/O0 into Semaphore Flag
L
X
X
L
____
Mode
Not Allowed
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 -I/O 7. These eight semaphores are addressed by A0-A2.
6.42
4
2941 tbl 03
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Maximum Operating Temperature
and Supply Voltage(1)
Absolute Maximum Ratings(1)
Symbol
Commercial
& Industrial
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-55 to +125
o
C
IOUT
DC Output
Current
VTERM(2)
Rating
50
Grade
Ambient
Temperature
GND
Vcc
Commercial
0OC to +70OC
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
Industrial
mA
2941 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V.
Recommended DC Operating
Conditions
Symbol
Supply Voltage
GND
Ground
VIL
Capacitance (TA = +25°C, f = 1.0MHz)
CIN
COUT
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Max.
Unit
VIN = 3dV
9
pF
V OUT = 3dV
10
Parameter
VCC
VIH
Symbol
2941 tbl 05
NOTE:
1. This is the parameter TA.
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
2.0
____
Input High Voltage
Input Low Voltage
-0.5
(1)
V
(2)
VCC+0.3
____
0.8
V
V
2941 tbl 06
NOTES:
1. VIL> -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VCC +0.3V.
pF
2941 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitznce when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V05S
Symbol
Parameter
(1)
Test Conditions
Min.
70V05L
Max.
Min.
Max.
Unit
10
___
5
µA
|ILI|
Input Leakage Current
VCC = 3.6V, VIN = 0V to VCC
___
|ILO|
Output Leakage Current
VOUT = 0V to V CC
___
10
___
5
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
___
0.4
V
2.4
___
2.4
___
VOH
Output High Voltage
IOH = -4mA
V
2941 tbl 08
NOTE:
1. At VCC < 2.0V input leakages are undefined.
6.42
5
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)
70V05X15
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
CE = VIL, Outputs Open
SEM = VIH
f = fMAX(3)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
CEL or CER = VIH
Active Port Outputs Open,
f=fMAX(3)
Version
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Typ.(2)
Max.
Typ.(2)
Max.
Typ. (2)
Max.
Unit
COM'L
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
IND
S
L
____
____
____
140
130
225
195
130
125
210
180
mA
____
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
mA
IND
S
L
____
____
____
20
15
45
40
16
13
45
40
mA
____
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
mA
IND
S
L
____
____
____
80
75
130
115
75
72
125
110
mA
____
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
IND
S
L
____
____
____
1.0
0.2
15
5
1.0
0.2
15
5
mA
____
One Port CEL or
CER > VCC - 0.2V
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
mA
IND
S
L
____
____
____
80
75
130
115
75
70
120
105
mA
____
2941 tbl 09a
70V05X35
Com'l
& Ind
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
CEL or CER = VIH
Active Port Outputs Open,
f=fMAX(3)
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
One Port CEL or
CER > VCC - 0.2V
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
Max.
Typ. (2)
Max.
Unit
S
L
120
115
180
155
120
115
180
155
mA
IND
S
L
120
115
200
170
120
115
200
170
mA
COM'L
S
L
13
11
25
20
13
11
25
20
mA
IND
S
L
13
11
40
35
13
11
40
35
mA
COM'L
S
L
70
65
100
90
70
65
100
90
mA
IND
S
L
70
65
120
105
70
65
120
105
mA
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
COM'L
S
L
65
60
100
85
65
60
100
85
mA
IND
S
L
65
60
115
100
65
60
115
100
mA
Version
f = fMAX(3)
Typ.(2)
COM'L
Test Condition
CE = VIL, Outputs Open
SEM = VIH
70V05X55
Com'l
& Ind
2941 tbl 09b
NOTES:
1. “X” in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
6.42
6
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
3.3V
3.3V
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
590Ω
590Ω
3ns Max.
DATAOUT
BUSY
INT
DATAOUT
435Ω
30pF
435Ω
5pF*
Figures 1 and 2
2941 drw 05
2941 tbl 10
Figure 2. Output Test Load
*Including scope and jig.
(For tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Test Load
Timing of Power-Up Power-Down
CE
ICC
tPU
tPD
50%
ISB
50%
2941 drw 06
6.42
7
,
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70V05X15
Com'l Only
Symbol
Parameter
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
15
____
20
____
25
____
ns
tAA
Address Access Time
____
15
____
20
____
25
ns
tACE
Chip Enable Access Time(3)
____
15
____
20
____
25
ns
tAOE
Output Enable Access Time (3)
____
10
____
12
____
13
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
3
____
3
____
3
____
ns
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
READ CYCLE
tRC
(1,2)
tLZ
Output Low-Z Time
tHZ
Output High-Z Time(1,2)
tPU
Chip Enable to Power Up Time (1,2)
tPD
Chip Disable to Power Down Time (1,2)
____
15
____
20
____
25
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
10
____
ns
tSAA
Semaphore Address Access(3)
____
15
____
20
____
25
ns
2941 tbl 11a
70V05X35
Com'l
& Ind
Symbol
Parameter
70V05X55
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
____
55
____
ns
tAA
Address Access Time
____
35
____
55
ns
tACE
Chip Enable Access Time(3)
____
35
____
55
ns
____
20
____
30
ns
3
____
3
____
ns
3
____
3
____
ns
____
15
____
25
ns
0
____
0
____
ns
____
35
____
50
ns
15
____
ns
____
55
ns
tAOE
tOH
Output Enable Access Time
(3)
Output Hold from Address Change
(1,2)
tLZ
Output Low-Z Time
tHZ
Output High-Z Time(1,2)
tPU
Chip Enable to Power Up Time (1,2)
(1,2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
15
____
tSAA
Semaphore Address Access(3)
____
35
2941 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
6.42
8
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
CE
tAA
(4)
tACE
tAOE
(4)
OE
R/W
tLZ
tOH
(1)
VALID DATA
DATAOUT
(4)
tHZ
(2)
BUSYOUT
tBDD
(3,4)
2941 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, t AA or tBDD .
5. SEM = VIH.
6.42
9
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
70V05X15
Com'l Only
Symbol
Parameter
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
25
____
ns
12
____
15
____
20
____
ns
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
10
____
15
____
15
____
ns
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
____
WRITE CYCLE
tWC
tEW
tAW
Write Cycle Time
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
tAS
(3)
(3)
Write Pulse Width
tWP
tWR
tDW
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
tHZ
tDH
Data Hold Time
(1,2)
(4)
(1,2)
tWZ
Write Enable to Output in High-Z
10
____
12
____
15
ns
tOW
Output Active from End-of-Write (1,2,4)
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
2941 tbl 12a
70V05X35
Com'l
& Ind
Symbol
Parameter
70V05X55
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
35
____
55
____
ns
30
____
45
____
ns
ns
WRITE CYCLE
tWC
tEW
Write Cycle Time
Chip Enable to End-of-Write
(3)
tAW
Address Valid to End-of-Write
30
____
45
____
tAS
Address Set-up Time (3)
0
____
0
____
ns
tWP
Write Pulse Width
25
____
40
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
15
____
30
____
ns
____
15
____
25
ns
0
____
0
____
ns
____
15
____
25
ns
0
____
0
____
ns
5
____
5
____
ns
5
____
5
____
tHZ
tDH
tWZ
Output High-Z Time
Data Hold Time
(1,2)
(4)
(1,2)
Write Enable to Output in High-Z
tOW
Output Active from End-of-Write
tSWRD
SEM Flag Write to Read Time
tSPS
SEM Flag Contention Window
(1,2,4)
ns
2941 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. “X” in part number indicates power rating (S or L).
6.42
10
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
tWC
ADDRESS
tHZ (7)
OE
tAW
CE
or
SEM
(9)
tAS (6)
tWP
(2)
tWR
(3)
R/W
tWZ (7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
2941 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
tWC
ADDRESS
tAW
CE or SEM
(9)
(6)
tAS
tEW
(2)
tWR (3)
R/W
tDW
tDH
DATAIN
2941 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or t WP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIN. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
11
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
tAW
tOH
VALID ADDRESS
tACE
tWR
tEW
SEM
tDW
DATA0
tSOP
DATA OUT
VALID(2)
DATAIN VALID
tAS
tWP
tDH
R/W
tSWRD
OE
tAOE
tSOP
Write Cycle
Read Cycle
2941 drw 10
NOTE:
1. CE = V IH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
2941 drw 11
NOTES:
1. DOR = D OL = VIL, CER = CE L = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42
12
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70V05X15
Com'l Ony
Symbol
Parameter
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
20
ns
15
____
20
____
20
ns
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
tBDA
BUSY Disable Time from Address Not Matched
____
tBAC
BUSY Access Time from Chip Enable LOW
____
15
____
20
____
20
ns
tBDC
BUSY Dis able Time from Chip Enable HIGH
____
15
____
17
____
17
ns
5
____
5
____
5
____
ns
____
18
____
30
____
30
ns
12
____
15
____
17
____
ns
tAPS
Arbitration Priority Set-up Time
tBDD
BUSY Disable to Valid Data
tWH
Write Hold After BUSY
(2)
(3)
(5)
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write (4)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
17
____
ns
____
30
____
45
____
50
ns
____
25
____
35
____
35
ns
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
(1)
2941 tbl 13a
70V05X35
Com'l
& Ind
Symbol
Parameter
70V05X55
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
20
____
45
ns
tBDA
BUSY Disable Time from Address Not Matched
____
20
____
40
ns
tBAC
BUSY Ac cess Time from Chip Enable LOW
____
20
____
40
ns
tBDC
BUSY Disable Time from Chip Enable HIGH
____
20
____
35
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
35
____
40
ns
tWH
Write Hold After BUSY(5)
25
____
25
____
ns
0
____
0
____
ns
25
____
25
____
ns
____
60
____
80
ns
45
____
65
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY
(5)
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
(1)
____
ns
2941 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to “Timing Waveform of Read With BUSY (M/S = VIH)” or “Timing Waveform of Write With PortTo-Port Delay (M/S = VIL)”.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – t WP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' is part number indicates power rating (S or L).
6.42
13
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read with BUSY(2,4,5) (M/S=VIH)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDW
tDH
VALID
DATAIN "A"
tAPS
(1)
MATCH
ADDR"B"
tBDA
tBAA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD (3)
2941 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE) then BUSY is input. For this example, BUSY “A” = V IH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the port opposite from Port “A”.
6.42
14
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH
R/W"B"
(1)
(2)
2941 drw 13
,
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port “B” Blocking R/W“B”, until BUSY “B” goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE "A"
tAPS
(2)
CE "B"
tBAC
tBDC
BUSY "B"
2941 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
tAPS
(2)
MATCHING ADDRESS "N"
ADDR"B"
tBAA
tBDA
BUSY"B"
2941 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
15
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
70V05X15
Com'l Only
Symbol
Parameter
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
0
____
0
____
0
____
ns
0
____
0
____
0
____
ns
15
____
20
____
20
ns
15
____
20
____
20
ns
INTERRUPT TIMING
Address Set-up Time
tAS
tWR
Write Recovery Time
tINS
Interrupt Set Time
____
tINR
Interrupt Reset Time
____
2941 tbl 14a
70V05X35
Com'l
& Ind
Symbol
Parameter
70V05X55
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
25
____
40
ns
25
____
40
ns
tINS
tINR
Interrupt Set Time
____
Interrupt Reset Time
____
2941 tbl 14b
NOTES:
1. 'X' in part number indicates power rating (S or L).
6.42
16
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS
ADDR"A"
tAS
(2)
(3)
tWR
(4)
CE"A"
R/W"A"
tINS
(3)
INT"B"
2941 drw 16
tRC
INTERRUPT CLEAR ADDRESS
ADDR"B"
tAS
(2)
(3)
CE"B"
OE"B"
(3)
tINR
INT"B"
2941 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
17
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
R/WL
CEL
OEL
A12L-A0L
INTL
R/WR
CER
OER
A12R-A0R
L
L
X
1FFF
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
Set Right INTR Flag
X
L
L
1FFF
H
Reset Right INTR Flag
L
L
X
1FFE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
L
1FFE
L(2)
Function
(3)
X
X
INTR
H
(3)
2941tbl 15
NOTES:
1. Assumes BUSYL = BUSY R = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
CEL
CER
A12L-A0L
A12R-A0R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
2941 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push
pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. VIL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving low regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
2941 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
6.42
18
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
BUSY (L)
CE
MASTER
Dual Port
SRAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
SRAM
BUSY (L) BUSY (R)
MASTER
CE
Dual Port
SRAM
BUSY (L) BUSY (R)
SLAVE
CE
Dual Port
SRAM
BUSY (L) BUSY (R)
DECODER
Military, Industrial and Commercial Temperature Ranges
BUSY (R)
2941 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs.
Functional Description
The IDT70V05 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V05 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading address location
1FFE. Likewise, the right port interrupt flag (INTR) is set when the left
port writes to memory location 1FFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 1FFF. The
message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used
as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY logic is not desirable, the BUSY logic can be disabled by placing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
The BUSY outputs on the IDT 70V05 SRAM in master mode, are
push-pull type outputs and do not require pull up resistors to
operate. If these SRAMs are being expanded in depth, then the
BUSY indication for the resulting array requires the use of an external
AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V05 SRAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V05 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Semaphores
The IDT70V05 is a fast Dual-Port 8K x 8 CMOS Static RAM with
an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the DualPort SRAM to claim a privilege over the other processor for functions
defined by the system designer’s software. As an example, the
semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port SRAM or any other shared
resource.
The Dual-Port SRAM features a fast access time, and both ports are
6.42
19
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or accessed, at the same time with the only possible conflict arising from
the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
have an automatic power-down feature controlled by CE, the Dual-Port
SRAM enable, and SEM, the semaphore enable. The CE and SEM pins
control on-chip power down circuitry that permits the respective port to go
into standby mode when not selected. This is the condition which is shown
in Truth Table II where CE and SEM are both HIGH.
Systems which can best use the IDT70V05 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT70V05's hardware semaphores, which provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V05 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side
writes a one to that latch.
The eight semaphore flags reside within the IDT70V05 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which can
be accessed by either side through address pins A0 – A2. When accessing
the semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processor writes a zero to the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side during
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no longer
needs the resource, the entire system can hang up until a one is written
into that semaphore request latch.
6.42
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IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V05’s Dual-Port SRAM. Say the
8K x 8 SRAM was to be divided into two 4K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 4K of Dual-Port
SRAM, the processor on the left port could write and then read a
zero in to Semaphore 0. If this task were successfully completed
(a zero was read back rather than a one), the left processor would
assume control of the lower 4K. Meanwhile the right processor was
attempting to gain control of the resource after the left processor, it
would read back a one in response to the zero it had attempted to
write into Semaphore 0. At this point, the software could choose to try
and gain control of the second 4K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would lock out
the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
4K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port SRAM or other shared resources into eight parts. Semaphores
can even be assigned different meanings on different sides rather than
being given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
WRITE
D
SEMAPHORE
REQUEST FLIP FLOP
Q
Q
SEMAPHORE
READ
D
D0
WRITE
SEMAPHORE
READ
2941 drw 19
Figure 4. IDT70V05 Semaphore Logic
6.42
21
,
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
G
J
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
15
20
25
35
55
Commercial Only
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
S
L
Standard Power
Low Power
70V05
64K (8K x 8) 3.3V Dual-Port RAM
,
Speed in nanoseconds
2941 drw 20
Datasheet Document History
3/11/99:
6/9/99:
11/10/99:
3/10/00:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
Changed drawing format
Replaced IDT logo
Added 15 & 20ns speed grades
Upgraded DC parameters
Added Industrial Temperature information
Changed ±200mV to 0mV in notes
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6.42
22
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