CY7C026A16 K × 16 Dual-Port Static RAM CY7C026A 16 K × 16 Dual-Port Static RAM 16 K × 16 Dual-Port Static RAM Features Functional Description ■ True dual-ported memory cells that allow simultaneous access of the same memory location ■ 16 K × 16 organization (CY7C026A) ■ 0.35 micron CMOS for optimum speed and power ■ High speed access: 15, and 20 ns ■ Low operating power ■ Active: ICC = 180 mA (typical) ■ Standby: ISB3 = 0.05 mA (typical) ■ Fully asynchronous operation The CY7C026A is a low power CMOS 16 K × 16 dual-port static RAM. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The device can be utilized as standalone 16-bit dual-port static RAM or multiple devices can be combined to function as a 32-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. ■ Automatic power-down ■ Expandable data bus to 32 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■ Semaphores included to permit software handshaking between ports ■ INT flags for port-to-port communication ■ Separate upper-byte and lower-byte control ■ Pin select for Master or Slave ■ Commercial and Industrial temperature ranges ■ Available in 100-pin thin quad plastic flatpack (TQFP) ■ Pb-free packages available Cypress Semiconductor Corporation Document Number: 38-06046 Rev. *J • Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by the chip enable pin. The CY7C026A is available in 100-pin thin quad plastic flatpack (TQFP) packages. For a complete list of related documentation, click here. 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 18, 2015 CY7C026A Logic Block Diagram R/WL UBL R/WR UBR CEL CER LBL LBR OEL OER 8 I/O8L–I/O15L 8 8 I/O Control I/O0L–I/O7L 14 A0L–A13L Address Decode True Dual-Ported RAM Array 14 A0L–A13L CEL OEL R/WL SEML BUSYL INTL UBL LBL 8 I/O Control I/O8L–I/O15R I/O0L–I/O7R Address Decode 14 A0R–A13R 14 Interrupt Semaphore Arbitration [1] A0R–A13R CER OER R/WR SEMR [1] M/S BUSYR INTR UBR LBR Note 1. BUSY is an output in master mode and an input in slave mode. Document Number: 38-06046 Rev. *J Page 2 of 24 CY7C026A Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Selection Guide ................................................................ 5 Architecture ...................................................................... 6 Functional Overview ........................................................ 6 Write Operation ........................................................... 6 Read Operation ........................................................... 6 Interrupts ..................................................................... 7 Busy ............................................................................ 7 Master/Slave ............................................................... 7 Semaphore Operation ................................................. 8 Maximum Ratings ............................................................. 9 Operating Range ............................................................... 9 Electrical Characteristics ................................................. 9 Capacitance .................................................................... 10 AC Test Loads and Waveforms ..................................... 10 Data Retention Mode ...................................................... 11 Timing .............................................................................. 11 Document Number: 38-06046 Rev. *J Switching Characteristics .............................................. 12 Switching Waveforms .................................................... 14 Ordering Information ...................................................... 20 16 K × 16 Asynchronous Dual-Port SRAM ............... 20 Ordering Code Definitions ......................................... 20 Package Diagram ............................................................ 21 Acronyms ........................................................................ 22 Document Conventions ................................................. 22 Units of Measure ....................................................... 22 Document History Page ................................................. 23 Sales, Solutions, and Legal Information ...................... 24 Worldwide Sales and Design Support ....................... 24 Products .................................................................... 24 PSoC® Solutions ...................................................... 24 Cypress Developer Community ................................. 24 Technical Support ..................................................... 24 Page 3 of 24 CY7C026A Pin Configurations A7L A8L A9L A10L A11L A12L A13L LBL UBL CEL SEML R/WL VCC OEL I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O8L I/O9L Figure 1. 100-pin TQFP pinout (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC NC 3 73 NC NC 4 72 A6L I/O10L 5 71 A5L I/O11L 6 70 A4L I/O12L 7 69 A3L I/O13L 8 68 A2L GND 9 67 A1L I/O14L 10 66 A0L I/O15L 11 65 INTL VCC 12 64 BUSYL GND 13 63 GND I/O0R 14 62 M/S I/O1R 15 61 BUSYR I/O2R 16 60 INTR VCC 17 59 A0R I/O3R 18 58 A1R I/O4R 19 57 A2R I/O5R 20 56 A3R I/O6R 21 55 A4R NC 22 54 A5R NC 23 53 NC NC 24 52 NC NC 25 51 NC CY7C026A (16 K × 16) Document Number: 38-06046 Rev. *J A6R A7R A8R A9R A10R A11R A12R A13R LBR UBR CER SEMR GND R/WR OER I/O15R GND I/O14R I/O13R I/O12R I/O11R I/O10R I/O9R I/O8R I/O7R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 4 of 24 CY7C026A Pin Definitions Left Port Right Port Description CEL CER Chip enable R/WL R/WR Read/Write enable OEL OER Output enable A0L–A13L A0R–A13R Address I/O0L–I/O15L I/O0R–I/O15R Data bus input/output SEML SEMR Semaphore enable UBL UBR Upper byte select (I/O8–I/O15 for × 16 devices) LBL LBR Lower byte select (I/O0–I/O7 for × 16 devices) INTL INTR Interrupt flag BUSYL BUSYR Busy flag M/S Master or slave select VCC Power GND Ground NC No connect Selection Guide Parameter CY7C026A CY7C026A Unit -15 -20 Maximum access time 15 20 ns Typical operating current 190 180 mA Typical standby current for ISB1 (Both ports TTL level) Typical standby current for ISB3 (Both ports CMOS level) Document Number: 38-06046 Rev. *J 50 45 mA 0.05 0.05 mA Page 5 of 24 CY7C026A Architecture Functional Overview The CY7C026A consists of an array of 16K words of 16 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power down feature controlled by CE. Each port is provided with its own Output Enable control (OE), which allows data to be read from the device. Write Operation Data must be set up for a duration of tSD before the rising edge of R/W to either the R/W pin (see Figure 6 on page 15) or the CE pin (see Figure 7 on page 15). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port. Table 1. Non-Contending Read/Write Inputs Outputs UB LB SEM I/O8–I/O15 Operation CE R/W OE I/O0–I/O7 H X X X X H High Z High Z Deselected: Power-down X X X H H H High Z High Z Deselected: Power-down L L X L H H Data in High Z Write to upper byte only L L X H L H High Z Data in Write to lower byte only L L X L L H Data in Data in Write to both bytes L H L L H H Data out High Z Read upper byte only L H L H L H High Z Data out Read lower byte only L H L L L H Data out Data out Read both bytes X X H X X X High Z High Z Outputs disabled H H L X X L Data out Data out Read data in semaphore flag H H L H H L Data out Data out Read data in semaphore flag H X X X L Data in Data in Write DIN0 into semaphore flag H X H H L Data in Data in Write DIN0 into semaphore flag L X X L X L Not allowed L X X X L L Not allowed Read Operation When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is Document Number: 38-06046 Rev. *J asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Page 6 of 24 CY7C026A Interrupts The upper two memory locations may be used for message passing. The highest memory location (3FFF) is the mailbox for the right port and the second highest memory location (3FFE) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH) Function Left Port Right Port R/WL CEL OEL A0L–13L INTL R/WR CER OER A0R–13R INTR Set right INTR flag L L X 3FFF X X X X X L[2] Reset right INTR flag X X X X X X L L 3FFF H[3] Set left INTL flag X X X X L[3] L L X 3FFE X Reset left INTL flag X L L 3FFE H[2] X X X X X Busy Master/Slave The CY7C026A provides on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission. BUSY is asserted tBLA after an address match or tBLC after CE is taken LOW. A M/S pin is provided to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This allows the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Notes 2. If BUSYR = L, then no change. 3. If BUSYL = L, then no change. Document Number: 38-06046 Rev. *J Page 7 of 24 CY7C026A Semaphore Operation The CY7C026A provides eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 on page 8 shows sample semaphore operations. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. Table 3. Semaphore Operation Example I/O0–I/O15 Left I/O0–I/O15 Right No action Function 1 1 Semaphore free Status Left port writes 0 to semaphore 0 1 Left port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Document Number: 38-06046 Rev. *J Page 8 of 24 CY7C026A Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding maximum ratings [4] may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Static discharge voltage .......................................... >2001 V Latch-up current .................................................... >200 mA Operating Range Ambient temperature with power applied ................................... –55°C to +125 °C Range Supply voltage to ground potential ..............–0.3 V to +7.0 V DC voltage applied to outputs in High Z state .............................................–0.5 V to +7.0 V Ambient Temperature VCC 0 °C to +70 °C 5 V 10% –40 °C to +85 °C 5 V 10% Commercial Industrial DC input voltage [5] .....................................–0.5 V to + 7.0 V Electrical Characteristics Over the Operating Range CY7C026A Parameter Description -15 -20 Unit Min Typ Max Min Typ Max – – 2.4 – – V 0.4 – 0.4 V VOH Output HIGH voltage (VCC = Min., IOH = –4.0 mA) 2.4 VOL Output LOW voltage (VCC = Min., IOH = +4.0 mA) – VIH Input HIGH voltage 2.2 – 2.2 – V VIL Input LOW voltage – 0.8 – 0.8 V IOZ Output leakage current –10 10 –10 10 A ICC Operating current (VCC = Max, IOUT = 0 mA) outputs disabled Commercial 190 285 – 275 mA Industrial 215 305 Standby current (Both ports TTL level) Commercial 50 70 Industrial 65 95 Commercial 120 180 Industrial 135 205 Commercial 0.05 0.5 Industrial 0.05 0.5 Commercial 110 160 Industrial 125 175 ISB1 – 180 – 45 mA 65 – mA mA CEL & CER VIH, f = fMAX ISB2 Standby current (One port TTL level) 110 160 – mA mA CEL | CER VIH, f = fMAX ISB3 Standby current (Both port CMOS level) 0.05 0.5 – mA mA CEL & CER VCC –0.2 V, f = 0 ISB4 Standby current (One port CMOS level) CEL | CER VIH, f = 100 140 – mA mA fMAX[6] Notes 4. The voltage on any input or I/O pin cannot exceed the power pin during power up. 5. Pulse width < 20 ns. 6. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document Number: 38-06046 Rev. *J Page 9 of 24 CY7C026A Capacitance Parameter [7] Description CIN Input capacitance COUT Output capacitance Test Conditions Max TA = 25 °C, f = 1 MHz, VCC = 5.0 V Unit 10 pF 10 pF AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 5V 5V R1 = 893 OUTPUT RTH = 250 OUTPUT R1 = 893 OUTPUT C = 30 pF C = 30 pF R2 = 347 C = 5 pF R2 = 347 VTH = 1.4 V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 10% GND 90% 10% 90% 3 ns 3 ns 1 . 00 0. 90 (ns) for all -12 access times 0. 80 0. 70 0. 60 0. 50 0. 40 0. 30 0. 20 0. 1 0 0. 00 10 15 20 25 30 35 Capacitance (pF) Load Derating Curve Note 7. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-06046 Rev. *J Page 10 of 24 CY7C026A Data Retention Mode The CY7C026A is designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2 V. 2. CE must be kept between VCC – 0.2 V and 70% of VCC during the power up and power down transitions. 3. The RAM can begin operation > tRC after VCC reaches the minimum operating voltage (4.5 V). Timing Data Retention Mode VCC CE Parameter ICCDR1 4.5 V VCC 2.0 V 4.5 V VCC to VCC – 0.2 V Test Conditions [8] At VCCDR = 2 V tRC V IH Max Unit 1.5 mA Note 8. CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested. Document Number: 38-06046 Rev. *J Page 11 of 24 CY7C026A Switching Characteristics Over the Operating Range CY7C026A Parameter [9] Description -15 -20 Unit Min Max Min Max Read Cycle tRC Read cycle time 15 – 20 – ns tAA Address to data valid – 15 – 20 ns tOHA Output hold from address change 3 – 3 – ns tACE[10] CE LOW to data valid – 15 – 20 ns tDOE OE LOW to data valid – 10 – 12 ns OE LOW to Low Z 3 – 3 – ns OE HIGH to High Z – 10 – 12 ns CE LOW to Low Z 3 – 3 – ns CE HIGH to High Z – 10 – 12 ns CE LOW to Power-up 0 – 0 – ns CE HIGH to Power-down – 15 – 20 ns Byte enable access time – 15 – 20 ns tWC Write cycle time 15 – 20 – ns tSCE[10] CE LOW to write end 12 – 15 – ns tAW Address valid to write end 12 – 15 – ns tHA Address hold From write end 0 – 0 – ns tSA[10] Address setup to write start 0 – 0 – ns tPWE Write pulse width 12 – 15 – ns tSD Data setup to write end 10 – 15 – ns tHD[14] tHZWE[12, 13] tLZWE[12, 13] tWDD[15] tDDD[15] Data hold from write end 0 – 0 – ns R/W LOW to High Z – 10 – 12 ns R/W HIGH to Low Z 3 – 3 – ns Write pulse to data delay – 30 – 45 ns Write data valid to read data valid – 25 – 30 ns tLZOE [11, 12, 13] tHZOE[11, 12, 13] tLZCE[11, 12, 13] tHZCE[11, 12, 13] tPU[13] tPD[13] tABE[10] Write Cycle Notes 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH and 30 pF load capacitance. 10. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 11. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 12. Test conditions used are Load 2. 13. This parameter is guaranteed but not tested. 14. For 15 ns industrial parts tHD minimum is 0.5 ns. 15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 10 on page 17. Document Number: 38-06046 Rev. *J Page 12 of 24 CY7C026A Switching Characteristics (continued) Over the Operating Range CY7C026A Parameter [9] Description -15 -20 Unit Min Max Min Max Busy Timing[16] tBLA BUSY LOW from address match – 15 – 20 ns tBHA BUSY HIGH from address mismatch – 15 – 20 ns tBLC BUSY LOW from CE LOW – 15 20 ns tBHC BUSY HIGH from CE HIGH – 15 – 17 ns tPS Port setup for priority 5 – 5 – ns tWB R/W HIGH after BUSY (Slave) 0 – 0 – ns tWH R/W HIGH after BUSY HIGH (Slave) 13 – 15 – ns tBDD[17] BUSY HIGH to data valid – 15 – 20 ns Interrupt Timing[16] tINS INT set time – 15 – 20 ns tINR INT reset time – 15 – 20 ns Semaphore Timing tSOP SEM flag update pulse (OE or SEM) 10 – 10 – ns tSWRD SEM flag write to read time 5 – 5 – ns tSPS SEM flag contention window 5 – 5 – ns tSAA SEM address access time – 15 – 20 ns Notes 16. Test conditions used are Load 2. 17. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). Document Number: 38-06046 Rev. *J Page 13 of 24 CY7C026A Switching Waveforms Figure 3. Read Cycle No. 1 (Either Port Address Access) [18, 19, 20] tRC ADDRESS tOHA DATAOUT tAA tOHA PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (Either Port CE/OE Access) [18, 21, 22] tACE CE and LB or UB tHZCE tDOE OE tHZOE tLZOE DATA VALID DATAOUT tLZCE tPU tPD ICC CURRENT ISB Figure 5. Read Cycle No. 3 (Either Port) [18, 20, 21, 22] tRC ADDRESS tAA tOHA UB or LB tHZCE tLZCE tABE CE tHZCE tACE tLZCE DATAOUT Notes 18. R/W is HIGH for read cycles. 19. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 20. OE = VIL. 21. Address valid prior to or coincident with CE transition LOW. 22. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Document Number: 38-06046 Rev. *J Page 14 of 24 CY7C026A Switching Waveforms (continued) Figure 6. Write Cycle No. 1: R/W Controlled Timing [23, 24, 25, 26] tWC ADDRESS tHZOE [27] OE tAW CE [28, 29] tPWE[26] tSA tHA R/W tHZWE[27] DATAOUT tLZWE NOTE 30 NOTE 30 tSD tHD DATAIN Figure 7. Write Cycle No. 2: CE Controlled Timing [23, 24, 25, 31] tWC ADDRESS tAW CE [28, 29] tSA tSCE tHA R/W tSD tHD DATAIN Notes 23. R/W must be HIGH during all address transitions. 24. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 25. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 26. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 27. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested. 28. To access RAM, CE = VIL, SEM = VIH. 29. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 30. During this period, the I/O pins are in the output state, and input signals must not be applied. 31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document Number: 38-06046 Rev. *J Page 15 of 24 CY7C026A Switching Waveforms (continued) Figure 8. Semaphore Read After Write Timing, Either Side [32] tOHA tSAA A0–A2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tSCE tSOP tSD I/O0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Figure 9. Timing Diagram of Semaphore Contention [33, 34, 35] A0L–A2L ADDRESS MATCH R/WL SEML tSPS A0R–A2R ADDRESS MATCH R/WR SEMR Notes 32. CE = HIGH for the duration of the above timing (both write and read cycle). 33. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 34. Semaphores are reset (available to both ports) at cycle start. 35. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable. Document Number: 38-06046 Rev. *J Page 16 of 24 CY7C026A Switching Waveforms (continued) Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH) [36] tWC ADDRESSR ADDRESS MATCH tPWE R/WR tSD DATAINR tHD VALID tPS ADDRESSL ADDRESS MATCH tBLA tBHA BUSYL tBDD tDDD DATAOUTL VALID tWDD Figure 11. Write Timing with Busy Input (M/S = LOW) tPWE R/W BUSY tWB tWH Note 36. CEL = CER = LOW. Document Number: 38-06046 Rev. *J Page 17 of 24 CY7C026A Switching Waveforms (continued) Figure 12. Busy Timing Diagram No. 1 (CE Arbitration) [37] CEL Valid First: ADDRESSL,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESSL,R ADDRESS MATCH CER tPS CEL tBLC tBHC BUSYL Figure 13. Busy Timing Diagram No. 2 (Address Arbitration) [37] Left Address Valid First: tRC or tWC ADDRESSL ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSYR Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSYL Note 37. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted. Document Number: 38-06046 Rev. *J Page 18 of 24 CY7C026A Switching Waveforms (continued) Figure 14. Interrupt Timing Diagrams Left Side Sets INTR: tWC ADDRESSL WRITE 3FFF tHA[38] CEL R/WL INTR tINS [39] Right Side Clears INTR: tRC ADDRESSR READ 3FFF CER tINR [39] R/WR OER INTR Right Side Sets INTL: tWC ADDRESSR WRITE 3FFE tHA[38] CER R/WR INTL [39] tINS Left Side Clears INTL: tRC READ 3FFE ADDRESSR CEL tINR[39] R/WL OEL INTL Notes 38. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 39. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document Number: 38-06046 Rev. *J Page 19 of 24 CY7C026A Ordering Information 16 K × 16 Asynchronous Dual-Port SRAM Speed (ns) Package Name Ordering Code Package Type Operating Range 15 CY7C026A-15AXI A100 100-pin TQFP (Pb-free) Industrial 20 CY7C026A-20AXC A100 100-pin TQFP (Pb-free) Commercial Ordering Code Definitions CY 7 C 026A - XX A X X Temperature Range: X = I or C I = Industrial; C = Commercial Pb-free Package Type: A = 100-pin TQFP Speed: XX = 15 ns or 20 ns Part Number Identifier Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-06046 Rev. *J Page 20 of 24 CY7C026A Package Diagram Figure 15. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048 51-85048 *J Document Number: 38-06046 Rev. *J Page 21 of 24 CY7C026A Acronyms Acronym Document Conventions Description CMOS Complementary Metal Oxide Semiconductor I/O Input/Output SRAM Static Random Access Memory TQFP Thin Quad Flat Pack Document Number: 38-06046 Rev. *J Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µA microampere mA milliampere mV millivolt ns nanosecond ohm pF picofarad V volt W watt Page 22 of 24 CY7C026A Document History Page Document Title: CY7C026A, 16 K × 16 Dual-Port Static RAM Document Number: 38-06046 Rev. ECN No. Orig. of Change Submission Date ** 110198 SZV 09/29/01 Change from Spec number: 38-00832 to 38-06046 *A 122296 RBI 12/27/02 Updated Maximum Ratings: Added Note 4 and referred the same note in maximum ratings. *B 237621 YDT See ECN Updated Features: Removed cross information. *C 393454 YIM See ECN Added Pb-free Logo. Updated Ordering Information: Added Pb-free parts namely CY7C026A-15AXC, CY7C026A-20AXC. *D 2623540 VKN / PYRS 12/17/08 Added CY7C026B part related information in all instances across the document. Updated Ordering Information: Added MPN CY7C026A-15AXI. *E 2896038 RAME 03/19/10 Updated Ordering Information: Removed inactive parts. Updated Package Diagram. *F 3081925 ADMU 11/10/2010 Changed title from “CY7C026A/026B, CY7C036A 16K X 16/18 Dual-Port Static RAM” to “CY7C026A, 16 K X 16 Dual-Port Static RAM”. Removed CY7C026B and CY7C036A part related information in all instances across the document. Removed 12 ns speed bin related information in all instances across the document. Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated to new template. *G 3403652 ADMU 10/14/2011 Updated Ordering Information: Removed pruned MPN CY7C026A-20AC. Updated Package Diagram. *H 3799343 SMCH 10/31/2012 Updated Logic Block Diagram (No change in diagram, removed the notes “I/O8–I/O15 for × 16 devices.” and “I/O0–I/O7 for × 16 devices.” and their references in Logic Block Diagram). Updated Functional Overview (Updated Write Operation (Updated Table 1 (Replaced “X” with “H” for CE inputs of “Read data in semaphore flag” and “Write DIN0 into semaphore flag” operations))). Updated Switching Characteristics (Updated Note 10 (Removed “UB = L”)). Updated Switching Waveforms (Updated Note 22 (Removed “UB or LB = VIL”), updated Figure 9 (Replaced “MATCH” with “ADDRESS MATCH”), updated Figure 10 (Replaced “MATCH” with “ADDRESS MATCH”)). Updated Package Diagram (spec 51-85048 (Changed revision from *E to *G)). *I 4580622 SMCH 11/26/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Package Diagram: spec 51-85048 – Changed revision from *G to *I. *J 5018928 NILE 11/18/2015 Updated Package Diagram: spec 51-85048 – Changed revision from *I to *J. Updated to new template. Completing Sunset Review. Document Number: 38-06046 Rev. *J Description of Change Page 23 of 24 CY7C026A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06046 Rev. *J Revised November 18, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 24 of 24