CY7C009V:3.3 V 128 K × 8 Dual-Port Static RAM

CY7C008V CY7C018V CY7C009V CY7C019V 3.3 V 128 K × 8
Dual-Port Static RAM
CY7C009V
3.3 V 128 K × 8
Dual-Port Static RAM
3.3 V 128 K × 8 Dual-Port Static RAM
Features
■
True dual-ported memory cells which allow simultaneous
access of the same memory location
■
128 K × 8 organization (CY7C009)
■
0.35-micron CMOS for optimum speed/power
■
High-speed access: 15/20/25 ns
■
Low operating power
❐ Active: ICC = 115 mA (typical)
❐ Standby: ISB3 = 10 A (typical)
■
Expandable data bus to 16 bits or more using Master/Slave
chip select when using more than one device
■
On-chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Dual chip enables
■
Pin select for Master or Slave
■
Commercial and industrial temperature ranges
■
Fully asynchronous operation
■
Available in 100-pin TQFP
■
Automatic power-down
■
Pb-free packages available
For a complete list of related documentation, click here.
Logic Block Diagram
R/WL
R/WR
CE0L
CE1L
CEL
CE0R
CE1R
CER
OEL
OER
8
8
I/O0L–I/O8L
I/O
Control
17
A0L–A16L
Address
Decode
Address
Decode
True Dual-Ported
RAM Array
17
17
A0R–A16R
17
A0L–A16L
CEL
OEL
R/WL
SEML
BUSYL
INTL
I/O0R–I/O8R
I/O
Control
A0R–A16R
CER
OER
R/WR
SEMR
Interrupt
Semaphore
Arbitration
[1]
[1]
BUSYR
INTR
M/S
Note
1. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document Number: 38-06044 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 26, 2014
CY7C009V
Functional Description
The CY7C009V is a low-power CMOS 64 K, 128 K × 8 dual-port
static RAM. Various arbitration schemes are included on the
devices to handle situations when multiple processors access
the same piece of data. Two ports are provided permitting
independent, asynchronous access for reads and writes to any
location in memory. The devices can be utilized as standalone
8/9-bit dual-port static RAMs or multiple devices can be
combined in order to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete
logic.
Application
areas
include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Document Number: 38-06044 Rev. *H
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a chip select (CE) pin.
The CY7C009V is available in 100-pin Thin Quad Plastic
Flatpacks (TQFP).
Page 2 of 23
CY7C009V
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Architecture ...................................................................... 5
Functional Overview ........................................................ 5
Write Operation ........................................................... 5
Read Operation ........................................................... 5
Interrupts ..................................................................... 5
Busy ............................................................................ 5
Master/Slave ............................................................... 5
Semaphore Operation ................................................. 6
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
Electrical Characteristics ................................................. 8
Capacitance ...................................................................... 9
AC Test Loads and Waveforms ....................................... 9
Data Retention Mode ........................................................ 9
Document Number: 38-06044 Rev. *H
Timing ................................................................................ 9
Switching Characteristics .............................................. 10
Switching Waveforms .................................................... 12
Ordering Information ...................................................... 18
128 K × 8, 3.3 V Asynchronous Dual-Port SRAM ..... 18
Ordering Code Definitions ......................................... 18
Package Diagram ............................................................ 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Page 3 of 23
CY7C009V
Selection Guide
CY7C009V
–15
Description
CY7C009V
–20
CY7C009V
–25
Unit
Maximum access time
15
20
25
ns
Typical operating current
125
120
115
mA
Typical standby current for ISB1
(both ports TTL level)
35
35
30
mA
Typical standby current for ISB3
(both ports CMOS level)
10
10
10
A
Pin Configurations
NC
NC
A6R
A5R
A4R
A3R
A2R
A1R
INTR
A0R
BUSYR
M/S
GND
BUSYL
INTL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
NC
NC
Figure 1. 100-pin TQFP pinout (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
1
75
NC
NC
2
74
NC
A7L
3
73
A7R
A8L
4
72
A8R
A9L
5
71
A9R
A10L
6
70
A10R
A11L
7
69
A11R
A12L
8
68
A12R
A13L
9
67
A13R
A14L
10
66
A14R
65
A15R
64
A16R
63
GND
A15L
11
A16L
12
VCC
13
NC
14
62
NC
NC
15
61
NC
NC
16
60
NC
NC
17
59
NC
CY7C009V (128 K × 8)
CE0L
18
58
CE0R
CE1L
19
57
CE1R
SEML
20
56
SEMR
R/WL
21
55
R/WR
OEL
22
54
OER
GND
23
53
GND
NC
24
52
GND
NC
25
51
NC
Document Number: 38-06044 Rev. *H
NC
NC
NC
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
VCC
I/O2R
I/01R
I/O0R
GND
VCC
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 4 of 23
CY7C009V
Pin Definitions
Left Port
Right Port
Description
CE0L, CE1L
CE0R, CE1R
Chip enable (CE is LOW when CE0VIL and CE1  VIH)
R/WL
R/WR
Read/Write enable
OEL
OER
Output enable
A0L–A16L
A0R–A16R
Address
I/O0L–I/O7L
I/O0R–I/O7R
Data bus input/output
SEML
SEMR
Semaphore enable
INTL
INTR
Interrupt flag
BUSYL
BUSYR
Busy flag
M/S
Master or slave select
VCC
Power
GND
Ground
NC
No Connect
Architecture
The CY7C009V consists of an array of 128 K words of 8 bits each
of dual-port RAM cells, I/O and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access
for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized
for port-to-port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin,
the devices can function as a master (BUSY pins are outputs) or
as a slave (BUSY pins are inputs). The devices also have an
automatic power-down feature controlled by CE. Each port is
provided with its own output enable control (OE), which allows
data to be read from the device.
Functional Overview
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summarized
in Table 1 on page 6.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Document Number: 38-06044 Rev. *H
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (1FFFF for the CY7C009)
is the mailbox for the right port and the second-highest memory
location (1FFFE for the CY7C009) is the mailbox for the left port.
When one port writes to the other port’s mailbox, an interrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2 on page 6.
Busy
The CY7C009V provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of
each other, the busy logic will determine which port has access.
If tPS is violated, one port will definitely gain permission to the
location, but it is not predictable which port will get that
permission. BUSY will be asserted tBLA after an address match
or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This will allow the device to interface to a master device with no
external components. Writing to slave devices must be delayed
until after the BUSY input has settled (tBLC or tBLA), otherwise,
Page 5 of 23
CY7C009V
the slave chip may begin a write cycle during a contention
situation. When tied HIGH, the M/S pin allows the device to be
used as a master and, therefore, the BUSY line is an output.
BUSY can then be used to send the arbitration outcome to a
slave.
Semaphore Operation
The CY7C009V provide eight semaphore latches, which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore.
The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left
side no longer requires the semaphore, a one is written to cancel
its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore will be set to
one for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Table 3 on page 7 shows sample semaphore
operations.
When reading a semaphore, all data lines output the semaphore
value. The read value is latched in an output register to prevent
the semaphore from changing state during a write from the other
port. If both ports attempt to access the semaphore within tSPS
of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
Table 1. Non-Contending Read/Write
Inputs
Outputs
Operation
CE
R/W
OE
SEM
H
X
X
H
High Z
Deselected: Power-down
H
H
L
L
Data out
Read data in semaphore flag
X
X
H
X
High Z
I/O lines disabled
X
L
Data in
Write into semaphore flag
H
L
H
Data out
Read
L
L
X
H
Data in
L
X
X
L
H
L
I/O0–I/O8
Write
Not allowed
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)
Function
Left Port
Right Port
R/WL
CEL
OEL
A0L–16L
INTL
R/WR
CER
OER
A0R–16R
INTR
Set Right INTR Flag
L
L
X
1FFFF
X
X
X
X
X
L[2]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
1FFFF
H[3]
Set Left INTL Flag
X
X
X
X
L[3]
L
L
X
1FFFE
X
Reset Left INTL Flag
X
L
L
1FFFE
H[2]
X
X
X
X
X
Notes
2. If BUSYL = L, then no change.
3. If BUSYR = L, then no change.
Document Number: 38-06044 Rev. *H
Page 6 of 23
CY7C009V
Table 3. Semaphore Operation Example
Function
I/O0–I/O8 Left
I/O0–I/O8Right
Status
No action
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Document Number: 38-06044 Rev. *H
Page 7 of 23
CY7C009V
Maximum Ratings
DC input voltage ................................. –0.5 V to VCC + 0.5 V
Exceeding maximum ratings [4] may shorten the useful life of the
device. User guidelines are not tested.
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage ......................................... > 1100 V
Storage temperature ................................ –65 °C to +150 °C
Latch-up current ................................................... > 200 mA
Ambient temperature with
power applied .......................................... –55 C to +125 C
Operating Range
Supply voltage to ground potential ..............–0.5 V to +4.6 V
Range
DC voltage applied to
outputs in high Z State ........................ –0.5 V to VCC + 0.5 V
Commercial
Industrial
[5]
Ambient Temperature
VCC
0 °C to +70 °C
3.3 V ± 300 mV
–40 °C to +85 °C
3.3 V ± 300 mV
Electrical Characteristics
Over the Operating Range
CY7C009V
Parameter
Description
Min
-15
-20
-25
Typ Max Min
Typ Max Min
Typ Max
VOH
Output HIGH voltage (VCC = Min, IOH = –4.0 mA)
2.4
–
2.4
–
2.4
–
V
VOL
Output LOW voltage (VCC = Min, IOH = +4.0 mA)
–
0.4
–
0.4
–
0.4
V
VIH
Input HIGH voltage
2.2
–
2.2
–
2.2
–
V
VIL
Input LOW voltage
–
0.8
–
0.8
–
0.8
V
IIX
Input leakage current
–5
5
–5
5
–5
5
A
IOZ
Output leakage current
–10
10
–10
10
–10
10
A
ICC
Operating current
(VCC = Max, IOUT = 0 mA)
outputs disabled
Commercial
185
–
120
175
–
165
mA
140
195
Standby current
(both ports TTL level)
CEL and CER  VIH, f = fMAX
Commercial
35
45
45
55
Standby current
(one port TTL level)
CEL | CER  VIH, f = fMAX
Commercial
ISB1
ISB2
ISB3
ISB4
–
–
125
Industrial
–
35
Industrial
–
80
Industrial
10
Standby current
(one port CMOS level)
CEL | CER  VIH, f = fMAX[6]
75
Industrial
120
–
Commercial
Standby current
(both ports CMOS level)
Industrial
CEL and CER  VCC 0.2 V, f = 0
Commercial
50
250
–
105
–
–
Unit
75
110
85
120
10
250
10
250
70
95
80
105
–
115
–
30
mA
40
–
65
mA
95
–
10
A
A
–
80
–
mA
mA
250
60
mA
mA
mA
Notes
4. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. Industrial parts are available in CY7C009V.
6. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
ISB3.
Document Number: 38-06044 Rev. *H
Page 8 of 23
CY7C009V
Capacitance
Parameter [7]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 3.3 V
Max
Unit
10
pF
10
pF
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V
3.3 V
R1 = 590 
C = 30 pF
RTH = 250 
OUTPUT
OUTPUT
R1 = 590 
OUTPUT
C = 30 pF
R2 = 435 
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0 V
GND
10%
90%
10%
90%
 3 ns
 3 ns
Data Retention Mode
The CY7C009V is designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power-up and power-down transitions.
3. The RAM can begin operation > tRC after VCC reaches the
minimum operating voltage (3.0 V).
R2 = 435 
C = 5 pF
VTH = 1.4 V
Timing
Data Retention Mode
VCC
CE
Parameter
ICCDR1
3.0 V
VCC 2.0 V
3.0 V
VCC to VCC – 0.2 V
Test Conditions [8]
@ VCCDR = 2 V
tRC
V
IH
Max
Unit
50
A
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested.
Document Number: 38-06044 Rev. *H
Page 9 of 23
CY7C009V
Switching Characteristics
Over the Operating Range
CY7C009V
Parameter
[9]
Description
-15
-20
-25
Unit
Min
Max
Min
Max
Min
Max
READ CYCLE
tRC
Read cycle time
15
–
20
–
25
–
ns
tAA
Address to data valid
–
15
–
20
–
25
ns
tOHA
Output hold from address change
3
–
3
–
3
–
ns
tACE[10]
CE LOW to data valid
–
15
–
20
–
25
ns
tDOE
OE LOW to data valid
–
10
–
12
–
13
ns
OE LOW to low Z
3
–
3
–
3
–
ns
OE HIGH to high Z
–
10
–
12
–
15
ns
CE LOW to low Z
3
–
3
–
3
–
ns
CE HIGH to high Z
–
10
–
12
–
15
ns
CE LOW to power-up
0
–
0
–
0
–
ns
CE HIGH to power-down
–
15
–
20
–
25
ns
Byte enable access time
–
15
–
20
–
25
ns
15
–
20
–
25
–
ns
tLZOE
[11, 12, 13]
tHZOE[11, 12, 13]
tLZCE[11, 12, 13]
tHZCE[11, 12, 13]
tPU[13]
tPD[13]
tABE[10]
WRITE CYCLE
tWC
Write cycle time
tSCE[10]
CE LOW to write end
12
–
16
–
20
–
ns
tAW
Address valid to write end
12
–
16
–
20
–
ns
tHA
Address hold from write end
0
–
0
–
0
–
ns
tSA[10]
Address set-up to write start
0
–
0
–
0
–
ns
tPWE
Write pulse width
12
–
17
–
22
–
ns
tSD
Data set-up to write end
10
–
12
–
15
–
ns
tHD
Data hold from write end
0
–
0
–
0
–
ns
tHZWE[12, 13]
tLZWE[12, 13]
tWDD[14]
tDDD[14]
R/W LOW to high Z
–
10
–
12
–
15
ns
R/W HIGH to low Z
3
–
3
–
3
–
ns
Write pulse to data delay
–
30
–
40
–
50
ns
Write data valid to read data valid
–
25
–
30
–
35
ns
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
10. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
11. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
12. Test conditions used are Load 2.
13. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading port, refer
to Read Timing with Busy waveform.
14. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Document Number: 38-06044 Rev. *H
Page 10 of 23
CY7C009V
Switching Characteristics (continued)
Over the Operating Range
CY7C009V
Parameter
[9]
Description
-15
-20
-25
Unit
Min
Max
Min
Max
Min
Max
–
15
–
20
–
20
BUSY TIMING [15]
tBLA
BUSY LOW from address match
tBHA
BUSY HIGH from address mismatch
–
15
–
20
–
20
ns
tBLC
BUSY LOW from CE LOW
–
15
–
20
–
20
ns
tBHC
BUSY HIGH from CE HIGH
–
15
–
16
–
17
ns
tPS
Port set-up for priority
5
–
5
–
5
–
ns
tWB
R/W HIGH after BUSY (Slave)
0
–
0
–
0
–
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
13
–
15
–
17
–
ns
tBDD[16]
BUSY HIGH to data valid
–
15
–
20
–
25
ns
INTERRUPT TIMING
ns
[15]
tINS
INT set time
–
15
–
20
–
20
ns
tINR
INT reset time
–
15
–
20
–
20
ns
10
–
10
–
12
–
ns
SEMAPHORE TIMING
tSOP
SEM flag update pulse (OE or SEM)
tSWRD
SEM flag write to read time
5
–
5
–
5
–
ns
tSPS
SEM flag contention window
5
–
5
–
5
–
ns
tSAA
SEM address access time
–
15
–
20
–
25
ns
Notes
15. Test conditions used are Load 1.
16. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Document Number: 38-06044 Rev. *H
Page 11 of 23
CY7C009V
Switching Waveforms
Figure 3. Read Cycle No.1 (Either Port Address Access) [17, 18, 19]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No.2 (Either Port CE/OE Access) [17, 20, 21]
tACE
CE
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Figure 5. Read Cycle No. 3 (Either Port) [17, 19, 20, 21]
tRC
ADDRESS
tAA
tOHA
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes
17. R/W is HIGH for read cycles.
18. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
19. OE = VIL.
20. Address valid prior to or coincident with CE transition LOW.
21. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document Number: 38-06044 Rev. *H
Page 12 of 23
CY7C009V
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1: R/W Controlled Timing [22, 23, 24, 25]
tWC
ADDRESS
tHZOE [26]
OE
tAW
CE
[27]
tPWE[25]
tSA
tHA
R/W
tHZWE[26]
DATA OUT
tLZWE
NOTE 28
NOTE 28
tSD
tHD
DATA IN
Figure 7. Write Cycle No. 2: CE Controlled Timing [22, 23, 24, 29]
tWC
ADDRESS
tAW
CE
[27]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes
22. R/W must be HIGH during all address transitions.
23. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
24. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
25. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tPWE.
26. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
27. To access RAM, CE = VIL, SEM = VIH.
28. During this period, the I/O pins are in the output state, and input signals must not be applied.
29. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document Number: 38-06044 Rev. *H
Page 13 of 23
CY7C009V
Switching Waveforms (continued)
Figure 8. Semaphore Read After Write Timing, Either Side [30]
tOHA
tSAA
A0–A2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tSCE
tSOP
tSD
I/O 0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Figure 9. Timing Diagram of Semaphore Contention [31, 32, 33]
A0L–A2L
MATCH
R/WL
SEML
tSPS
A0R–A2R
MATCH
R/WR
SEMR
Notes
30. CE = HIGH for the duration of the above timing (both write and read cycle).
31. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
32. Semaphores are reset (available to both ports) at cycle start.
33. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document Number: 38-06044 Rev. *H
Page 14 of 23
CY7C009V
Switching Waveforms (continued)
Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH) [34]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATAOUTL
VALID
tWDD
Figure 11. Write Timing with Busy Input (M/S = LOW)
tPWE
R/W
BUSY
tWB
tWH
Note
34. CEL = CER = LOW.
Document Number: 38-06044 Rev. *H
Page 15 of 23
CY7C009V
Switching Waveforms (continued)
Figure 12. Busy Timing Diagram No. 1 (CE Arbitration) [35]
CEL Valid First:
ADDRESSL,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESSL,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
Figure 13. Busy Timing Diagram No. 2 (Address Arbitration) [35]
Left Address Valid First:
tRC or tWC
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSYR
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSYL
Note
35. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document Number: 38-06044 Rev. *H
Page 16 of 23
CY7C009V
Switching Waveforms (continued)
Figure 14. Interrupt Timing Diagrams
Left Side Sets INTR:
ADDRESSL
tWC
WRITE 1FFFF
tHA[36]
CEL
R/WL
INTR
tINS [37]
Right Side Clears INTR:
tRC
READ 1FFFF
ADDRESSR
CER
tINR [37]
R/WR
OER
INTR
Right Side Sets INTL:
tWC
ADDRESSR
WRITE 1FFFE
tHA[36]
CER
R/WR
INTL
[37]
tINS
Left Side Clears INTL:
tRC
READ 1FFFE
ADDRESSR
CEL
tINR[37]
R/WL
OEL
INTL
Notes
36. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
37. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document Number: 38-06044 Rev. *H
Page 17 of 23
CY7C009V
Ordering Information
128 K × 8, 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Name
Ordering Code
Package Type
Operating
Range
15
CY7C009V-15AXC
A100
100-pin TQFP Pb-free
Commercial
20
CY7C009V-20AXI
A100
100-pin TQFP Pb-free
Industrial
25
CY7C009V-25AXC
A100
100-pin TQFP Pb-free
Commercial
Ordering Code Definitions
CY 7
C 00 9
V - XX A
X
X
Operating Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package: A = 100-pin TQFP
Speed Bin: XX = 15 or 20 or 25
3.3 V part
64 K / 128 K Dual Port Family
00 = × 8
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-06044 Rev. *H
Page 18 of 23
CY7C009V
Package Diagram
Figure 15. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048
51-85048 *I
Document Number: 38-06044 Rev. *H
Page 19 of 23
CY7C009V
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
CE
Chip Enable
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
INT
Interrupt
µA
microampere
OE
Output Enable
mA
milliampere
SEM
Semaphore
ms
millisecond
SRAM
Static Random Access Memory
mV
millivolt
TQFP
Thin Quad Flat Pack
ns
nanosecond
TTL
Transistor-Transistor Logic
pF
picofarad
V
volt
W
watt
Document Number: 38-06044 Rev. *H
Symbol
Unit of Measure
Page 20 of 23
CY7C009V
Document History Page
Document Title: CY7C009V, 3.3 V 128 K × 8 Dual-Port Static RAM
Document Number: 38-06044
Rev.
ECN No.
Issue Date
Orig. of
Change
**
110192
09/29/01
SZV
Change from Spec number: 38-00669 to 38-06044
*A
113541
04/15/02
OOR
Updated Pin Configurations (Changed pin 85 from BUSYL to BUSYR in the
figure “100-pin TQFP (Top View)” (corresponding to CY7C018V/019V)).
Description of Change
*B
122294
12/27/02
RBI
Updated Maximum Ratings (Added Power up requirements).
*C
393440
See ECN
YIM
Added Pb-free Logo
Updated Ordering Information (Added Pb-free parts (CY7C008V-25AXC,
CY7C009V-15AXC, CY7C009V-20AXI, CY7C009V-25AXC,
CY7C019V-15AXC, CY7C019V-20AXC, CY7C019V-20AXI,
CY7C019V-25AXC)).
*D
2896038
03/19/10
RAME
Updated Ordering Information (Removed inactive parts).
Updated Package Diagram.
*E
3081242
11/09/2010
ADMU
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*F
3816114
11/19/2012
SMCH
Updated Document Title to read “CY7C009V, 3.3 V 128 K × 8 Dual-Port Static
RAM”.
Updated Features (Removed CY7C008V, CY7C018V, CY7C019V related
information).
Updated Logic Block Diagram (Removed CY7C008V, CY7C018V, CY7C019V
related information, removed Notes “I/O0–I/O7 for × 8 devices; I/O0–I/O8 for ×
9 devices.” and “A0–A15 for 64 K devices; A0–A16 for 128 K.” and their
references in Logic Block DIagram).
Updated Functional Description (Removed CY7C008V, CY7C018V,
CY7C019V related information).
Updated Selection Guide (Removed CY7C008V, CY7C018V, CY7C019V
related information).
Updated Pin Configurations (Updated Figure 1 (Removed CY7C008V related
information, removed the Note “This pin is NC for CY7C008V.” and its reference
in the same figure), removed the figure “100-pin TQFP (Top View)”, removed
the Note “This pin is NC for CY7C018V.”).
Updated Pin Definitions (Removed CY7C008V, CY7C018V, CY7C019V
related information).
Updated Architecture (Removed CY7C008V, CY7C018V, CY7C019V related
information).
Updated Functional Overview (Updated Interrupts (Removed CY7C008V,
CY7C018V, CY7C019V related information), updated Busy (Removed
CY7C008V, CY7C018V, CY7C019V related information), updated Semaphore
Operation (Removed CY7C008V, CY7C018V, CY7C019V related information),
updated Table 2 (Removed CY7C008V, CY7C018V, CY7C019V related
information), removed the Note “A0L–16L and A0R–16R, 1FFFF/1FFFE for the
CY7C009V/19V.” and its reference in the same table)).
Updated Operating Range (Updated Note 5 (Removed CY7C019V related
information)).
Updated Electrical Characteristics (Removed CY7C008V, CY7C018V,
CY7C019V related information, removed the Note “Industrial parts are available
in CY7C009V and CY7C019V only.” and its reference in Electrical
Characteristics).
Updated Data Retention Mode (Removed CY7C008V, CY7C018V, CY7C019V
related information).
Updated Switching Characteristics (Removed CY7C008V, CY7C018V,
CY7C019V related information, updated Note 10 (Removed UB = L)).
Document Number: 38-06044 Rev. *H
Page 21 of 23
CY7C009V
Document History Page (continued)
Document Title: CY7C009V, 3.3 V 128 K × 8 Dual-Port Static RAM
Document Number: 38-06044
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
*F (cont.)
3816114
11/19/2012
SMCH
Updated Switching Waveforms (Updated Figure 14 (Removed CY7C019V
related information)).
Updated Package Diagram (spec 51-85048 (Changed revision from *D to *G)).
*G
4194765
11/18/2013
SMCH
Updated Pin Definitions:
Replaced “CER, CE1R” with “CE0R, CE1R” in “Right Port” column.
Updated Switching Waveforms:
Updated Figure 14.
Updated Package Diagram:
spec 51-85048 – Changed revision from *G to *H.
Updated in new template.
Completing Sunset Review.
*H
4580622
11/26/2014
SMCH
Added related documentation hyperlink in page 1.
Updated Figure 15 in Package Diagram (spec 51-85048 *H to *I).
Document Number: 38-06044 Rev. *H
Page 22 of 23
CY7C009V
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06044 Rev. *H
Revised November 26, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 23 of 23