INTEGRATED CIRCUITS 74LVC373A Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) Product specification 1998 Jul 29 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC373A The 74LVC373A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Supply voltage range of 2.7V to 3.6V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • Direct interface with TTL levels • High impedance when VCC = 0V The ’373’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one setup time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. DESCRIPTION The 74LVC373A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The ’373’ is functionally identical to the ’573’, but the ’573’ has a different pin arrangement. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. QUICK REFERENCE DATA SYMBOL tPHL/tPLH PARAMETER CONDITIONS Propagation delay Dn to Qn; LE to Qn CL = 50pF VCC = 3.3V CI Input capacitance CPD Power dissipation capacitance per latch TYPICAL 4.2 4.6 Notes 1 and 2 UNIT ns 5.0 pF 20 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVC373A D 74LVC373A D SOT163-1 20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVC373A DB 74LVC373A DB SOT339-1 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVC373A PW 7LVC373APW DH SOT360-1 PACKAGES 1998 Jul 29 2 853-1860 19802 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) PIN CONFIGURATION 74LVC373A LOGIC SYMBOL (IEEE/IEC) 1 VCC 11 EN OE 1 20 Q0 2 19 Q7 D0 3 18 D7 3 D1 4 17 D6 4 5 Q1 5 16 Q6 7 6 Q2 6 15 Q5 8 D2 7 14 D5 13 12 D3 8 13 D4 14 15 Q3 9 12 Q4 17 16 11 LE 18 19 GND 10 C1 1D 2 9 SA00383 SA00385 PIN DESCRIPTION FUNCTIONAL DIAGRAM PIN NUMBER SYMBOL 1 OE FUNCTION 3, 4, 7, 8, 13, 14, 17, 18 D0-D7 Data inputs 2, 5, 6, 9, 12, 15, 16, 19 Q0-Q7 Data outputs 11 LE 10 GND Ground (0V) 20 VCC Positive supply voltage Output enable input (active-Low) Latch enable input (active-High) 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 Q4 12 LATCH 1 to 8 3-State OUTPUTS 13 D4 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 11 LE 1 OE LOGIC SYMBOL 3 4 7 8 13 14 17 18 SA00387 D0 D1 D2 D3 D4 D5 D6 D7 11 LE 1 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 SA00384 1998 Jul 29 3 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC373A LOGIC DIAGRAM D0 D1 D D2 D Q LE LE D3 D Q D Q LE LE LE LE D4 D5 D Q D Q LE LE LE LE D6 D7 D Q D Q LE LE LE LE Q LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SA00386 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES H h L l X Z INTERNAL LATCHES OE LE Dn Enable and read register (transparent mode) L L H H L H L H L H Latch and read register L L L L l h L H H H Latch register and disable outputs H H L L l h L H Z Z = HIGH voltage level = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition = Don’t care = High impedance OFF-state 1998 Jul 29 4 Q0 to Q7 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC373A RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VI VO PARAMETER CONDITIONS UNIT MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 DC Input voltage range 0 5.5 DC Output voltage range; output HIGH or LOW state 0 VCC DC output voltage range; output 3-State 0 5.5 –40 +85 °C 0 0 20 10 ns/V V Tamb Operating ambient temperature range in free-air tr, tf Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V V V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC CONDITIONS UNIT –0.5 to +6.5 V IIK DC input diode current VI 0 –50 mA VI DC input voltage Note 2 –0.5 to +6.5 V IOK DC output diode current VO VCC or VO 0 50 mA DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5 DC output voltage; output 3-State Note 2 –0.5 to 6.5 DC output source or sink current VO = 0 to VCC VO IO IGND, ICC Tstg PTOT DC supply voltage RATING DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K V 50 mA 100 mA –65 to +150 °C 500 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jul 29 5 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC373A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 TYP1 V VCC = 1.2V GND V VCC = 2.7 to 3.6V HIGH level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC0.2 VCC = 3.0V; VI = VIH or VIL; IO = –18mA VCC0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC0.8 VCC VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage UNIT MAX VCC = 3.0V; VI = VIH or VIL; IO = 100µA V 0.40 GND VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.20 V 0.55 0 1 0.1 5 µA IOZ 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND 0.1 10 µA Ioff Power off leakage supply VCC = 0.0V; VI or VO = 5.5V 0.1 10 µA ICC Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA II ∆ICC Input leakage current2 VCC = 3 3.6V; 6V; VI = 5 5.5V 5V or GND NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state. 1998 Jul 29 6 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC373A AC CHARACTERISTICS GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER tPHL tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay LE to Qn 3-State output enable time OE to Qn 3-State output disable time OE to Qn tW LE pulse width HIGH Setup time Dn to LE Hold time Dn to LE tSU th VCC = 3.3V ±0.3V WAVEFORM VCC = 2.7V VCC = 1.2V UNIT MIN TYP1 MAX MIN MAX TYP 1, 5 1.5 4.2 6.8 1.5 7.8 19 ns 2, 5 1.5 4.6 7.2 1.5 8.2 21 ns 3, 5 1.5 4.8 7.7 1.5 8.7 22 ns 3, 5 1.5 4.3 6.1 1.5 7.1 15 ns 2 3.0 1.5 – 3.0 – – ns 4 2.0 0 – 2.0 – – ns 4 1.5 0.3 – 1.5 – – ns NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C. AC WAVEFORMS VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V VI nOE INPUT VM GND VI INPUT VM tPLZ tPZL VCC GND tPHL VOH Qn OUTPUT LOW-to-OFF OFF-to-LOW tPLH VM VX OUTPUT VOL VM tPHZ VOL SY00041 tPZH VOH Waveform 1. Input (Dn) to output (Qn) propagation delays. Qn OUTPUT HIGH-to-OFF OFF-to-HIGH VY VM GND outputs enabled VI outputs disabled outputs enabled VM LE INPUT SW00207 GND VOH Qn OUTPUT Waveform 3. 3-State enable and disable times. tw tPHL tPLH VM VOL SA00388 Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays 1998 Jul 29 7 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) AC WAVEFORMS 74LVC373A TEST CIRCUIT with 5-volt tolerant inputs/outputs VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V 2<VCC Open GND RL=500 Ω VIN ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ VOUT PULSE GENERATOR VI Dn INPUT S1 VCC VM D.U.T. RT RL=500 Ω CL GND th th tSU tSU Test Circuit for 3-State Outputs VI LE INPUT SWITCH POSITION VM GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SW00073 Waveform 4. Data setup and hold times for the Dn input to the LE input. (The shaded areas indicate when the input is permitted to change for predictable output performance). TEST SWITCH VCC VIN tPLH/tPHL Open tPLZ/tPZL 2<VCC t 2.7V 2.7 – 3.6V VCC 2.7V tPHZ/tPZH GND DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. SW00047 Waveform 5. Load circuitry for switching times. 1998 Jul 29 8 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1998 Jul 29 9 74LVC373A SOT163-1 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1998 Jul 29 10 74LVC373A SOT339-1 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1998 Jul 29 11 74LVC373A SOT360-1 Philips Semiconductors Product specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State) 74LVC373A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 08-98 9397-750-04506