INTEGRATED CIRCUITS 74LV573 Octal D-type transparent latch (3-State) Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 Jun 10 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) FEATURES 74LV573 DESCRIPTION • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0V to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, The 74LV573 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT573. The 74LV573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. Tamb = 25°C • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, The ‘573’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. Tamb = 25°C • Inputs and outputs on opposite sides of package allowing easy interface with microprocessors When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. • Useful as input or output port for microprocessors/microcomputer • Common 3-State output enable input • Output capability: bus driver • ICC category: MSI The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the ‘563’ has inverted outputs and the ‘373’ has a different pin arrangement. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf 2.5 ns SYMBOL PARAMETER CONDITIONS tPHL/tPLH Propagation delay Dn to Qn LE to Qn CI Input capacitance CPD Power dissipation capacitance per latch TYPICAL UNIT 12 13 ns 3.5 pF 26 pF CL = 15pF VCC = 3.3V Notes 1, 2 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING AND PACKAGE INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL –40°C to +125°C 74LV573 N 74LV573 N SOT146-1 20-Pin Plastic SO –40°C to +125°C 74LV573 D 74LV573 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +125°C 74LV573 DB 74LV573 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +125°C 74LV573 PW 74LV573PW DH SOT360-1 PACKAGES PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE Output enabled input (active LOW) 2, 3, 4, 5, 6, 7, 8, 9 D0–D7 Data inputs 19, 18, 17, 16, 15, 14, 13, 12 Q0–Q7 Data outputs 10 GND Ground (0V) 11 LE Latch enable input (active HIGH) 20 VCC Positive supply voltage 1998 Jun 10 2 853-1989 19545 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV573 FUNCTION TABLE LE Dn INTERNAL LATCHES OUTPUTS OE INPUTS Enable and read register (transparent mode) L L H H L H L H L H Latch and read register L L L L I h L H L H Latch register and disable outputs H H L L I h L H Z Z OPERATING MODES H h L I Z Q0 to Q7 = HIGH voltage level = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition = High impedance OFF-state PIN CONFIGURATION LOGIC SYMBOL 1 OE 1 20 VCC D0 2 19 Q0 D1 3 18 D2 4 D3 OE 2 D0 Q0 19 Q1 3 D1 Q1 18 17 Q2 4 D2 Q2 17 5 16 Q3 5 D3 Q3 16 D4 6 15 Q4 6 D4 Q4 15 D5 7 14 Q5 7 D5 Q5 14 D6 8 13 Q6 8 D6 Q6 13 D7 9 12 Q7 9 D7 Q7 12 GND 10 11 LE LE 11 SV00701 1998 Jun 10 3 SV00702 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) LOGIC SYMBOL (IEEE/IEC) 11 1 2 74LV573 FUNCTIONAL DIAGRAM C1 2 D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 Q3 16 Q4 15 EN1 19 1D 3 18 4 17 5 16 6 15 7 14 8 9 3-STATE OUTPUTS LATCH 1 TO 8 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 13 11 LE 12 1 OE SV00703 SV00704 LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 Q D LATCH 1 Q D LATCH 2 Q D LATCH 3 Q D LATCH 4 Q D LATCH 5 Q D LATCH 6 Q D LATCH 7 Q D LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SV00661 1998 Jun 10 4 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV573 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC DC supply voltage ±IIK DC input diode current ±IOK ±IO ±IGND, ±ICC CONDITIONS RATING UNIT –0.5 to +7.0 V VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current – bus driver outputs –0.5V < VO < VCC + 0.5V 35 mA 70 mA –65 to +150 °C DC VCC or GND current for types with –bus driver outputs Tstg Storage temperature range Ptot t t Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER DC supply voltage CONDITIONS MIN TYP. MAX UNIT See Note 1 1.0 3.3 5.5 V VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V +85 +125 °C 500 200 100 50 ns/V Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V –40 –40 – – – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 Jun 10 5 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV573 DC CHARACTERISTICS FOR THE LV FAMILY Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 HIGH level output voltage; BUS driver outputs LOW level output voltage all outputs out uts voltage; VOL LOW level output voltage; BUS driver outputs MIN 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*VCC UNIT MAX V 0.7*VCC VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 0.3*VCC 0.3*VCC VCC = 1.2V; VI = VIH or VIL; –IO = 100µA VOH MAX VCC = 1.2V VCC = 4.5 to 5.5 HIGH level output voltage out uts voltage; all outputs -40°C to +125°C V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5V;VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 VCC = 3.0V;VI = VIH or VIL; –IO = 8mA 2.40 2.82 2.20 VCC = 4.5V;VI = VIH or VIL; –IO = 16mA 3.60 4.20 3.50 V VCC = 1.2V; VI = VIH or VIL; IO = 100µA VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 8mA 0.20 0.40 0.50 VCC = 4.5V;VI = VIH or VIL; IO = 16mA 0.35 0.55 0.65 1.0 1.0 µA 5 10 µA V Input leakage current VCC = 5.5V; VI = VCC or GND IOZ 3-State output OFF-state current VCC = 5.5V; VI = VIH or VIL; VO = VCC or GND ICC Quiescent supply current; MSI VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA II NOTE: 1. All typical values are measured at Tamb = 25°C. 1998 Jun 10 6 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV573 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL tPHL/tPLH tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th PARAMETER Propagation delay Dn to Qn Propagation delay LE to Qn 3 State output 3-State out ut enable time OE to t Q Qn 3 State output 3-State out ut disable time t Q OE to Qn LE pulse width HIGH Setup time Dn to LE Setu Hold time Dn to LE WAVEFORM Figures 1, 5 Figures 2, 5 Figures 3, 5 Figures 3, 5 Figure 2 Figure 4 Figure 4 VCC(V) MIN TYP 1.2 – 2.0 – LIMITS –40 to +125 °C MAX MIN 75 – – – 26 39 – 49 2.7 – 19 29 – 36 – 142 23 – 29 4.5 to 5.5 – _ 19 – 24 1.2 – 80 – – – 2.0 – 27 43 – 53 2.7 – 20 31 – 34 3.0 to 3.6 – 152 25 – 31 4.5 to 5.5 – – 21 – 26 1.2 – 70 – – – 2.0 – 24 37 – 48 2.7 – 18 28 – 35 3.0 to 3.6 – 132 22 – 28 4.5 to 5.5 – – 18 – 23 1.2 – 80 – – – 2.0 – 29 39 – 48 2.7 – 22 29 – 36 3.0 to 3.6 – 172 24 – 29 4.5 to 5.5 – – 20 – 24 2.0 34 9 – 41 – 2.7 25 6 – 30 – 3.0 to 3.6 20 52 – 24 – 1.2 – 25 – – – 2.0 17 9 – 20 – 2.7 13 6 – 15 – 3.0 to 3.6 10 52 – 12 – 1.2 – 5 – – – 2.0 8 2 – 8 – 2.7 8 2 – 8 – 3.0 to 3.6 8 12 – 8 – 7 UNIT MAX 3.0 to 3.6 NOTES: All typical values are measured at Tamb = 25°C 1. Typical values are measured at VCC = 3.3V 1998 Jun 10 LIMITS –40 to +85 °C CONDITION ns ns ns ns ns ns ns Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV573 ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ AC WAVEFORMS VM = 1.5V at VCC 2.7V and 3.6V VM = 0.5 * VCC at VCC 2.7V and 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC 2.7V and 3.6V VX = VOL + 0.1VCC at VCC < 2.7V and 4.5V VY = VOH – 0.3V at VCC 2.7V and 3.6V VY = VOH – 0.1VCC at VCC < 2.7V and 4.5V VI Dn INPUT VM GND th tsu tsu VI VI LE INPUT Dn INPUT th VM VM GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. GND tPHL tPLH SV00665 Figure 4. Data set-up and hold times for the Dn input to the LE input VOH Qn OUTPUT VM VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SV00705 Figure 1. Data input (Dn) to output (Qn) propagation delays and the output transition times TEST CIRCUIT VI LE INPUT VCC VM 2 * VCC Open GND GND tW PULSE GENERATOR VOH Qn OUTPUT RL = 1k VO VI tPLH tPHL D.U.T. VM RT CL RL = 1k 50 pF VOL SV00706 Test Circuit for Outputs Figure 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays and the output transition times. DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitiance. RT = Termination resistance should be equal to ZOUT of pulse generators. SWITCH POSITION VI OE INPUT GND tPLZ VCC Qn OUTPUT LOW-to-OFF OFF-to-LOW VOL tPZL VCC tPLH/tPHL Open < 2.7V VCC tPLZ/tPZL 2 * VCC 2.7–3.6V 2.7V tPHZ/tPZH GND 4.5V VI VCC VM VX SV00896 VOH Qn OUTPUT HIGH-to-OFF OFF-to-HIGH GND Figure 5. Load circuitry for switching times tPZH tPHZ VY VM outputs enabled outputs disabled outputs enabled SV00664 Figure 3. 3-State enable and disable times 1998 Jun 10 S1 TEST VM 8 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) DIP20: plastic dual in-line package; 20 leads (300 mil) 1998 Jun 10 9 74LV573 SOT146-1 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1998 Jun 10 10 74LV573 SOT163-1 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1998 Jun 10 11 74LV573 SOT339-1 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1998 Jun 10 12 74LV573 SOT360-1 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) NOTES 1998 Jun 10 13 74LV573 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV573 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Jun 10 14 Date of release: 05-96 9397-750-04453