INTEGRATED CIRCUITS PCA9538 8-bit I2C and SMBus low power I/O port with interrupt and reset Product data sheet Supersedes data of 2004 Sep 30 Philips Semiconductors 2004 Oct 05 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 DESCRIPTION The PCA9538 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C/SMBus applications and was developed to enhance the Philips family of I2C I/O expanders. I/O expanders provides a simple solution when additional I/O is needed for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc. The PCA9538 consists of an 8-bit Configuration register (Input or Output selection); 8-bit Input register, 8-bit Output register and an 8-bit Polarity inversion register (Active HIGH or Active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the input port register can be inverted with the Polarity Inversion Register. All registers can be read by the system master. FEATURES • 8-bit I2C GPIO with interrupt and reset • Operating power supply voltage range of 2.3 V to 5.5 V • 5 V tolerant I/Os • Polarity inversion register • Active LOW interrupt output • Active LOW reset input • Low stand-by current • Noise filter on SCL/SDA inputs • No glitch on power-up • Internal power-on reset • 8 I/O pins which default to 8 inputs • 0 kHz to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, The PCA9538 is identical to the PCA9554 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW, replacement of A2 with RESET and different address range. The PCA9538 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without depowering the device. Two hardware pins (A0 and A1) vary the fixed I2C address and allow up to four devices to share the same I2C/SMBus. 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA • Offered in three different packages: SO16, TSSOP16, and HVQFN16 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER 16-Pin Plastic SO (wide) –40 °C to +85 °C PCA9538D PCA9538D SOT162-1 16-Pin Plastic TSSOP –40 °C to +85 °C PCA9538PW PCA9538 SOT403-1 16-Pin Plastic HVQFN –40 °C to +85 °C PCA9538BS 9538 SOT629-1 Standard packing quantities and other packing data are available at www.standardproducts.philips.com/packaging. I2C-bus is a trademark of Philips Semiconductors Corporation. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent. 2004 Oct 05 2 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 I/O0 4 13 INT I/O1 5 12 I/O7 I/O2 6 11 I/O6 I/O3 7 10 I/O5 VSS 8 9 13 14 SCL SDA RESET 1 12 SCL I/O0 2 11 INT I/O1 3 10 I/O7 I/O2 4 9 5 I/O4 I/O3 SW02172 VSS I/O4 I/O6 8 15 SDA VDD 14 2 A0 7 A1 RESET 3 A1 15 16 VDD 6 A0 1 PIN CONFIGURATION — HVQFN 16 PIN CONFIGURATION — SO, TSSOP I/O5 TOP VIEW Figure 1. Pin configuration — SO, TSSOP SW02173 Figure 2. Pin Configuration — HVQFN PIN DESCRIPTION SO, TSSOP PIN NUMBER HVQFN PIN NUMBER SYMBOL 1 15 A0 Address input 0 2 16 A1 Address input 1 3 1 RESET Active LOW reset input 4–7 2–5 I/O0–3 I/O0 to I/O3 8 6 VSS 9–12 7–10 I/O4–7 FUNCTION Supply ground I/O4 to I/O7 13 11 INT Interrupt output (open drain) 14 12 SCL Serial clock line 15 13 SDA Serial data line 16 14 VDD Supply voltage BLOCK DIAGRAM PCA9538 A0 I/O0 A1 I/O1 SCL SDA I/O2 INPUT FILTER 8-BIT I2C/SMBUS CONTROL INPUT/ OUTPUT PORTS I/O3 I/O4 WRITE pulse I/O5 READ pulse I/O6 I/O7 VDD RESET VCC POWER-ON RESET INT VSS LP FILTER NOTE: ALL I/Os ARE SET TO INPUTS AT RESET SW02174 Figure 3. Block diagram 2004 Oct 05 3 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 REGISTERS Power-on Reset When power is applied to VDD, an internal power-on reset holds the PCA9538 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9538 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. Command Byte Command Protocol Function 0 Read byte Input port register 1 Read/write byte Output port register 2 Read/write byte Polarity inversion register 3 Read/write byte Configuration register For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. RESET Input A reset can be accomplished by holding the RESET pin LOW for a minimum of tW. The PCA9538 registers and SMBus/I2C state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if no active connection is used. The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. Register 0 – Input Port Register bit I7 I6 I5 I4 I3 I2 I1 I0 default X X X X X X X X Interrupt Output The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the input port register is read. This register is a read only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register. The default value ‘X’ is determined by the externally applied logic level. Register 1 – Output Port Register bit O7 O6 O5 O4 O3 O2 O1 O0 default 1 1 1 1 1 1 1 1 This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, NOT the actual pin value. Register 2 – Polarity Inversion Register bit N7 N6 N5 N4 N3 N2 N1 N0 default 0 0 0 0 0 0 0 0 This register allows the user to invert the polarity of the Input Port Register data. If a bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. Register 3 – Configuration Register bit C7 C6 C5 C4 C3 C2 C1 C0 default 1 1 1 1 1 1 1 1 This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs. 2004 Oct 05 4 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7 DATA FROM SHIFT REGISTER OUTPUT PORT REGISTER DATA CONFIGURATION REGISTER DATA FROM SHIFT REGISTER VDD Q D Q1 FF WRITE CONFIGURATION PULSE WRITE PULSE CK ESD PROTECTION DIODE Q D Q FF CK I/O0 TO I/O7 Q Q2 OUTPUT PORT REGISTER INPUT PORT REGISTER D Q ESD PROTECTION DIODE VSS INPUT PORT REGISTER DATA FF READ PULSE Q CK DATA FROM SHIFT REGISTER TO INT D Q POLARITY REGISTER DATA FF WRITE POLARITY PULSE CK Q POLARITY INVERSION REGISTER NOTE: At Power-on Reset, all registers return to default values. Figure 4. Simplified schematic of I/O0 to I/O7 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low impedance paths that exist between the pin and either VDD or VSS. 2004 Oct 05 5 SU01784 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 Device address SLAVE ADDRESS 1 1 1 0 FIXED 0 A1 A0 R/W HARDWARE SELECTABLE SW02175 Figure 5. PCA9538 address Bus transactions Data is transmitted to the PCA9538 registers using the write mode as shown in Figures 6 and 7. Data is read from the PCA9538 registers using the read mode as shown in Figures 8 and 9. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. 1 SCL 2 3 4 5 6 7 8 9 command byte slave address SDA S 1 1 1 0 0 A1 A0 start condition 0 A R/W 0 0 0 0 0 data to port 0 0 1 acknowledge from slave DATA 1 A A acknowledge from slave P acknowledge from slave WRITE TO PORT DATA OUT FROM PORT DATA 1 VALID tpv SW02176 Figure 6. WRITE to output port register 1 SCL 2 3 4 5 6 7 8 9 command byte slave address SDA S 1 1 start condition 1 0 0 A1 A0 0 R/W A 0 0 0 0 0 acknowledge from slave data to register 0 1 1/0 A DATA acknowledge from slave A P acknowledge from slave DATA TO REGISTER SW02177 Figure 7. WRITE to configuration or polarity inversion registers 2004 Oct 05 6 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset acknowledge from slave slave address S 1 1 1 0 0 A1 A0 0 PCA9538 acknowledge from slave COMMAND BYTE A A S acknowledge from slave slave address 1 1 1 0 0 A1 A0 R/W 1 acknowledge from master data from register DATA A A first byte R/W at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter data from register no acknowledge from master NA DATA P last byte SW02178 Figure 8. READ from register 1 SCL 2 3 4 5 6 7 8 9 slave address SDA S 1 1 start condition 1 0 0 data from port A1 A0 1 R/W data from port DATA 1 A A acknowledge from slave DATA 4 acknowledge from master NA no acknowledge from master P stop condition READ FROM PORT DATA INTO PORT DATA 2 DATA 3 tph DATA 4 tps INT tiv tir SW02179 NOTES: 1. This figure assumes the command byte has previously been programmed with 00h. 2. Transfer of data can be stopped at any moment by a stop condition. Figure 9. READ input port register 2004 Oct 05 7 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 TYPICAL APPLICATION VDD (5 V) 100 kΩ (×3) 2 kΩ VDD 10 kΩ 10 kΩ 10 kΩ 10 kΩ VDD MASTER CONTROLLER SCL SCL SDA SDA INT INT SUBSYSTEM 1 (e.g. temp sensor) I/O0 INT I/O1 IRESET I/O2 IRESET RESET GND I/O3 SUBSYSTEM 2 (e.g. counter) I/O4 PCA9538 I/O5 A Controlled Switch (e.g. CBT device) I/O6 ENABLE A1 I/O7 B A0 VSS ALARM SUBSYSTEM 3 (e.g. alarm system) NOTE: Device address configured as 1110000 for this example I/O0, I/O2, I/O3, configured as outputs I/O1, I/O4, I/O5, configured as inputs I/O06, I/O7, are not used and need 100 kΩ pull-up resistors to protect them from floating. VDD SW02180 Figure 10. Typical application Minimizing IDD when the I/O is used to control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 10. Since the LED acts as a diode, when the LED is off the I/O VIN is about 1.2 V less than VDD. The supply current , IDD, increases as VIN becomes lower than VDD and is specified as ∆IDD in the DC characteristics table. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 11 shows a high value resistor in parallel with the LED. Figure 12 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VDD and prevents additional supply current consumption when the LED is off. 3.3 V VDD LED 100 kΩ VDD VDD LEDx LED LEDx SW02086 SW02087 Figure 11. High value resistor in parallel with the LED 2004 Oct 05 5V Figure 12. Device supplied by a lower voltage 8 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) PARAMETER SYMBOL VDD II CONDITIONS Supply voltage DC input current VI/O DC voltage on an I/O MIN MAX UNIT –0.5 6.0 V — ±20 mA VSS – 0.5 5.5 V II/O DC output current on an I/O — ±50 mA IDD Supply current — 85 mA ISS Supply current — 100 mA Ptot Total power dissipation — 200 mW Tstg Storage temperature range –65 +150 °C Tamb Operating ambient temperature –40 +85 °C TJ(MAX) Maximum junction temperature — +125 °C 2004 Oct 05 9 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”. DC CHARACTERISTICS VDD = 2.3 to 5.5 V; VSS = 0 V; Tamb = –40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Supplies VDD Supply voltage 2.3 — 5.5 V — 104 175 µA IDD Supply current Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz Istbl Standby current Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs — 0.25 1 µA Istbh Standby current Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs — 0.25 1 µA Power-on reset voltage (Note 1) No load; VI = VDD or VSS — 1.5 1.65 V V VPOR Input SCL; input/output SDA VIL LOW-level input voltage –0.5 — 0.3 VDD VIH HIGH-level input voltage 0.7 VDD — 5.5 V IOL LOW-level output current VOL = 0.4V 3 tbd — mA IL Leakage current VI = VDD = VSS –1 — +1 µA CI Input capacitance VI = VSS — 5 10 pF VIL LOW-level input voltage –0.5 — 0.8 V VIH HIGH-level input voltage 2.0 — 5.5 V VOL = 0.5 V; VDD = 2.3 V; Note 2 8 10 — mA VOL = 0.7 V; VDD = 2.3 V; Note 2 10 13 — mA VOL = 0.5 V; VDD = 4.5 V; Note 2 8 17 — mA VOL = 0.7 V; VDD = 4.5 V; Note 2 10 24 — mA VOL = 0.5 V; VDD = 3.0 V; Note 2 8 14 — mA VOL = 0.7 V; VDD = 3.0 V; Note 2 10 19 — mA IOH = –8 mA; VDD = 2.3 V; Note 3 1.8 — — V IOH = –10 mA; VDD = 2.3 V; Note 3 1.7 — — V IOH = –8 mA; VDD = 3.0 V; Note 3 2.6 — — V IOH = –10 mA; VDD = 3.0 V; Note 3 2.5 — — V IOH = –8 mA; VDD = 4.5 V; Note 3 4.1 — — V IOH = –10 mA; VDD = 4.5 V; Note 3 4.0 — — V VI = VDD = VSS –1 — 1 µA — 5 10 pF 3 tbd — mA I/Os IOL O VOH O LOW level output current LOW-level HIGH level output voltage HIGH-level IIL Input leakage current CI Input capacitance Interrupt INT IOL LOW-level output current VOL = 0.4 V Select Inputs A0, A1, and RESET VIL LOW-level input voltage –0.5 — 0.8 V VIH HIGH-level input voltage 2.0 — 5.5 V ILI Input leakage current –1 — 1 µA NOTES: 1. VDD must be lowered to 0.2 V in order to reset part. 2. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. 3. The total current sourced by all I/Os must be limited to 85 mA. 2004 Oct 05 10 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 AC SPECIFICATIONS SYMBOL STANDARD MODE I2C-bus PARAMETER fSCL Operating frequency tBUF FAST MODE I2C-bus UNITS MIN MAX MIN MAX 0 100 0 400 kHz Bus free time between STOP and START conditions 4.7 — 1.3 — µs tHD;STA Hold time after (repeated) START condition 4.0 — 0.6 — µs tSU;STA Repeated START condition setup time 4.7 — 0.6 — µs tSU;STO Setup time for STOP condition 4.0 — 0.6 — µs tHD;DAT Data in hold time 0 — 0 — ns tVD;ACK Valid time for ACK 0.3 3.45 0.1 0.9 µs tVD;DAT Data out valid time3 300 — 50 — ns tSU;DAT Data setup time 250 — 100 — ns condition2 tLOW Clock LOW period 4.7 — 1.3 — µs tHIGH Clock HIGH period 4.0 — 0.6 — µs tF Clock/Data fall time — 300 20 + 0.1 Cb1 300 ns 1 tR Clock/Data rise time — 1000 20 + 0.1 Cb 300 ns tSP Pulse width of spikes that must be suppressed by the input filters — 50 — 50 ns Port Timing tPV Output data valid — 200 — 200 ns tPS Input data setup time 100 — 100 — ns tPH Input data hold time 1 — 1 — µs Interrupt Timing tIV Interrupt valid — 4 — 4 µs tIR Interrupt reset — 4 — 4 µs Reset pulse width 4 — 4 — ns Reset recovery time 0 — 0 — ns 400 — 400 — ns RESET tW tREC tRESET Time to reset NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL low. SDA tBUF tLOW tR tF tHD;STA tSP SCL tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P SU00645 Figure 13. Definition of timing 2004 Oct 05 11 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 START ACK OR READ CYCLE SCL SDA 30% tRESET RESET 50% 50% 50% tREC tW tRESET 50% I/Ox I/O configured as inputs SW02340 Figure 14. Definition of RESET timing 70 % SCL 2 1 0 A P 30 % SDA tPS tPH INPUT 50 % tIV tIR INT SW02329 Figure 15. Expanded view of Read input port register 70 % SCL 2 1 0 A P 30 % SDA tPV OUTPUT 50 % SW02330 Figure 16. Expanded view of Write to output port register 2004 Oct 05 12 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset BIT 7 MSB (A7) START CONDITION (S) PROTOCOL t t SU;STA BIT 6 (A6) t HIGH LOW PCA9538 BIT 0 (R/W) STOP CONDITION (S) ACKNOWLEDGE (A) 1 / f SCL SCL t t f tr BUF SDA t t HD;STA t SU;DAT t HD;DAT tSU;STO VD;DAT t VD;ACK Figure 17. I2C-bus timing diagram; rise and fall times refer to VIL and VIH TEST CIRCUITS VDD VDD Open RL = 500 Ω VO VI PULSE GENERATOR D.U.T. RT CL 50 pF DEFINITIONS RL = Load resistor. CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to the output impedance ZO of the pulse generators. SW02181 Figure 18. Test circuitry for switching times 2VDD 500 Ω From Output Under Test S1 Open GND 500 Ω CL = 50 pF Load Circuit TEST S1 tpv 2 VDD SA00652 Figure 19. Test circuit 2004 Oct 05 13 SW02210 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 SO16: plastic small outline package; 16 leads; body width 7.5 mm 2004 Oct 05 14 SOT162-1 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 2004 Oct 05 15 SOT403-1 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm 2004 Oct 05 16 SOT629-1 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 REVISION HISTORY Rev Date Description _3 20041005 Product data sheet (9397 750 14176). Supersedes data of 2004 Sep 30 (9397 750 14049). Modifications: • Upgrade status to “Product data sheet” _2 20040930 Objective data sheet (9397 750 14049). Supersedes data of 2004 Aug 20 (9397 750 12881). _1 20040820 Objective data sheet (9397 750 12881). 2004 Oct 05 17 Philips Semiconductors Product data sheet 8-bit I2C and SMBus low power I/O port with interrupt and reset PCA9538 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 10-04 For sales offices addresses send e-mail to: [email protected]. Document order number: Philips Semiconductors 2004 Oct 05 18 9397 750 14176