REVISIONS LTR DESCRIPTION DATE APPROVED A Add EP suffix to generic number and correct the vendor part number. - CFS 04-01-29 Thomas M. Hess B Correct lead finish. Update boilerplate. - CFS 05-11-08 Thomas M. Hess C Update boilerplate paragraphs to current requirements. - PHN 12-03-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV C C C C PAGE 40 41 42 43 REV C C C C C C C C C C C C C C C C C C C C C C PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV C C C C C C C C C C C C C C C C C PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 REV STATUS OF PAGES PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing CHECKED BY TITLE Phu H. Nguyen YY MM DD APPROVED BY 03-12-09 MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON Thomas M. Hess SIZE A REV AMSC N/A DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 CODE IDENT. NO. DWG NO. V62/04605 16236 C PAGE 1 OF 43 5962-V043-12 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04605 - Drawing number 1.2.1 Device type(s). 01 X A Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1/ Device type Generic 01 SM32VC5510-EP Circuit function Fixed Point Digital Signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins X 240 Package style Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z 1.3 Absolute maximum ratings. Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other 2/ Supply voltage I/O range, (DVDD) ............................................................................................. Supply voltage core range, (CVDD) ........................................................................................... Input voltage range, (VI) ........................................................................................................... Output voltage range, (VO) ....................................................................................................... Operating case temperature ranges, (TC): (Extended) ............................................................. Storage temperature range, (TSTG)............................................................................................ 1/ 2/ 3/ 4/ -0.3 V to +4.0 V 3/ -0.3 V to +2.0 V 3/ -0.3 V to +4.5 V -0.3 V to +4.5 V -40C to +85C 4/ -55C to +150C 4/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS. Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See manufacturer data for additional information on enhanced plastic packaging. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 2 1.4 Recommended operating conditions. 3/ Device supply voltage, I/O (DVDD) .............................................................................. Device supply voltage, core (CVDD) ............................................................................ Supply voltage, GND (VSS) ......................................................................................... High level input voltage, I/O (VIH): Hysteresis inputs, DVDD = 3.3 0.3 V .................................................................... All other inputs ...................................................................................................... Low level input voltage, I/O (VIL): Hysteresis inputs, DVDD = 3.3 0.3 V .................................................................... All other inputs ...................................................................................................... High level output current, (IOH), All outputs: ................................................................ Low level output current, (IOL), All outputs: ................................................................. Operating case temperature (TC), Extended temperature range ................................ Junction to case (RθJC) Board type: 2s JEDEC test card 5/ ................................................................... Junction to air (RθJA) Board type: High K 6/ Air flow = 0 LFM ........................................................................................ Air flow = 150 LFM .................................................................................... Air flow = 250 LFM .................................................................................... Board type: Low K 6/ Air flow = 0 LFM ........................................................................................ Air flow = 150 LFM .................................................................................... Air flow = 250 LFM .................................................................................... +3.0 V to +3.6 V +1.55 V to +1.65 V 0V 5/ 2.4 V to DVDD + 0.3 V 2.0 V to DVDD + 0.3 V -0.3 V to +0.8 V -0.3 V to +0.8 V -8 mA maximum 8 mA maximum -40C to +85C 6C/W 26C/W 22C/W 20C/W 50C/W 35C/W 29C/W 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 JESD51-9 – – Registered and Standard Outlines for Semiconductor Devices Test Boards for Area Array Surface Mount Package Thermal Measurements. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201.) 5/ 6/ Prototype revision 2.1 and 2.2 and production silicon. See the TMS320VC5510 Digital Signal Silicon Errata (literature number SPRZ008) for further clarification and distinguishing marking. Board types are as defined by JEDEC. See JEDEC Standard JESD51-9. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 3 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Load circuit. The load circuit shall be as specified in figure 4. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figures 5 - 27. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 4 TABLE I. Electrical performance characteristics. No. Test High level output voltage Symbol All output except CLKOUT VOH CLKOUT Limits Min DVDD = 3.3 0.3 V, IOH = Max 2.4 CVDD = 1.6 0.05 V, IOH = Max 1.24 Unit Max V 0.4 V -275 275 A Bus holders disabled CVDD = Max, VO = VSS to VDD -5 5 CVDD = Max, VI = VSS to VDD -5 300 Input pins with internal pullup Pullup enabled CVDD = Max, VI = VSS to VDD -300 5 All other input only pins or input only pins with pullup/plldown disabled CVDD = Max, VI = VSS to VDD -5 5 VOL Output only or input/output pins with bus holders IIZ All other output only or input/output pins Input pins with internal pulldown Input current Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Bus holders enabled CVDD = Max, VO = VSS to VDD Low level output voltage Input current for outputs in high impedance 1/ II IOL = Max A CVDD supply current, CPU plus internal memory access 2/ IDDC CVDD = 1.6 V, TC = 25C CPU clock = 200 MHz 112 Typ mA DVDD supply current, pins active IDDP DVDD = 3.3 V, TC = 25C CPU clock = 100 MHz 8 Typ mA IDDC CVDD = 1.6 V, TC = 25C 10 MHz clock input, DLL mode = x 20 32 Typ mA CVDD = 1.6 V, TC = 25C Input clock stopped. 69 Typ A CVDD = 1.6 V, TC = 55C Input clock stopped. 374 Typ CVDD = 1.6 V, TC = 85C Input clock stopped. 976 Typ DVDD = 3.3 V, TC = 25C No pin activity. 10 Typ DVDD = 3.3 V, TC = 55C No pin activity. 10 Typ DVDD = 3.3 V, TC = 85C No pin activity. 10 Typ 3/ CVDD supply current, standby Only CLKGEN domain enabled, PLL enabled CVDD supply current, standby All domains idled IDDC DVDD supply current, standby All domains idled IDDP A Input capacitance CI 3 Typ pF Output capacitance CO 3 Typ pF See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 5 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted 1/ Limits Unit Min Max 20 4/ CLOCK GENERATION IN BYPASS MODE (DPLL Disabled) CLKIN in Bypass Mode Timing Requirements C7 Cycle time, CLKIN tc(CI) C8 Fall time, CLKIN tf(CI) See figure 5 6 C9 Rise time, CLKIN tr(CI) 6 C10 Pulse duration, CLKIN low tW(CIL) 4 C11 Pulse duration, CLKIN high tW(CIH) 4 ns CLKOUT in bypass mode switching characteristics C1 Cycle time, CLKOUT 5/ tc(CO) See figure 5 20 C2 Delay time, CLKIN high/low to CLKOUT high/low C3 Fall time, CLKOUT C4 Rise time, CLKOUT C5 Pulse duration , CLKOUT low tW(COL) H-1 H+1 C6 Pulse duration , CLKOUT high tW(COH) H-1 H+1 td(CI-CO) ns 1 14 tf(CO) 1 Typ tr(CO) 1 Typ CLOCK GENERATION IN LOCK MODE (DPLL Synthesis Enabled) CLKIN in lock mode timing requirements C7 Cycle time, CLKIN DPLL synthesis enable tc(CI) See figure 6 20 6/ C8 Fall time, CLKIN tf(CI) C9 Rise time, CLKIN C10 Pulse duration, CLKIN low tW(CIL) 4 C11 Pulse duration, CLKIN high tW(CIH) 4 400 ns 6 tr(CI) 6 CLKOUT in lock mode switching characteristics C1 Cycle time, CLKOUT C2 Delay time, CLKIN high/low to CLKOUT high/low tc(CO) See figure 6 5 td(CI-CO) ns 1 14 C3 Fall time, CLKOUT tf(CO) 1 Typ C4 Rise time, CLKOUT tr(CO) 1 Typ C5 Pulse duration , CLKOUT low tW(COL) H-1 H+1 C6 Pulse duration , CLKOUT high tW(COH) H-1 H+1 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 6 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max ASYNCHRONOUS MEMORY TIMING Asynchronous memory cycles timing requirements A6 Setup time, read data valid before CLKOUT high 7/ tsu(DV-COH) A7 Hold time, read data valid after CLKOUT high th(COH-DV) 0 A10 Setup time, ARDY valid before CLKOUT high tsu(ARDY-COH) 7 A11 Hold time, ARDY valid after CLKOUT high th(COH-ARDY) 0 Asynchronous memory cycle switching characteristics See figure 7 and 8 6 ns 8/ 9/ A1 Delay time, CLKOUT high to CEx transaction td(COH-CEV) A2 Delay time, CLKOUT high to BEx valid td(COH-BEV) A3 Delay time, CLKOUT high to BEx invalid td(COH-BEIV) A4 Delay time, CLKOUT high to address valid td(COH-AV) A5 Delay time, CLKOUT high to address invalid See figure 7 and 8 -2 4 4 -2 4 td(COH-AIV) -2 Delay time, CLKOUT high to AOE valid td(COH-AOEV) -2 4 A9 Delay time, CLKOUT high to ARE td(COH-AREV) -2 4 A12 Delay time, CLKOUT high to data valid (write) A13 Delay time, CLKOUT high to data invalid (write) A8 A14 Delay time, CLKOUT high to AWE valid ns td(COH-DV) 4 td(COH-DIV) -2 td(COH-AWEV) -2 4 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 7 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max SYNCHRONOUS BURST SRAM (SBSRAM) TIMING Synchronous burst SRAM cycle timing requirements SB7 Setup time, read data valid before CLKMEM high tsu(DV-CLKMEMH) SB8 Hold time, read data valid after CLKMEM high th(CLKMEMH-DV) See figure 9 5 ns 2 Synchronous burst SRAM cycle switching characteristics SB1 Delay time, CLKMEM high to CEx low td(CLKMEMH-CEL) SB2 Delay time, CLKMEM high to CEx high SB3 See figure 9 3 6 td(CLKMEMH-CEH) 3 6 Delay time, CLKMEM high to BEx valid td(CLKMEMH-BEV) 3 6 SB4 Delay time, CLKMEM high to BEx invalid td(CLKMEMH-BEIV) 3 6 SB5 Delay time, CLKMEM high to address valid td(CLKMEMH-AV) 3 6 SB6 Delay time, CLKMEM high to address invalid td(CLKMEMH-AIV) 3 6 SB9 Delay time, CLKMEM high to SSADS low td(CLKMEMH-ADSL) 3 6 SB10 Delay time, CLKMEM high to SSADS high td(CLKMEMH-ADSH) 3 6 SB11 Delay time, CLKMEM high to SSOE low td(CLKMEMH-OEL) 3 6 SB12 Delay time, CLKMEM high to SSOE high td(CLKMEMH-OEH) 3 6 SB13 Delay time, CLKMEM high to data valid td(CLKMEMH-DV) 3 6 SB14 Delay time, CLKMEM high to data invalid td(CLKMEMH-DIV) 3 6 SB15 Delay time, CLKMEM high to SSWE low td(CLKMEMH-WEL) 3 6 SB16 Delay time, CLKMEM high to SSWE high td(CLKMEMH-WEH) 3 6 ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 8 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max SYNCHRONOUS DRAM (SDRAM) TIMING Synchronous DRAM cycle timing requirements SB7 Setup time, read data valid before CLKMEM high tsu(DV-CLKMEMH) SB8 Hold time, read data valid after CLKMEM high th(CLKMEMH-DV) See figure 10-12 5 ns 2 Synchronous DRAM cycle switching characteristics SB1 Delay time, CLKMEM high to CEx low td(CLKMEMH-CEL) SB2 Delay time, CLKMEM high to CEx high SB3 3 6 td(CLKMEMH-CEH) 3 6 Delay time, CLKMEM high to BEx valid td(CLKMEMH-BEV) 3 6 SB4 Delay time, CLKMEM high to BEx invalid td(CLKMEMH-BEIV) 3 6 SB5 Delay time, CLKMEM high to address valid td(CLKMEMH-AV) 3 6 SB6 Delay time, CLKMEM high to address invalid td(CLKMEMH-AIV) 3 6 SB9 Delay time, CLKMEM high to SDCAS low td(CLKMEMH-SDCASL) 3 5 SB10 Delay time, CLKMEM high to SDCAS high td(CLKMEMH-SDCASH) 3 5 SB11 Delay time, CLKMEM high to data valid td(CLKMEMH-DV) 3 5 SB12 Delay time, CLKMEM high to data invalid td(CLKMEMH-DIV) 3 5 SB13 Delay time, CLKMEM high to SDWE low td(CLKMEMH-SDWEL) 3 5 SB14 Delay time, CLKMEM high to SDWE high Delay time, CLKMEM high to SDA10 valid Delay time, CLKMEM high to SDA10 invalid td(CLKMEMH-SDWEH) 3 5 td(CLKMEMH-SDA10V) 3 5 td(CLKMEMH-SDA10IV) 3 5 SB15 SB16 See figure 10-12 SB17 Delay time, CLKMEM high to SSWE low td(CLKMEMH-SDRASL) 3 5 SB18 Delay time, CLKMEM high to SSWE high td(CLKMEMH-SDRASH) 3 5 ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 9 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max HOLD AND HOLDA TIMINGS HOLD and HOLDA timing requirements H1 Setup time, HOLD high before CLKOUT high 10/ HOLD and HOLDA switching characteristics tsu(HOLDH-COH) See figure 13 7 tR(COH-BHZ) See figure 13 4P ns 11/ H2 Response time, CLKOUT high to EMIF bus high impedance (HZ) 13/ 12/ H3 Response time, CLKOUT high to HOLDA low tR(COH-HOLDAL) 5P-1 H4 Response time, CLKOUT high to HOLDA high tR(COH-HOLDAH) 4P-1 4P+5 H5 Response time, CLKOUT high to EMIF bus low impedance (LZ) (active) 13/ tR(COH-BLZ) 4P-1 4P+5 ns RESET TIMINGS Reset timing requirements R1 Pulse width, reset low tw(RSL) See figure 14 td(RSL-EMIFHZ) See figure 14 2P+5 ns Reset timing switching characteristics R3 Delay time, reset low to EMIF group high impedance 14/ R4 Delay time, reset low to EMIF group valid 14/ td(RSL-EMIFV) 38P+19 R5 Delay time, reset low to low group invalid 15/ td(RSL-LOWIV) 17 R6 Delay time, reset low to low group valid td(RSL-LOWV) 38P+17 R7 Delay time, reset low to high group invalid 15/ td(RSL-HIGHIV) 9 R8 Delay time, reset low to high group valid td(RSL-HIGHV) 38P+9 R9 Delay time, reset low to Z group high impedance 16/ td(RSL-ZHZ) 18 R10 Delay time, reset low to Z group valid td(RSL-ZV) 38P+18 15/ 15/ 16/ 19 ns EXTERNAL INTERRUPT TIMINGS External interrupt timing requirements 11/ I1 Pulse width, interrupt low, CPU active tw(INTL)A I2 Pulse width, interrupt high, CPU active tw(INTH)A See figure 15 3P ns 2P See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 10 TABLE I. Electrical performance characteristics - Continued. No. Test 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Symbol Limits Unit Min Max 0 4 0 4 XF TIMINGS XF switching characteristics X1 Delay time, CLKOUT high to XF high td(XF) See figure 16 Delay time, CLKOUT high to XF low ns GENERAL PURPOSE INPUT/OUTPUT (IOx) TIMINGS General Purpose Input/Output (GPIO) pins configured as Inputs timing requirements G2 Setup time, IOx input valid before CLKOUT high tsu(GPIO-COH) G3 Hold time, IOx input valid after CLKOUT high th(COH-GPIO) See figure 17 8 ns 0 General Purpose Input/Output (GPIO) pins configured as Inputs switching characteristics. G1 Delay time, CLKOUT high to IOx output change td(COH-GPIO) See figure 17 0 6 ns TIN/TOUT TIMINGS TIN/TOUT pins configures as Inputs timing requirements 11/ T4 Pulse width TIN/TOUT low tw(TIN/TOUTL) T5 Pulse width TIN/TOUT high tw(TIN/TOUTH) TIN/TOUT pins configures as outputs switching characteristics T1 Delay time, CLKOUT high to TIN/TOUT high td(COH-TIN/TOUTH) T2 Delay time, CLKOUT high to TIN/TOUT low T3 Pulse duration, TIN/TOUT (output) See figure 18 2P+1 ns 2P+1 11/ 17/ See figure 18 0 2 td(COH-TIN/TOUTL) 0 2 tw(TIN/TOUT) P ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 11 TABLE I. Electrical performance characteristics - Continued. No. Test 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Symbol Limits Min Unit Max MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMINGS McBSP transmit and receive timings 11/ 18/ M11 Cycle time, CLKR/X tc(CKRX) CLKR/X ext 2P M12 Pulse duration, CLKR/X high or CLKR/X low tw(CKRX) CLKR/X ext P-1 M13 Rise time, CLKR/X tr(CKRX) CLKR/X ext 5 M14 Fall time, CLKR/X tf(CKRX) CLKR/X ext 5 M15 Setup time, external FSR high before CLKR low tsu(FRH-CKRL) Hold time, external FSR high after CLKR low th(CKRL-FRH) M17 Setup time, DR valid before CLKR low tsu(DRV-CKRL) M18 Hold time, DR valid after CLKR low th(CKRL-DRV) M16 M19 Setup time, external FSX high before CLKX low tsu(FXH-CKXL) M20 Hold time, external FSX high after CLKX low th(CKXL-FXH) See figure 19 CLKR int 5 CLKR ext 1 CLKR int 0 CLKR ext 2 CLKR int 4 CLKR ext 1 CLKR int 0 CLKR ext 2 CLKR int 5 CLKR ext 1 CLKR int 0 CLKR ext 2 ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 12 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMINGS - Continued McBSP switching characteristics 11/ 18/ M1 Cycle time, CLKR/X CLKR/X int 2P M2 Pulse duration, CLKR/X high tw(CKRXH) CLKR/X int D - 1 19/ D + 1 19/ ns M3 Pulse duration, CLKR/X low tw(CKRXL) CLKR/X int C - 1 19/ D + 1 19/ ns M4 Delay time, CLKR high to internal FSR valid td(CKRH-FRV) -2 2 ns CLKR ext 3 7 M5 Delay time, CLKX high to internal FSX valid td(CKXH-FXV) CLKR int -2 2 CLKR ext 3 7 CLKR int 0 2 CLKR ext 1 11 M6 Disable time, CLKX high to DX high impedance following last data bit Delay time, CLKX high to DX valid. This applied to all bits except the first bit transmitted. M7 M8 Delay time, CLKX high to DX valid 20/ tc(CKRX) td(CKXH-DXV) DXENA = 0 Only applies to first bit transmitted when in data delay 1 or 2 (XDATDLY = 01b or 10b) modes DXENA = 1 Enable time, CLKX high to DX driven 20/ DXENA = 0 ten(CKXH-DX) Delay time, FSX high to DX valid 20/ DXENA = 1 td(FXH-DXV) Only applies to first bit transmitted when in data delay 0 (XDATDLY = 00b) mode. M10 CLKR int tdis(CKXH-DXHZ) Only applies to first bit transmitted when in data delay 1 or 2 (XDATDLY = 01b 0r 10b) modes M9 See figure 19 Enable time, FSX high to DX driven 20/ DXENA = 0 DXENA = 1 ten(FXH-DX) Only applies to first bit transmitted when in data delay 0 (XDATDLY = 00b) mode. DXENA = 0 DXENA = 1 ns CLKR int 6 CLKR ext 9 CLKR int 6 CLKR ext 9 CLKR int 2P+6 CLKR ext 2P+9 CLKR int 0 CLKR ext 6 CLKR int P CLKR ext P+6 ns ns ns CLKR int 5 CLKR ext 9 CLKR int 2P+5 CLKR ext 2P+9 CLKR int ns ns 0 CLKR ext 6 CLKR int P CLKR ext P+6 ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 13 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max McBSP GENERAL PURPOSE I/O TIMING McBSP general purpose I/O timing requirements M22 Setup time, MGPIOx input mode before CLKOUT high 21/ tsu(MGPIO-COH) M23 Hold time, MGPIOx input mode after CLKOUT high 21/ th(COH-MGPIO) See figure 20 7 ns 0 McBSP general purpose I/O switching characteristics M21 Delay time, CLKOUT high to MGPIOx output mode 22/ td(COH-MGPIO) See figure 20 0 3 ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 14 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted 1/ Limits Unit Master Min Slave Max Min Max McBSP as SPI MASTER OR SLAVE TIMING McBSP as SPI Master or Slave timing requirements (CLKSTP = 10b, CLKXP = 0) 11/ 23/ M30 Setup time, DR valid before CLKX low tsu(DRV-CKXL) M31 Hold time, DR valid after CLKX low th(CKXL-DRV) M32 Setup time, FSX low before CLKX high M33 Cycle time, CLKX See figure 21 4 3-6P 1 1+6P tsu(BFXL-CKXH) ns 10 tc(CKX) 2P McBSP as SPI Master or Slave switching characteristics (CLKSTP = 10b, CLKXP = 0) See figure 21 16P 11/ 19/ 23/ M24 Delay time, FSX low to CLKX low 24/ td(CKXL-FXL) T-1 T+3 M25 Delay time, FSX low to CLKX high 25/ td(FXL-CKXH) C-2 C+2 M26 Delay time, CLKX high to DX valid td(CKXH-DXV) -2 4 M27 Disable time, DX high impedance following last data bit from CLKX low tdis(CKXL- C-2 C M28 Disable time, DX high impedance following last data bit from FSX high M29 Delay time, FSX low to DX valid ns 3P+2 5P+8 tdis(FXH-DXHZ) 3P+8 3P+20 td(FXL-DXV) 3P-3 3P+20 DXHZ) See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 15 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted 1/ Limits Unit Master Min Slave Max Min Max McBSP as SPI MASTER OR SLAVE TIMING - Continued McBSP as SPI Master or Slave timing requirements (CLKSTP = 11b, CLKXP = 0) 11/ 23/ M39 Setup time, DR valid before CLKX high tsu(DRV-CKXH) M40 Hold time, DR valid after CLKX high th(CKXH-DRV) M41 Setup time, FSX low before CLKX high tsu(FXL-CKXH) M42 Cycle time, CLKX See figure 21 4 3-6P 1 1+6P ns 10 tc(CKX) 2P 16P McBSP as SPI Master or Slave switching characteristics (CLKSTP = 11b, CLKXP = 0) 11/ 19/ 23/ M34 Delay time, FSX low to CLKX low 24/ td(CKXL-FXL) C-1 C+3 M35 Delay time, FSX low to CLKX high 25/ td(FXL-CKXH) T-2 T+2 M36 Delay time, CLKX low to DX valid td(CKXL-DXV) -2 4 3P+2 5P+8 M37 Disable time, DX high impedance following last data bit from CLKX low tdis(CKXL- -2 0 3P+8 3P+21 D-2 D+10 3P-3 3P+21 M38 Delay time, FSX low to DX valid See figure 21 DXHZ) td(FXL-DXV) McBSP as SPI Master or Slave timing requirements (CLKSTP = 10b, CLKXP = 1) M49 Setup time, DR valid before CLKX high ns tsu(DRV-CKXH) M50 Hold time, DR valid after CLKX high th(CKXH-DRV) M51 Setup time, FSX low before CLKX low tsu(FXL-CKXL) M52 Cycle time, CLKX See figure 22 11/ 23/ 4 3-6P 1 1+6P ns 10 tc(CKX) 2P 16P McBSP as SPI Master or Slave switching characteristics (CLKSTP = 10b, CLKXP = 1) 11/ 19/ 23/ M43 Delay time, FSX low to CLKX high 24/ td(CKXH-FXL) T-1 T+3 M44 Delay time, FSX low to CLKX low 25/ td(FXL-CKXL) D-2 D+2 M45 Delay time, CLKX low to DX valid td(CKXL-DXV) -2 4 M46 Disable time, DX high impedance following last data bit from CLKX high tdis(CKXH- D-2 D M47 Disable time, DX high impedance following last data bit from FSX high M48 Delay time, FSX low to DX valid See figure 22 ns 3P+2 5P+8 tdis(FXH-DXHZ) 3P+8 3P+20 td(FXL-DXV) 3P-3 3P+20 DXHZ) See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 16 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted 1/ Limits Unit Master Min Slave Max Min Max McBSP as SPI MASTER OR SLAVE TIMING - Continued McBSP as SPI Master or Slave timing requirements (CLKSTP = 11b, CLKXP = 1) 11/ 23/ M58 Setup time, DR valid before CLKX low tsu(DRV-CKXL) M59 Hold time, DR valid after CLKX low th(CKXL-DRV) M60 Setup time, FSX low before CLKX low tsu(FXL-CKXL) M61 Cycle time, CLKX See figure 22 4 3-6P 1 1+6P ns 10 tc(CKX) 2P 16P McBSP as SPI Master or Slave switching characteristics (CLKSTP = 11b, CLKXP = 1) 11/ 19/ 23/ M53 Delay time, FSX low to CLKX high 24/ td(CKXH-FXL) D-1 D+3 M54 Delay time, FSX low to CLKX low 25/ td(FXL-CKXL) T-2 T+2 M55 Delay time, CLKX high to DX valid td(CKXH-DXV) -2 4 3P+2 5P+8 M56 Disable time, DX high impedance following last data bit from CLKX high tdis(CKXH- -2 0 3P+8 3P+21 Delay time, FSX low to DX valid td(FXL-DXV) C-2 C+10 3P-3 3P+21 M57 See figure 22 ns DXHZ) See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 17 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max ENHANCED HOST PORT INTERFACE (EHPI) TIMING EHPI timing requirements E11 Setup time, HAS low before HDS low tsu(HASL-HDSL) See figure 23-27 4 E12 Hold time, HAS low after HDS low th(HDSL-HASL) 3 E13 Setup time, (HR/ W , HA[19:0], tsu(HCNTLV-HDSL) 4 th(HDSL-HCNTLIV) 4 ns HCNTL[1:0]) valid before HDS low E14 Hold time, (HR/ W , HA[19:0], HCNTL[1:0]) invalid after HDS low E15 Pulse duration, HDS low tw(HDSL) 4P 11/ E16 Pulse duration, HDS high tw(HDSH) 4P 11/ E17 Setup time, HD bus write data valid before tsu(HDV-HDSH) 5 th(HDSH-HDIV) 3 tsu(HCNTLV-HASL) 5 th(HASL-HCNTLIV) 3 HDS high E18 Hold time, HD bus write data invalid after HDS high E19 Setup time, (HR/ W ,HCNTL[1:0]) valid before HAS low E20 Hold time, (HR/ W ,HCNTL[1:0]) valid after HAS low See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 18 TABLE I. Electrical performance characteristics - Continued. No. Test Symbol 1/ Test condition -40C TC +85C 1.55 V CVDD 1.65 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max 6 16 ENHANCED HOST PORT INTERFACE (EHPI) TIMING - Continued EHPI switching characteristics E1 Delay time, HDS low to HD bus read data driven (memory access) td(HDSL-HDD)M E2 Delay time, HDS low to HD bus read data valid (memory access) td(HDSL-HDV)M 14P+10 11/ 26/ E4 Delay time, HDS low to HD bus read data driven (register access) td(HDSL-HDD)R 6 E5 Delay time, HDS low to HD bus read data valid (register access) td(HDSL-HDV)R E6 Disable time, HDS high to HD bus read data invalid tdis(HDSH-HDIV) E7 Disable time, HDS low to HRDY low (during reads) td(HDSL-HRDYL) E8 Delay time, HD bus valid to HRDY high (during reads) td(HDV-HRDYH) E9 Disable time, HDS high to HRDY low (during writes) td(HDSH-HRDYL) E10 Disable time, HDS high to HRDY high (during writes) td(HDSH-HRDYH) See figure 23-27 ns 16 16 6 16 P+10 11/ 2 16 14P+10 11/ See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 19 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ 8/ 9/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Test conditions: CPU executing 75% Dual-MAC / 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN domains are active. All other domains are idled. The DPLL is enabled. Test conditions: One word of a table of 16 bit sine values is writtern to the EMIF each microsecond (16 Mbps). Each EMIF output pin is connected to a 10 pF load capacitance. This device utilizes a fully static design and therefore can operate with tc(CI) approaching . The device is characterized at frequencies approaching 0 Hz. M Clock frequency synthesis factor which is determined by: N = DL Where : M = the multiply factoir set in the PLL_MULT field of the clock mode register, DL = the divide factor set in the PLL_DIV field of the clock mode register Valid values for M are (multiply by) 2 to 31. Valid values for DL are (divide by) 1, 2, 3, and 4. For more detail information see manufacturer data. The clock frequency factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified range (tc(CO)). To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be asynchronous input. The minimum delay is also the minimum output hold after CLKOUT high. All timings referenced to CLKOUT assume CLKOUT represents the internal CPU clock (divide-by 1 mode). 10/ 11/ HOLD is synchronized internally. If the setup time shown not met, HOLD will be recognized on the next clock cycle. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. 12/ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. 13/ EMIF bus consists of CE[3 : 0] , BE[3 : 0] , D[31:0], A[21:0], ARE , AOE , AWE , SSADS , SSOE , SSWE , CLKMEM, 2/ 3/ 4/ 5/ 6/ 7/ SDA10, SDRAS , SDCAS , and SDWE . 14/ 15/ 16/ 17/ 18/ 19/ 20/ 21/ 22/ 23/ 24/ 25/ 26/ EMIF bus consists of CE[3 : 0] , BE[3 : 0] , CLKMEM, AOE , AWE , SSADS , SSOE , SSWE , SDRAS , SDCAS , SDWE , and SDA10. High group: HINT Low group: HOLDA Z group: A[21:0], D[31:0], CLKR[2:0], CLKX[2:0], FSR[2:0], FSX[2:0], DX[2:0], IO[7:0], XF, and TIN/TOUT[1:0]. For proper operation of the TIN/TOUT pin configured as an output, the time period must be configured for at least 4 cycles. Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. T = CLKRX period = (1+ CLKGDV)*P C = CLKLX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2)*P when CLKGDV is even D = CLKLX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1)*P when CLKGDV is even. See manufacturer for the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA) and data delay features of the McBSP. MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general purpose input. MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general purpose output. For all SPI slave modes, CLKG is programmed as ½ of the CPU clocks by setting CLKSM = CLKGDV = 1. FSRP = FSXP =1. As SPI master, FSX is inverted to provide active low slave enable output. As a slave, the active low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = FSXM = CLKRM = FSRM = 0 for slave McBSP. FSX should be low before the rising edge of clock to enable slave devices and then begin as SPI transfer at the rising edge of the master clock (CLKX). EHPI latency is dependent on the number of DMA channels active, their priorities and their source/destination ports. The latency shown assumes no competing CPU or DMA activity to the memory resource being accessed by the EHPI. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 20 Case X Millimeters Symbol Min Max A 1.40 A1 0.85 0.95 A2 0.35 0.45 b 0.45 0.55 D/E 14.90 15.10 D1/E1 12.80 Typ e 0.80 Typ Notes: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. FIGURE 1. Case outlines. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 21 PIN No. A1 PIN NAME VSS PIN No. B1 PIN NAME VSS PIN No. C1 PIN NAME A10 PIN No. D1 PIN NAME DVDD PIN No. E1 PIN NAME A11 A2 A9 B2 XF C2 D13 D2 D14 E2 D15 A3 DVDD B3 D9 C3 D10 D3 D11 E3 D12 A4 A8 B4 D7 C4 A6 D4 D8 E4 CE3 A5 CVDD B5 D5 C5 A7 D5 D6 E5 BOOTM3 A6 A4 B6 D3 C6 A5 D6 D4 E6 CVDD A7 DVDD B7 A2 C7 A3 D7 D1 E7 CVDD A8 D2 B8 A0 C8 D0 D8 A1 E8 NC A9 VSS B9 CLKMEM C9 HD4 D9 HD15 E9 NC A10 VSS B10 SDA10 C10 HD5 D10 HD14 E10 CVDD A11 SDRAS B11 HD2 C11 HD6 D11 HD13 E11 NC A12 DVDD B12 SDWE C12 HD7 D12 HD12 E12 NC A13 SDCAS B13 HD1 C13 HD8 D13 HD11 E13 RSVD9 A14 CVDD B14 HDRY C14 HD9 D14 HDS2 E14 HA12 A15 HD10 B15 HD3 C15 HR/ W D15 HA11 E15 HA10 A16 VSS B16 HD0 C16 HCS D16 HA0 E16 HA1/HCNTL1 A17 VSS B17 HDS1 C17 TRST D17 DVDD E17 RST_MODE F1 DVDD G1 CE2 H1 VSS J1 VSS K1 IO7 F2 A13 G2 A17 H2 CE1 J2 CE0 K2 BE0 F3 A12 G3 A15 H3 A19 J3 A21 K3 BE1 F4 A16 G4 A14 H4 A18 J4 A20 K4 IO0 F5 CVDD G5 NC H5 NC J5 NC K5 CVDD F13 RSVD8 G13 RSVD7 H13 RSVD6 J13 RSVD5 K13 RSVD4 F14 HA9 G14 HA8 H14 HA4 J14 HA5 K14 TMS F15 HA2/ HAS G15 HA3 H15 CLKOUT J15 HA15 K15 HBE0 F16 CLKIN G16 RESET H16 HA14 J16 HA7 K16 HA16 F17 CVDD G17 HA13 H17 VSS J17 VSS K17 HA6 FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 22 PIN No. N1 PIN NAME DVDD PIN No. P1 PIN NAME IO3/BOOTM2 PIN No. R1 PIN NAME CVDD PIN No. T1 PIN NAME D17 PIN No. U1 PIN NAME VSS N2 IO4 P2 CLKS1 R2 FSR1 T2 IO2/BOOTM1 U2 VSS N3 D16 P3 DR1 R3 D18 T3 CLKR1 U3 CLKR0 N4 SSADS P4 D19 R4 D20 T4 D21 U4 CVDD N5 NC P5 D22 R5 CLKR2 T5 FSR0 U5 CLKS0 N6 CVDD P6 D23 R6 FSR2 T6 DR0 U6 DVDD N7 NC P7 D24 R7 DR2 T7 D25 U7 CLKX0 N8 NC P8 CLKS2 R8 D26 T8 D27 U8 CLKX2 N9 NC P9 FSX0 R9 FSX2 T9 D29 U9 VSS N10 CVDD P10 D31 R10 DX0 T10 D30 U10 VSS N11 NC P11 D28 R11 INT 5 T11 NC U11 DX2 N12 NC P12 INT 4 R12 INT 0 T12 NMI U12 CVDD N13 RSVD1 P13 ARDY R13 INT2 T13 AWE U13 INT1 N14 HINT P14 HOLDA R14 ARE T14 INT 3 U14 DVDD N15 HCNTL0 P15 TIN/TOUT0 R15 CLKX1 T15 FSX1 U15 AOE N16 HMODE P16 CLKMD R16 EMU0 T16 DX1 U16 HOLD N17 HA19 P17 CVDD R17 TIN/TOUT1 T17 VSS U17 VSS L1 CVDD M1 IO5 L2 IO6 M2 SSWE L3 BE2 M3 SSOE L4 BE3 M4 IO1/BOOTM0 L5 NC M5 NC L13 RSVD3 M13 RSVD2 L14 EMU1/ OFF M14 HA18 L15 TDO M15 HA17 L16 TDI M16 HBE1 L17 TCK M17 DVDD FIGURE 2. Terminal connections - Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 23 FIGURE 3. Block diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 24 Where: IOL – test IOH – test VLoad CT = +2 mA (all outputs) = -2 mA (all outputs) = 50% of DVDD = 15 pF typical load circuit capacitance. FIGURE 4. Load circuit. Notes: 1. The relationship of CLKIN to CLKOUT depends on the device factor chosen. The waveform relationship shown above is intended to illustrate the timing parameters only and may differ based on configuration. FIGURE 5. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 25 Notes: 1. The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen. The waveform relationship shown above is intended to illustrate the timing parameters only and may differ based on configuration. FIGURE 6. Timing waveforms. Notes: 1. Setup, Strobe, Hold, and Extended Hold are programmable in the EMIF. The programmable HOLD period is not associated with 2. the activity of the HOLD and HOLDA signals. The extended hold time is programmable in the EMIF and is only present when consecutive memory accesses are made to 3. 4. 5. different CEx spaces, or are of different types (read/write). All timings referenced to CLKOUT assume CLKOUT is the same frequency as the internal CPU clock (divide-by 1 mode). The chip enable that becomes active depends on the address. ARDY is synchronized internally. If the setup time shown is not met, ARDY will be recognized on the next clock cycle. FIGURE 7. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 26 Notes: 1. Setup, Strobe, Hold, and Extended Hold are programmable in the EMIF. The programmable HOLD period is not associated with 2. the activity of the HOLD and HOLDA signals. The extended hold time is programmable in the EMIF and is only present when consecutive memory accesses are made to 3. 4. 5. different CEx spaces, or are of different types (read/write). All timings referenced to CLKOUT assume CLKOUT is the same frequency as the internal CPU clock (divide-by 1 mode). The chip enable that becomes active depends on the address. ARDY is synchronized internally. If the setup time shown is not met, ARDY will be recognized on the next clock cycle. FIGURE 8. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 27 Notes: 1. The chip enable that becomes active depends on the address. FIGURE 9. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 28 Notes: 1. The chip enable that becomes active depends on the address. 2. 3. All BE[3 : 0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain active until the next access that is not an SDRAM read occurs. The number of address signals used depends on the SDRAM size and width. FIGURE 10. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 29 Notes: 1. The chip enable that becomes active depends on the address. 2. The number of address signals used depends on the SDRAM size and width. FIGURE 11. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 30 Notes: 3. The chip enable that becomes active depends on the address. 4. The number of address signals used depends on the SDRAM size and width. FIGURE 12. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 31 Notes: 1. EMIF bus consists of CE[3 : 0] , BE[3 : 0] , D[31:0], A[21:0], ARE , AOE , AWE , SSADS , SSOE , SSWE , SDA10, SDRAS , SDCAS , SDWE , and CLKMEM. FIGURE 13. Timing waveforms. Notes: 1. EMIF group: CE[3 : 0] , BE[3 : 0] , CLKMEM, ARE , AOE , AWE , SSADS , SSOE , SSWE , SDRAS , SDCAS , SDWE , and SDA10. 2. High group: HINT 3. Low group: HOLDA Z group: A[21:0], D[31:0], CLKR[2:0], CLKX[2:0], FSR[2:0], DX[2:0], IO[7:0], XF, and TIN/TOUT[1:0]. FIGURE 14. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 32 FIGURE 15. Timing waveforms. FIGURE 16. Timing waveforms. FIGURE 17. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 33 FIGURE 18. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 34 FIGURE 19. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 35 Notes: 1. MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general purpose input. 2. MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx, when configured as a general purpose output. FIGURE 20. Timing waveforms. FIGURE 21. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 36 FIGURE 22. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 37 Notes: 1. As of revision 2.1, the byte enable function on the EHPI (as controlled by pins HBE0 and HBE1 ) is no longer supported. These pins must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry controlled by the HPE bit in the System Register (SYSR). 2. The falling edge of HCS must occur concurrent with or before the falling edge of HDS . The rising edge of HCS must occur concurrent with or after the rising edge of HDS . If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown of HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is high HRDY is not driven). FIGURE 23. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 38 Notes: 1. As of revision 2.1, the byte enable function on the EHPI (as controlled by pins HBE0 and HBE1 ) is no longer supported. These pins must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry controlled by the HPE bit in the System Register (SYSR). 2. The falling edge of HCS must occur concurrent with or before the falling edge of HDS . The rising edge of HCS must occur concurrent with or after the rising edge of HDS . If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown of HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is high HRDY is not driven). FIGURE 24. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 39 Notes: 1. 2. 3. As of revision 2.1, the byte enable function on the EHPI (as controlled by pins HBE0 and HBE1 ) is no longer supported. These pins must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry controlled by the HPE bit in the System Register (SYSR). During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host will always indicate the base address. The falling edge of HCS must occur concurrent with or before the falling edge of HDS . The rising edge of HCS must occur concurrent with or after the rising edge of HDS . If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown of HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is high HRDY is not driven). FIGURE 25. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 40 Notes: 1. 2. 3. As of revision 2.1, the byte enable function on the EHPI (as controlled by pins HBE0 and HBE1 ) is no longer supported. These pins must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry controlled by the HPE bit in the System Register (SYSR). During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host will always indicate the base address. The falling edge of HCS must occur concurrent with or before the falling edge of HDS . The rising edge of HCS must occur concurrent with or after the rising edge of HDS . If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown of HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is high HRDY is not driven). FIGURE 26. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 41 Notes: 1. 2. 3. As of revision 2.1, the byte enable function on the EHPI (as controlled by pins HBE0 and HBE1 ) is no longer supported. These pins must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry controlled by the HPE bit in the System Register (SYSR). During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host will always indicate the base address. The falling edge of HCS must occur concurrent with or before the falling edge of HDS . The rising edge of HCS must occur concurrent with or after the rising edge of HDS . If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown of HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is high HRDY is not driven). FIGURE 27. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/04605 PAGE 42 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. 1/ Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/04605-01XA 01295 SM32VC5510AGGWA2EP The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04605 PAGE 43