REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 53 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 REV PAGE REV STATUS OF PAGES REV PAGE PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing CHECKED BY Phu H. Nguyen YY MM DD 10-06-22 APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A CODE IDENT. NO. DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON DWG NO. V62/09647 16236 A PAGE 1 OF 53 5962-V065-10 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -55C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: - V62/09647 Drawing number 01 X A Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). 1/ Generic Device type 01 Circuit function SM320VC5507-EP Fixed Point Digital Signal Processor 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins Package style X 144 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage I/O range, (DVDD) ............................................................................................. Supply voltage core range, (CVDD) ........................................................................................... Input voltage range, (VI) ........................................................................................................... Output voltage range (VO) ....................................................................................................... Operating case temperature ranges, (TC): (Extended) ............................................................. Storage temperature range, (TSTG)............................................................................................ 1/ 2/ 3/ 4/ -0.3 V to +4.0 V -0.3 V to +2.0 V -0.3 V to +4.5 V -0.3 V to +4.5 V -55C to +85C -55C to +150C 4/ 4/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See manufacturer data for additional information on enhanced plastic packaging. All voltage values are with respect to VSS. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 2 1.4 Recommended operating conditions. 5/ For CVDD = 1.2 V (108 MHz) CORE Device supply voltage (CVDD) ............................................................................ +1.14 V to +1.26 V PERIPHERALS RTC module supply voltage, core (RCVDD) ........................................................ +1.14 V to +1.26 V RTC module supply voltage, I/O (RTCINX1 and RTCINX2), (RDVDD) ................ +1.14 V to +1.26 V USBPLL supply voltage, (USBPLLVDD) .............................................................. +1.14 V to +1.26 V 6/ USB module supply voltage, I/O (DP, DN, and PU), (USBVDD) .......................... +3.0 V to +3.6 V 7/ Device supply voltage, I/O (except DP, DN, PU, SDA, SCL), (DVDD) .................. +2.7 V to +3.6 V A/D module digital supply voltage, (ADVDD) ....................................................... +2.7 V to +3.6 V A/D module analog supply voltage, (AVDD) ......................................................... +2.7 V to +3.6 V GROUNDS Supply voltage, GND, I/O, and core (VSS) .......................................................... 0 V Supply voltage, GND, A/D module, digital (ADVSS) ............................................ 0 V Supply voltage, GND, A/D module, analog (AVSS) ............................................. 0 V Supply voltage, GND, USBPLL (USBPLLVSS) .................................................... 0 V High level input voltage, I/O (VIH): DN and DP .................................................................................................. +2 V minimum 8/ SDA and SCL: VDD related input level ......................................................... 0.7 x DVDD to DVDD (max) + 0.5 V 7/ All other inputs (including hysteresis inputs) ................................................ +2 V to DVDD +0.3 V Low level input voltage, I/O (VIL): DN and DP .................................................................................................. +0.8 V maximum 8/ SDA and SCL: VDD related input level ......................................................... -0.5 V to0.3 x DVDD 7/ All other inputs (including hysteresis inputs) ................................................ -0.3 V to +0.8 V Hysteresis level, (Vhys) – Inputs with hysteresis only .............................................. 0.1 x DVDD High level output current, (IOH): DN and DP (VOH = 2.45 V) .......................................................................... -17 mA max 8/ All other outputs .......................................................................................... - 4 mA max Low level output current, (IOL): DN and DP (VOL = 0.36 V) ........................................................................... 17mA min 8/ SDA and SCL .............................................................................................. 3 mA max All other outputs .......................................................................................... 4 mA max Operating case temperature (TC) ........................................................................... -55C to +85C __________ 5/ 6/ 7/ 8/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. USB PLL is susceptible to power supply ripple. The maximum allowable supply ripple is 1% for 1 Hz to 5 kHz; 1.5% for 5 kHz to 10 MHz; 3% for 10 MHz to 100 MHz , and less than 5% for 100 MHz or greater. The I2C pins SDA and SCL do not feature fail-safer I/O buffers. These pins could potentially draw current when the device is powered down. Due to the fact that different voltage devices can be connected to the I2C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and depends on the associated VDD. USB I/O pins DP and DN can tolerate a short circuit at D+ and D- to 0 V or 5 V, as long as the recommended series resistors (see Figure 40) are connected between the D+ and DP (package), and the D- and DN (package). Do not apply a short circuit to the USB I/O pins DP and DN in absence of the series resistors. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 3 1.4 Recommended operating conditions - Continued. For CVDD = 1.35 V (144 MHz) CORE Device supply voltage (CVDD) ............................................................................ +1.28 V to +1.42 V PERIPHERALS RTC module supply voltage, core (RCVDD) ........................................................ +1.28 V to +1.42 V RTC module supply voltage, I/O (RTCINX1 and RTCINX2), (RDVDD) ................ +1.28 V to +1.42 V USBPLL supply voltage, (USBPLLVDD) .............................................................. +1.28 V to +1.42 V 6/ USB module supply voltage, I/O (DP, DN, and PU), (USBVDD) .......................... +3.0 V to +3.6 V 7/ Device supply voltage, I/O (except DP, DN, PU, SDA, SCL), (DVDD) .................. +2.7 V to +3.6 V A/D module digital supply voltage, (ADVDD) ....................................................... +2.7 V to +3.6 V A/D module analog supply voltage, (AVDD) ......................................................... +2.7 V to +3.6 V GROUNDS Supply voltage, GND, I/O, and core (VSS) .......................................................... 0 V Supply voltage, GND, A/D module, digital (ADVSS) ............................................ 0 V Supply voltage, GND, A/D module, analog (AVSS) ............................................. 0 V Supply voltage, GND, USBPLL (USBPLLVSS) .................................................... 0 V High level input voltage, I/O (VIH): DN and DP .................................................................................................. +2 V minimum 8/ SDA and SCL: VDD related input level ......................................................... 0.7 x DVDD to DVDD (max) + 0.5 V 7/ All other inputs (including hysteresis inputs) ................................................ +2 V to DVDD +0.3 V Low level input voltage, I/O (VIL): DN and DP .................................................................................................. +0.8 V maximum 8/ SDA and SCL: VDD related input level ......................................................... -0.5 V to0.3 x DVDD 7/ All other inputs (including hysteresis inputs) ................................................ -0.3 V to +0.8 V Hysteresis level, (Vhys) – Inputs with hysteresis only .............................................. 0.1 x DVDD High level output current, (IOH): DN and DP (VOH = 2.45 V) .......................................................................... -17 mA max 8/ All other outputs .......................................................................................... - 4 mA max Low level output current, (IOL): DN and DP (VOL = 0.36 V) ........................................................................... 17mA min 8/ SDA and SCL .............................................................................................. 3 mA max All other outputs .......................................................................................... 4 mA max Operating case temperature (TC) ........................................................................... -55C to +85C DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 4 1.4 Recommended operating conditions - Continued. For CVDD = 1.6 V (200 MHz) CORE Device supply voltage (CVDD) ............................................................................ +1.55 V to +1.65 V PERIPHERALS RTC module supply voltage, core (RCVDD) ........................................................ +1.55 V to +1.65 V RTC module supply voltage, I/O (RTCINX1 and RTCINX2), (RDVDD) ................ +1.55 V to +1.65 V USBPLL supply voltage, (USBPLLVDD) .............................................................. +1.55 V to +1.65 V 6/ USB module supply voltage, I/O (DP, DN, and PU), (USBVDD) .......................... +3.0 V to +3.6 V Device supply voltage, I/O (except DP, DN, PU, SDA, SCL), (DVDD) .................. +2.7 V to +3.6 V 7/ A/D module digital supply voltage, (ADVDD) ....................................................... +2.7 V to +3.6 V A/D module analog supply voltage, (AVDD) ......................................................... +2.7 V to +3.6 V GROUNDS Supply voltage, GND, I/O, and core (VSS) .......................................................... 0 V Supply voltage, GND, A/D module, digital (ADVSS) ............................................ 0 V Supply voltage, GND, A/D module, analog (AVSS) ............................................. 0 V Supply voltage, GND, USBPLL (USBPLLVSS) .................................................... 0 V High level input voltage, I/O (VIH): DN and DP .................................................................................................. +2 V minimum 8/ SDA and SCL: VDD related input level ......................................................... 0.7 x DVDD to DVDD (max) + 0.5 V 7/ All other inputs (including hysteresis inputs) ................................................ +2 V to DVDD +0.3 V Low level input voltage, I/O (VIL): DN and DP .................................................................................................. +0.8 V maximum 8/ SDA and SCL: VDD related input level ......................................................... -0.5 V to0.3 x DVDD 7/ All other inputs (including hysteresis inputs) ................................................ -0.3 V to +0.8 V Hysteresis level, (Vhys) – Inputs with hysteresis only .............................................. 0.1 x DVDD High level output current, (IOH): DN and DP (VOH = 2.45 V) .......................................................................... -17 mA max 8/ All other outputs .......................................................................................... - 4 mA max Low level output current, (IOL): DN and DP (VOL = 0.36 V) ........................................................................... 17mA min 8/ SDA and SCL .............................................................................................. 3 mA max All other outputs .......................................................................................... 4 mA max Operating case temperature (TC) ........................................................................... -55C to +85C Thermal resistance characteristics (ambient temperature) Package RθJA(C/W) 71.2 61.8 Case outline X 58.9 54.8 103.6 84.2 77.8 69.4 Thermal resistance characteristics (Case temperature) Package RθJA(C/W) Case outline X 13.8 9/ Board type 9/ High - K High - K High - K High - K Low - K Low - K Low - K Low - K Air flow (LFM) 0 150 250 500 0 150 250 500 Board type 9/ 2s JEDEC test card Board types are defined by JEDEC. Reference JEDEC standard JESD51-9. test board are array surface mount package. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 5 2. APPLICABLE DOCUMENTS JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2 3.5.3 Functional block diagram. The functional block diagram shall be as specified in figure 3. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figure 4-40. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 6 TABLE I. Electrical performance characteristics. Test High level output voltage Low level output voltage Input current for outputs in highimpedance Input current DN and DP 3/ PU SDA & SCL 4/ DN and DP 3/ All other outputs Output-only or I/O pins with bus keepers (enabled) All other outputonly or I/O pins Input pins with internal pulldown (enabled) Input pins with internal pullup (enabled) X2/CLKIN All other inputonly pins DVDD supply current, pins active 6/ DVDD supply current, standby VOH All other outputs Input capacitance Output capacitance For CVDD = 1.2 V (108 MHz) CVDD supply current, CPU + internal memory access 5/ CVDD supply current, standby 7/ Symbol Oscillator disabled. All domains in low – power state Oscillator disabled. All domains in low – power state VOL IIZ II Test condition 2/ USBDVDD = 3.0 V to 3.6 V IOH = -300 µA DVDD = 2.7 V to 3.6 V IOH = -300 µA At 3 mA sink current IOL = 3.0 mA IOL = MAX CVDD -= 1.2 V (108 MHz) Min Max 2.8 USBVDD 0.9 x USBVDD USBVDD 0.75 x DVDD 0 0.4 0.3 0.4 -300 300 1/ Unit Limits CVDD -= 1.35 V CVDD -= 1.6 V (144 MHz) (200 MHz) Min Max Min Max 2.8 USBVDD 2.8 USBVDD 0.9 x USBVDD 0.9 x USBVDD USBVDD USBVDD 0.75 x 0.75 x DVDD DVDD 0 0.4 0 0.4 0.3 0.3 0.4 0.4 -300 300 -300 300 V V µA DVDD = MAX, VO = VSS to DVDD DVDD = MAX, VI = VSS to DVDD CI CO -5 5 -5 5 -5 5 30 300 30 300 30 300 -300 -30 -300 -30 -300 -30 -50 -5 50 5 -50 -5 50 5 -50 -5 50 5 3 TYP 3 TYP 3 TYP 3 TYP µA 3 TYP 3 TYP pF pF IDDC CVDD = 1.2 V, TC = 25C CPU clock = 108 MHz 0.45 TYP mA/ MHz IDDP DVDD = 3.3 V, TC = 25C CPU clock = 108 MHz 5.5 TYP mA IDDC CVDD = 1.2 V, TC = 25C (Nominal process) 100 TYP µA IDDP DVDD = 3.3 V, TC = 25C No I/O activity 10 TYP µA See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 7 TABLE I. Electrical performance characteristics - Continued. Test For CVDD = 1.35 V (144 MHz) CVDD supply current, CPU + internal memory access 5/ Symbol Test condition 2/ CVDD -= 1.2 V (108 MHz) Min Max 1/ Limits CVDD -= 1.35 V (144 MHz) Min Max Unit CVDD -= 1.6 V (200 MHz) Min Max IDDC CVDD = 1.35 V, TC = 25C CPU clock = 144 MHz 0.51 TYP mA/ MHz DVDD supply current, pins active 6/ IDDP DVDD = 3.3 V, TC = 25C CPU clock = 144 MHz 5.5 TYP mA Oscillator disabled. All domains in low – power state DVDD supply Oscillator current, disabled. All standby domains in low – power state For CVDD = 1.6 V (200 MHz) CVDD supply current, CPU + internal memory access 5/ IDDC CVDD = 1.35 V, TC = 25C (Nominal process) 125 TYP µA IDDP DVDD = 3.3 V, TC = 25C No I/O activity 10 TYP µA IDDC CVDD = 1.6 V, TC = 25C CPU clock = 200 MHz 0.6 TYP mA/ MHz DVDD supply current, pins active 6/ IDDP DVDD = 3.3 V, TC = 25C CPU clock = 200 MHz 5.5 TYP mA IDDC CVDD = 1.6 V, TC = 25C (Nominal process) 150 TYP µA IDDP DVDD = 3.3 V, TC = 25C No I/O activity 10 TYP µA CVDD supply current, standby 7/ CVDD supply current, standby 7/ DVDD supply current, standby Oscillator disabled. All domains in low – power state Oscillator disabled. All domains in low – power state See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 8 TABLE I. Electrical performance characteristics - Continued. No Test Symbol 1/ Limits Test condition 2/ CVDD= 1.2 V CVDD = 1.35 V Min Max CLOCK GENERATION IN BYPASS MODE (DPLL DISABLED) CLKIN timing requirements C1 Cycle time, X2/CLKIN tc(CI) See figure 4 20 400 8/ C2 Fall time, X2/CLKIN tf(CI) 4 C3 Rise time, X2/CLKIN tr(CI) 4 C10 Pulse duration CLKIN low tw(CIL) 6 C11 Pulse duration CLKIN high tw(CIH) 6 CLKOUT switching characteristics C4 Cycle time, CLKOUT tc(CO) 20 9/ 1600 10/ C5 Delay time, X2/CLKIN high to td(CI-CO) 5 25 CLKOUT high/low C6 Fall time, CLKOUT tf(CO) 1 TYP C7 Rise time, CLKOUT tr(CO) 1 TYP C8 Pulse duration CLKOUT low tw(COL) H-1 H+1 C9 Pulse duration CLKOUT high tw(COH) H-1 H+1 CLOCK GENERATION IN LOCK MODE (DPLL SYNTHESIS ENABLED) CLKIN timing requirements C1 Cycle time, X2/CLKIN tc(CI) DPLL synthesis enabled 20 400 8/ C2 Fall time, X2/CLKIN tf(CI) 4 C3 Rise time, X2/CLKIN tr(CI) 4 C10 Pulse duration CLKIN low tw(CIL) 6 C11 Pulse duration CLKIN high tw(CIH) 6 Multiply by N clock operation switching characteristics See figure 5 C4 Cycle time, CLKOUT tc(CO) for CVDD = 1.2 V 9.26 1600 C4 Cycle time, CLKOUT tc(CO) for CVDD = 1.35 V 6.95 1600 C6 Fall time, CLKOUT tf(CO) 1 TYP C7 Rise time, CLKOUT tr(CO) 1 TYP C8 Pulse duration CLKOUT low tw(COL) H-1 H+1 C9 Pulse duration CLKOUT high tw(COH) H-1 H+1 C12 Delay time, X2/CLKIN high to td(CI-CO) 5 25 CLKOUT high/low No Test Symbol Test condition 2/ REAL TIME CLOCK OSCILLATOR WITH EXTERNAL CRYSTAL Recommended RTC crystal parameters Frequency of oscillation 11/ fo See figure 6 Series resistance 11/ ESR Load capacitance CL Crystal drive level DL Unit CVDD = 1.6 V Min Max 20 400 8/ 4 4 ns 1600 8/ 25 ns 6 6 20 9/ 5 1 TYP 1 TYP H-1 H+1 H-1 H+1 20 400 8/ 4 4 ns 6 6 5 5 1600 1600 1 TYP 1 TYP H-1 H+1 H-1 H+1 5 25 Limits Min ns Unit Max 32.768 30 60 12.5 TYP 1 kHz kΩ pF µW See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 9 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 2/ ASYNCHRONUOS MEMORY TIMINGS Asynchronous memory cycle timing requirements M1 Setup time, read data valid before CLKOUT high 12/ tsu(DV-COH) See figure 7 and 8 M2 Hold time, read data after CLKOUT high th(COH-DV) M3 Setup time, ARDY valid before CLKOUT high 12/ tsu(ARDY-COH) M4 Hold time, ARDY after CLKOUT high th(COH-ARDY) Asynchronous memory cycle switching characteristics M5 See figure 7 td(COH-CEV) Delay time, CLKOUT high to CEx valid and 8 M6 td(COH-CEIV) Delay time, CLKOUT high to CEx invalid td(COHM7 Delay time, CLKOUT high to BEx valid td(COHM8 Delay time, CLKOUT high to BEx invalid M9 Delay time, CLKOUT high to address valid td(COHM10 Delay time, CLKOUT high to address invalid td(COHM11 Delay time, CLKOUT high to AOE valid td(COHM12 Delay time, CLKOUT high to AOE invalid td(COHM13 Delay time, CLKOUT high to ARE valid td(COHM14 Delay time, CLKOUT high to ARE invalid td(COHM15 Delay time, CLKOUT high to data valid td(COHM16 Delay time, CLKOUT high to data invalid td(COHM17 Delay time, CLKOUT high to AWE valid td(COHM18 Delay time, CLKOUT high to AWE invalid td(COH- 1/ Limits CVDD= 1.2 V CVDD = 1.6 V CVDD = 1.35 V Min Max Min Max 6 0 10 0 -2 -2 5 0 7 0 4 4 4 -2 ns -2 -2 4 4 4 -2 -2 -2 ns -2 4 -2 -2 -2 -2 -2 Unit 4 4 4 4 4 4 4 4 -2 -2 -2 -2 -2 4 4 4 4 4 -2 -2 -2 4 4 See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 10 TABLE I. Electrical performance characteristics - Continued. No Symbol Test Test condition 2/ SYNCHRONOUS DRAM (SDRAM) TIMINGS Synchronous DRAM cycle timing requirements M19 Setup time, read data valid before CLKMEN high tsu(DV-CLKMENH) See figure 9-15 M20 Hold time, read data valid after CLKMEN high th(CLKMENH-DV) M21 Cycle time, CLKMEN tc(CLKMEN) Synchronous DRAM cycle switching characteristics M22 Delay time, CLKMEM high to CEx low M23 Delay time, CLKMEM high to CEx high M24 Delay time, CLKMEM high to BEx valid M25 Delay time, CLKMEM high to HBEx invalid M26 Delay time, CLKMEM high to address valid M27 Delay time, CLKMEM high to address invalid M28 Delay time, CLKMEM high to SDCAS low M29 Delay time, CLKMEM high to SDCAS high M30 Delay time, CLKMEM high to data valid M31 Delay time, CLKMEM high to data invalid M32 Delay time, CLKMEM high to SDWE low M33 Delay time, CLKMEM high to SDWE high M34 Delay time, CLKMEM high to SDA10 valid M35 Delay time, CLKMEM high to SDA10 invalid M36 Delay time, CLKMEM high to SDRAS low M37 Delay time, CLKMEM high to SDRAS high M38 Delay time, CLKMEM high to CKE low M39 Delay time, CLKMEM high to CKE high td(CLKMEMH-CEL) td(CLKMEMH-CEH) td(CLKMEMH-BEV) td(CLKMEMH-BEIV) td(CLKMEMH-AV) td(CLKMEMH-AIV) See figure 9-15 td(CLKMEMH-SDCASL) td(CLKMEMH-SDCAH) td(CLKMEMH-DV) td(CLKMEMH-DIV) td(CLKMEMH-SDWEL) td(CLKMEMH-SDWEH) td(CLKMEMH-SDA10V) td(CLKMEMH-SDA10IV) td(CLKMEMH-SDRASL) td(CLKMEMH-SDRASH) td(CLKMEMH-CKEL) td(CLKMEMH-CKEH) 1/ Limits CVDD= 1.2 V CVDD = 1.6 CVDD = 1.35 V V Min Max Min Max 3 2 9.26 13/ 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 Unit 3 2 7.52 13/ 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 ns 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 ns See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 11 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 2/ 1/ Limits CVDD= 1.2 V CVDD = 1.35 V Min Max POWER UP RESET (ON CHIP OSCILLATOR ACTIVE) Timing requirements th(SUPSTBL-RSTL) R1 Hold time, RESET low after oscillator stable See figure 16 3P 15/ 16/ POWER UP RESET (ON CHIP OSCILLATOR INACTIVE) Timing requirements R2 Hold time, CLKOUT valid to RESET low See figure 16 3P 15/ th(CLKOUTV-RSTL) Switching characteristics R3 Delay time, CLKIN valid to CLKOUT valid td(CLKINV-CLKOUTV) See figure 16 30 WARM RESET Reset timing requirements R4 Pulse width, reset low tw(RSL) See figure 53P 15/ Reset switching characteristics 15/ R5 Delay time, reset high to BK group valid 17/ td(RSTH-BKV) See figure 18 38P+15 R6 Delay time, reset high to High group valid 18/ td(RSTH-HIGHV) 38P+15 R7 Delay time, reset low to Z group valid 19/ td(RSTL-ZIV) 1P+15 R8 Delay time, reset high to Z group valid 19/ td(RSTH-ZV) 38P+15 EXTERNAL INTERRUP TIMING External interrupt timing requirements 15/ I1 Pulse width, interrupt high, CPU active tw(INTH)A See figure 19 2P I2 Pulse width, interrupt low, CPU active tw(INTL)A 3P WAKE UP FROM IDLE Wake up from IDLE switching characteristics 15/ td(WKPEVTL-CLKGEN) See figure 20 ID1 Delay time, wake up event low to clock 1.25 TYP generation enable 20/ (CPU and clock domain idle) ID2 Hold time, clock generation enable to wake up td(CLKGEN-WKPEVTL) 3P event low 21/ (CPU and clock domain in idle) ID3 Pulse width, wake up event low tw(WKPEVTL) 3P (for CPU idle only) Unit CVDD = 1.6 V Min Max 3P 15/ ns 3P 15/ 30 ns 3P 15/ ns 38P+15 38P+15 1P+15 38P+15 2P 3P ns ns 1.25 TYP 20/ ns 3P 21/ 3P See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 12 TABLE I. Electrical performance characteristics – Continued. No Test Symbol Test condition 2/ 1/ Limits CVDD= 1.2 V CVDD = 1.6 CVDD = 1.35 V V Min Max Min Max XF TIMINGS XF switching characteristics X1 Delay time, CLKOUT high to XF high td(XF) See figure 21 -1 Delay time, CLKOUT high to XF high -1 GENERAL PURPOSE INPUT/OUTPUT (GPIOx) TIMINGS GPIO pins configured as Inputs timing requirements See figure 22 4 G1 Setup time, IOx input valid GPIO tsu(GPIO-COH) AGPIO 22/ 8 before CLKOUT high EHPIGPIO 23/ 8 0 GPIO G2 Hold time, IOx input valid th(COH-GPIO) AGPIO 22/ 0 after CLKOUT high EHPIGPIO 23/ 0 GPIO configured as outputs switching characteristics See figure 22 0 G3 Delay time, CLKOUT high GPIO td(COH-GPIO) AGPIO 22/ 0 to IOx output change EHPIGPIO 23/ 0 TIN/TOUT TIMINGS (TIMER0 ONLY) TIN/TOUT pins configured as inputs timing requirements 15/ 24/ T4 Pulse width, TIN/TOUT low tw(TIN/TOUTL) See figure 23 2P+1 T5 Pulse width, TIN/TOUT high tw(TIN/TOUTH) 2P+1 TIN/TOUT pins configured as outputs switching characteristics 15/ 24/ 25/ T1 Delay time, CLKOUT high to TIN/TOUT high td(COH-TIN/TOUTH) See figure 23 -1 T2 Delay time, CLKOUT high to TIN/TOUT low td(COH-TIN/TOUTL) -1 T3 Pulse duration, TIN/TOUT (output) tw(TIN/TOUT) P-1 3 3 -1 -1 3 3 4 8 8 0 0 0 6 11 13 ns ns 0 0 0 6 11 13 2P+1 2P+1 3 3 Unit -1 -1 P-1 ns ns 3 3 ns See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 13 TABLE I. Electrical performance characteristics – Continued. No Test Symbol Test condition 2/ McBSP0 TIMINGS McBSP0 timing requirements 26/ See figure 24 and 25 MC1 Cycle time, CLKR/X tc(CKRX) CLKR/X ext MC2 Pulse duration, CLKR/X high or CLKR/X tw(CKRX) CLKR/X ext low MC3 Rise time, CLKR/X tr(CKRX) CLKR/X ext MC4 Fall time CLKR/X tf(CKRX) CLKR/X ext MC5 Setup time, external FSR high before tsu(FRH-CKRL) CLKR int CLKR low CLKR ext MC6 Hold time, external FSR high after CLKR th(CKRL-FRH) CLKR int low CLKR ext MC7 Setup time, DR valid before CLKR low tsu(DRV-CKRL) CLKR int CLKR ext MC8 Hold time, DR valid after CLKR low th(CKRL-DRV) CLKR int CLKR ext MC9 Setup time, external FSX high before tsu(FXH-CKXL) CLKR int CLKX low CLKR ext MC10 Hold time, external FSX high after CLKX th(CKXL-FXH) CLKR int low CLKR ext 1/ Limits CVDD= 1.2 V CVDD = 1.35 V Min Max 2P 15/ P-1 15/ Unit CVDD = 1.6 V Min Max 2P 15/ P-1 15/ ns 6 6 10 2 -3 1 10 2 -2 3 13 3 -3 1 6 6 7 2 -3 1 7 2 -2 3 8 2 -3 1 See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 14 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 2/ McBSP0 TIMINGS - Continued McPSP0 switching characteristics 15/ 26/ See figure 24 and 25 MC1 Cycle time, CLKR/X tc(CKRX) CLKR/X int MC3 Rise time, CLKR/X tr(CKRX) CLKR/X int MC4 Fall time CLKR/X tf(CKRX) CLKR/X int MC11 Pulse duration, CLKR/X high tw(CKRXH) CLKR/X int MC12 Pulse duration, CLKR/X low tw(CKRXL) CLKR/X int MC13 Delay time, CLKR high to internal FSR valid td(CKRHCLKR int FRV) CLKR ext MC14 Delay time, CLKR high to internal FSX valid td(CKXHCLKR int FXV) CLKR ext CLKR int MC15 Disable time, DX high impedance from CLKX tdis(CKXHhigh following last data bit DXHZ) CLKR ext CLKR int Delay time, CLKX high to DX valid. This MC16 applies to all bits except the first bit transmitted. td(CKXHCLKR ext DXV) Delay time, CLKX high to DX DXENA = 0 CLKR int valid 28/ CLKR ext Only applies to first bit CLKR int transmitted when in Data Delay DXENA = 1 CLKR ext 1 or 2 (XDATDLY = 01b or 10b) modes CLKR int Enable time, DX driven from DXENA = 0 MC17 CLKX high 28/ ten(CKXHCLKR ext DX) Only applies to first bit CLKR int transmitted when in Data Delay DXENA = 1 CLKR ext 1 or 2 (XDATDLY = 01b or 10b) modes Delay time, FSX high to DX DXENA = 0 CLKR int MC18 valid 28/ td(FXH-DXV) CLKR ext CLKR int Only applies to first bit transmitted when in Data Delay DXENA = 1 CLKR ext 0 (XDATDLY = 00b) mode Enable time, DX driven from DXENA = 0 CLKR int MC19 FSX high 28/ ten(FXH-DX) CLKR ext Only applies to first bit CLKR int transmitted when in Data Delay DXENA = 1 CLKR ext 0 (XDATDLY = 00b) mode 1/ Limits Unit CVDD= 1.2 V CVDD = 1.35 V Min Max Min 2P 2P D-2 27/ C-2 27/ -2 4 -2 4 0 10 1 1 D+2 27/ C+2 27/ 1 13 2 15 5 18 5 15 4 13 2P+1 2P+4 CVDD = 1.6 V Max ns D-1 27/ C-1 27/ -2 4 -2 4 -5 3 -1 6 P-1 P+6 1 1 1 D+1 27/ C+1 27/ 1 8 2 9 1 11 4 9 2 7 2P+1 2P+3 -3 3 P-3 P+3 2 13 2P+1 2P+10 0 8 P-3 P+8 2 8 2P+1 2P+10 0 3 P-3 P+4 See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 15 TABLE I. Electrical performance characteristics – Continued. No Test Symbol Test condition 2/ 1/ Limits CVDD= 1.2 V CVDD = 1.35 V Min Max McBSP1 AND McBSP2 TIMINGS McBSP1 and McBSP2 timing requirements 26/ See figure 24 and 25 MC1 Cycle time, CLKR/X tc(CKRX) CLKR/X ext 2P 15/ MC2 Pulse duration, CLKR/X high or CLKR/X tw(CKRX) CLKR/X ext P-1 15/ low MC3 Rise time, CLKR/X tr(CKRX) CLKR/X ext MC4 Fall time CLKR/X tf(CKRX) CLKR/X ext MC5 Setup time, external FSR high before tsu(FRH-CKRL) CLKR int 11 CLKR low CLKR ext 3 MC6 Hold time, external FSR high after CLKR th(CKRL-FRH) CLKR int -3 low CLKR ext 1 MC7 Setup time, DR valid before CLKR low tsu(DRV-CKRL) CLKR int 11 CLKR ext 3 MC8 Hold time, DR valid after CLKR low th(CKRL-DRV) CLKR int -2 CLKR ext 3 MC9 Setup time, external FSX high before tsu(FXH-CKXL) CLKR int 14 CLKX low CLKR ext 4 MC10 Hold time, external FSX high after CLKX th(CKXL-FXH) CLKR int -3 low CLKR ext 1 Unit CVDD = 1.6 V Min Max 2P 15/ P-1 15/ ns 6 6 6 6 7 3 -3 1 7 3 -2 3 9 3 -3 1 See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 16 TABLE I. Electrical performance characteristics - Continued. No Test Symbol 1/ Limits Test condition 2/ CVDD= 1.2 V CVDD = 1.35 V Min Max McBSP1 AND McBSP2 TIMINGS - Continued McPSP1 and McBSP2 switching characteristics 15/ 26/ See figure 24 and 25 MC1 Cycle time, CLKR/X tc(CKRX) CLKR/X int 2P MC3 Rise time, CLKR/X tr(CKRX) CLKR/X int 2 MC4 Fall time CLKR/X tf(CKRX) CLKR/X int 2 MC11 Pulse duration, CLKR/X high tw(CKRXH) CLKR/X int D-2 27/ D+2 27/ MC12 Pulse duration, CLKR/X low tw(CKRXL) CLKR/X int C-2 27/ C+2 27/ MC13 Delay time, CLKR high to internal FSR valid td(CKRHCLKR int -3 2 FRV) CLKR ext 3 14 MC14 Delay time, CLKR high to internal FSX valid td(CKXHCLKR int -3 2 FXV) CLKR ext 4 15 CLKR int -3 3 MC15 Disable time, DX high impedance from CLKX tdis(CKXHhigh following last data bit DXHZ) CLKR ext 10 19 CLKR int 5 Delay time, CLKX high to DX valid. This MC16 applies to all bits except the first bit transmitted. td(CKXHCLKR ext 15 DXV) Delay time, CLKX high to DX DXENA = 0 CLKR int 4 valid 28/ CLKR ext 15 Only applies to first bit CLKR int 2P+1 transmitted when in Data Delay DXENA = 1 CLKR ext 2P+5 1 or 2 (XDATDLY = 01b or 10b) modes CLKR int -2 Enable time, DX driven from DXENA = 0 MC17 CLKX high 28/ ten(CKXHCLKR ext 9 DX) Only applies to first bit CLKR int P-2 transmitted when in Data Delay DXENA = 1 CLKR ext P+9 1 or 2 (XDATDLY = 01b or 10b) modes Delay time, FSX high to DX DXENA = 0 CLKR int 3 MC18 valid 28/ td(FXH-DXV) CLKR ext 13 CLKR int 2P+1 Only applies to first bit transmitted when in Data Delay DXENA = 1 CLKR ext 2P+12 0 (XDATDLY = 00b) mode Enable time, DX driven from DXENA = 0 CLKR int 1 MC19 FSX high 28/ ten(FXH-DX) CLKR ext 8 Only applies to first bit CLKR int P-1 transmitted when in Data Delay DXENA = 1 CLKR ext P+8 0 (XDATDLY = 00b) mode Unit CVDD = 1.6 V Min Max 2P ns D-2 27/ C-2 27/ -3 3 -3 4 -5 3 2 2 D+2 27/ C+2 27/ 2 9 2 9 1 12 3 9 2 9 2P+1 2P+3 -4 4 P-4 P+4 2 8 2P+1 2P+7 0 4 P-3 P+5 See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 17 TABLE I. Electrical performance characteristics – Continued. No Test Symbol 1/ Limits Test condition 2/ Unit CVDD= 1.2 V CVDD = 1.6 V CVDD = 1.35 V Master Slave Master Slave Min Max Min Max Min Max Min Max McBSP AS SPI MASTER OR SLAVE TIMINGS McBSP as SPI Master or Slave timing requirements (CLKSTP = 10b, CLKXP = 0) 15/ 29/ See figure 26-29 MC23 Setup time, DR valid before CLKX high tsu(DRV-CKXL) 15 3-6P 10 3-6P MC24 Hold time, DR valid after CLKX high th(CKXL-DRV) MC25 Setup time, FSX low before CLKX low tsu(FXL-CKXH) MC26 Cycle time, CLKX tc(CKX) 0 3+6P 2P 16P 0 3+6P 2P 16P 5 5 McBSP as SPI Master or Slave switching characteristics (CLKSTP = 10b, CLKXP =0) 15/ 29/ See figure 26-29 MC27 Delay time, CLKX low to FSX low 31/ T-5 T+5 T-5 T+5 td(CKXL-FXL) MC28 Delay time, FSX low to CLKX high 32/ td(FXL-CKXH) MC29 Delay time, CLKX high to DX valid C-5 C+5 td(CKXH-DXV) -4 6 MC30 Disable time, DX high impedance following last data bit from CLKX low tdis(CKXL- C-4 C+4 MC31 Disable time, DX high impedance following last data bit from FSX high tdis(FXH- MC32 Delay time, FSX low to DX valid C-5 3P+3 ns 5P+15 ns C+5 -3 3 C-3 C+1 3P+3 5P+8 DXHZ) 3P+4 3P+19 3P+3 3P+11 3P+4 3P+18 3P+4 3P+10 DXHZ) td(FXL-DXV) McBSP as SPI Master or Slave timing requirements (CLKSTP = 11b, CLKXP = 0) 15/ 29/ 15 3-6P MC33 Setup time, DR valid before CLKX high tsu(DRV- See figure 26-29 10 3-6P ns CKXH) MC34 Hold time, DR valid after CLKX high th(cKXH-DRV) MC25 Setup time, FSX low before CLKX high tsu(FXL-CKXH) MC26 Cycle time, CLKX tc(CKX) 0 3+6P 0 3+6P 5 2P 5 16P 2P 16P McBSP as SPI Master or Slave switching characteristics (CLKSTP = 11b, CLKXP =0) 15/ 29/ See figure 26-29 MC27 Delay time, CLKX low to FSX low 31/ C-5 C+5 C-4 C+4 td(CKXL-FXL) MC28 Delay time, FSX low to CLKX high 32/ td(FXL-CKXH) T-5 T+5 MC35 Delay time, CLKX high to DX valid td(CKXL-DXV) -4 6 3P+3 MC30 Disable time, DX high impedance following last data bit from CLKX low tdis(CKXL- -4 4 MC32 Delay time, FSX low to DX valid td(FXL-DXV) D-4 D+4 ns T-4 T+4 5P+15 -3 3 3P+3 3P+4 3P+19 -3 1 3P+3 3P+12 3P+4 3P+18 D-3 D+3 3P+4 3P+10 5P+8 DXHZ) See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 18 TABLE I. Electrical performance characteristics – Continued. No Test Symbol 1/ Limits Test condition 2/ Unit CVDD= 1.2 V CVDD = 1.6 V CVDD = 1.35 V Master Slave Master Slave Min Max Min Max Min Max Min Max McBSP AS SPI MASTER OR SLAVE TIMINGS - Continued McBSP as SPI Master or Slave timing requirements (CLKSTP = 10b, CLKXP = 1) 15/ 29/ See figure 26-29 15 3-6P 10 3-6P MC33 Setup time, DR valid before CLKX high tsu(DRV- ns CKXH) MC34 Hold time, DR valid after CLKX high th(CKXH-DRV) MC35 Setup time, FSX low before CLKX low tsu(FXL-CKXL) MC26 Cycle time, CLKX tc(CKX) 0 3+6P 0 3+6P 5 2P 5 16P 2P 16P McBSP as SPI Master or Slave switching characteristics (CLKSTP = 10b, CLKXP =1) 15/ 29/ See figure 26-29 MC37 Delay time, CLKX high to FSX low 31/ T-5 T+5 T-4 T+4 td(CKXH-FXL) MC38 Delay time, FSX low to CLKX low 32/ MC39 Delay time, CLKX low to DX valid td(FXL-CKXL) D-5 D+5 td(CKXL-DXV) -4 6 MC30 Disable time, DX high impedance following last data bit from CLKX high tdis(CKXH- D-4 D+4 MC31 Disable time, DX high impedance following last data bit from FSX high tdis(FXH- MC32 Delay time, FSX low to DX valid 3P+3 5P+15 D-4 D+4 -3 3 D-3 D+1 ns 3P+3 DXHZ) 3P+4 3P+19 3P+3 3P+11 3P+4 3P+18 3P+4 3P+10 DXHZ) td(FXL-DXV) McBSP as SPI Master or Slave timing requirements (CLKSTP = 11b, CLKXP = 1) 15/ 29/ See figure 26-29 MC23 Setup time, DR valid before CLKX high tsu(DRV-CKXL) 15 3-6P 10 3-6P MC24 Hold time, DR valid after CLKX high th(CKXL-DRV) 3+6P MC36 Setup time, FSX low before CLKX high tsu(FXL-CKXL) MC26 Cycle time, CLKX 5P+8 tc(CKX) 0 3+6P 0 5 2P 5 16P 2P McBSP as SPI Master or Slave switching characteristics (CLKSTP = 11b, CLKXP =1) 15/ 29/ MC37 Delay time, CLKX low to FSX low 31/ D-5 D+5 td(CKXL-FXL) MC38 Delay time, FSX low to CLKX high 32/ td(FXL-CKXH) T-5 T+5 MC29 Delay time, CLKX high to DX valid td(CKXH-DXV) -4 6 3P+3 MC39 Disable time, DX high impedance following last data bit from CLKX low tdis(CKXL- -4 4 MC32 Delay time, FSX low to DX valid td(FXL-DXV) C-4 C+4 ns 16P See figure 26-29 D-4 D+4 ns T-4 T+4 5P+15 -3 3 3P+3 3P+4 3P+19 -3 1 3P+3 3P+12 3P+4 3P+18 C-3 C+3 3P+4 3P+10 5P+8 DXHZ) See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 19 TABLE I. Electrical performance characteristics – Continued. No Test Symbol Test condition 2/ McBSP GENERAL PURPOSE I/O TIMINGS McBSP general purpose I/O timing requirements See figure 30 MC20 Setup time, MGPIOx input mode before CLKOUT tsu(MGPIO-COH) high 33/ 1/ Limits CVDD= 1.2 V CVDD = 1.35 V Min Max Unit CVDD = 1.6 V Min 7 7 0 0 ENHANCED HOST PORT INTERFACE (EHPI) TIMINGS EHPI timing requirements See figure 31-36 E11 4 tsu(HASL-HDSL) Setup time, HAS low before HDS low 4 MC21 Hold time, MGPIOx input mode after CLKOUT high 33/ th(COH-MGPIO) Max ns ns th(HDSL-HASL) 3 3 Setup time, (HR/W, HA[13:0], HBE 1: 0 , HCNTL[1:0]) valid before HDS low tsu(HCNTLV-HDSL) 2 2 Hold time, (HR/W, HA[13:0], HBE 1: 0 , HCNTL[1:0]) invalid after HDS low Pulse duration, HDS low Pulse duration, HDS high Setup time, HD bus write data valid before HDS high Hold time, HD bus write data invalid after HDS high th(HDSL-HCTNLIV) 4 4 tw(HDSL) tw(HDSH) Setup time, (HR/W, HBE 1: 0 , HCTNL[1:0]) valid before HAS low tsu(HCTNLV-HASL) 4P 15/ 4P 15/ 3 4 3 4P 15/ 4P 15/ 3 4 3 Hold time, (HR/W, HBE 1: 0 , HCTNL[1:0]) valid before HAS low EHPI switching characteristics See figure 31-36 E1 Enable time, HDS low to HD bus enable (memory access) E2 Delay time, HDS low to HD bus read data valid (memory access) th(HASL-HCTNLIV) 4 4 ten(HDSL-HDD)M 6 td(HDSL-HDV)M 14P 15/ 35/ 6 E12 Hold time, HAS low after HDS low E13 E14 E15 E16 E17 E18 E19 E20 E4 E9 E10 Enable time, HDS low to HD enabled (register access) Delay time, HDS low to HD bus read data valid (register access) Disable time, HDS high to HD bus read data invalid Delay time, HDS low to HRDY low (during reads) Delay time, HD bus valid to HRDY high (during reads) Delay time, HDS high to HRDY low (during writes) Delay time, HDS high to HRDY high (during writes) E21 Delay time, CLKOUT high to HINT high/low E5 E6 E7 E8 tsu(HDV-HDSH) th(HDSH-HDIV) ten(HDSL-HDD)R td(HDSL-HDV)R 26 6 19 26 14P 15/ 35/ 6 19 26 tdis(HDSH-HDIV) td(HDSL-HRDYL) td(HDV-HRDYH) 6 26 18 2 td(HDSH-HRDYL) td(HDSH-HRDYH) 19 6 19 15 2 18 14P 15/ 35/ 0 td(COH-HINT) ns 11 15 14P 15/ 35/ 0 8 See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 20 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 2/ 1/ Limits Unit CVDD= 1.2 V CVDD = 1.35 V Standard Fast Mode Mode Min Max Min Max CVDD = 1.6 V Standard Mode Min Max 10 4.7 2.5 0.6 10 4.7 2.5 0.6 4 0.6 4 0.6 4.7 4 250 4.7 4 250 0 37/ 1.3 0.6 100 36/ 0 37/ 4.7 1.3 Fast Mode Min Max I2C TIMINGS See figure 37-38 2 I C signals (SDA and SCL) timing requirements IC1 Cycle time, SCL tc(SCL) IC2 Setup time, SCL high before SDA low tsu(SCLH-SDAL) for a repeated START condition th(SCLL-SDAL) IC3 Hold time, SCL low after SDA low for a START and a repeated START condition IC4 Pulse duration, SCL low tw(SCLL) IC5 Pulse duration, SCL high tw(SCLH) IC6 Setup time, SDA valid before SCL high tsu(SDA-SCLH) IC7 Hold time, SDA valid after SCL low th(SDA-SCLL) 0 37/ 1.3 0.6 100 36/ 0 37/ IC8 tw(SDAH) 4.7 1.3 IC9 Pulse duration, SDA high between STOP and START conditions Rise time, SDA IC10 tr(SDA) 1000 Rise time, SCL tr(SCL) 1000 IC11 Fall time, SDA tf(SDA) 300 IC12 Fall time, SCL tf(SCL) 300 IC13 Setup time, SCL high before SDA high (for STOP condition) Pulse duration, spike (must be suppressed) Capacitive load for each bus line IC14 IC15 tsu(SCLH-SDAH) 4 tw(SP) Cb 40/ 400 0.9 38/ 39/ 40/ 39/ 40/ 39/ 40/ 39/ 40/ 0.6 300 1000 300 1000 300 300 300 300 0 50 4 400 µs ns 0.9 38/ µs 39/ 40/ 39/ 40/ 39/ 40/ 39/ 40/ 0.6 300 ns 0 50 ns 400 pF 400 300 300 300 µs See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 21 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 2/ 1/ Limits CVDD= 1.2 V CVDD = 1.35 V Standard Fast Mode Mode Min Max Min Max I2C TIMINGS I C signals (SDA and SCL) timing requirements- Continued See figure 37-38 IC16 Cycle time, SCL tc(SCL) 10 IC17 Delay time, SCL high before SDA low td(SCLH-SDAL) 4.7 for a repeated START condition th(SDAL-CLLL) IC18 Delay time, SDA low to SCL low for a 4 START and a repeated START condition IC19 Pulse duration, SCL low tw(SCLL) 4.7 IC20 Pulse duration, SCL high tw(SCLH) 4 IC21 Delay time, SDA valid to SCL high td(SDA-SCLH) 250 IC22 Valid time, SDA valid after SCL low th(SCLL-=SDAV) 0 IC23 Pulse duration, SDA high between tw(SDAH) 4.7 STOP and START conditions IC24 Rise time, SDA tr(SDA) 1000 IC25 Rise time, SCL tr(SCL) 1000 IC26 Fall time, SDA tf(SDA) 300 IC27 Fall time, SCL tf(SCL) 300 IC28 Delay time, SCL high before SDA high (for STOP condition) Capacitive load for each bus line Unit CVDD = 1.6 V Standard Mode Min Max Fast Mode Min Max 2 IC29 td(SCLH-SDAH) 4 Cb 40/ 400 2.5 0.6 10 4.7 2.5 0.6 0.6 4 0.6 1.3 0.6 100 0 1.3 4.7 4 250 0 4.7 1.3 0.6 100 0 1.3 39/ 40/ 39/ 40/ 39/ 40/ 39/ 40/ 0.6 0.9 300 1000 300 1000 300 300 300 300 4 400 39/ 40/ 39/ 40/ 39/ 40/ 39/ 40/ 0.6 400 µs 0.9 ns µs 300 ns 300 300 300 µs 400 pF See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 22 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 2/ UNIVERSAL SERIAL BUS (USB) TIMINGS Universal serial bus (ISB) characteristics See figure 39 and 40 U1 Rise time of DP and DN signal 41/ tr U2 Fall time of DP and DN signal 41/ tf Rise/Fall time matching 42/ tRFM Output signal cross over voltage 41/ VCRS Differential propagation jitter 43/ 44/ tjr Operating frequency (full speed mode) fop U3 Series resistor Rs(DP) U4 Series resistor Rs(DN) U5 Edge rate control capacitor Cedge(DP) U6 Edge rate control capacitor Cedge(DN) ADC TIMINGS ADC characteristics A1 Cycle time, ADC internal conversion clock tc(SCLC) A2 Delay time, ADC sample and hold acquisition time td(AQ) A3 Delay time, ADC conversion time td(CONV) A4 Static differential non-linearity error SDNL Static integral non-linearity error A5 Zero scale offset error Zset A6 Full scale offset error Fset A7 Analog input impendance 1/ Limits CVDD= 1.2 V CVDD = 1.6 V CVDD = 1.35 V Full speed Full speed 12Mbps 12Mbps Min Max Min Max 4 4 90 1.3 -2 12 24 24 22 22 20 20 111.11 2 2 TYP TYP TYP TYP TYP 500 4 4 90 1.3 -2 12 24 24 22 22 20 20 111.11 2 2 TYP TYP TYP TYP TYP 500 40 45/ 2 3 9 9 1 40 45/ 2 3 9 9 1 Unit ns % V ns Mb/s W W pF ns µs ns LSB LSB LSB MW See footnote at end of table DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 23 TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/ 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 13/ 14/ 15/ 16/ 17/ 18/ 19/ 20/ 21/ 22/ 23/ 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Over recommended operating case temperature range; unless otherwise noted. USB I/O pins DP and DN can tolerate a short circuit at D+ and D- to 0 V or 5 V, as long as the recommended series resistors ( see Figure 40) are connected between the D+ and DP (package), and the D- and DN (package. Do not apply a short circuit to the USB I/O pins DP and DN in absence of the series resistors. The I2C pins SDA and SCL do not feature fail-safe I/O buffers, These pins could potentially draw current when the device is powered down. CPU executing 75% dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active. All other domain are idled. One world of a table of a 16-bit sine value is writtern to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10 pF load. In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current will be higher if an external clock source tries to drive the X2/CLKIN pin during this time. This device utilizes a fully static design and therefore can operate with tc(CI) approaching . If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in manufacturer data. It is recommended that the DPLL synthesized clocking option be used to obtain maximum operating frequency. N = Clock frequency synthesis factor. ESR must be 200 kΩ or greater at frequency other than 32.768 kHz. Otherwise, oscillations at overtone frequency may occur. To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus ARDY can be asynchronous input. Maximum SDRAM operating frequency = 108 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board design and the memory chip timing requirement. Maximum SDRAM operating frequency = 133 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board design and the memory chip timing requirement. P = 1/(input clock frequency) in ns. For example, when running parts at 12 MHz, P = 83.33 ns. Oscillator stable time depends on the crystal characteristics (i.e., frequency, ESR, etc.) which varies from one crystal manufacturer to another. Based on the crystal characteristics, the oscillator stable time can be in the range of a few to 10 s of ms. A reset circuit with 100 ms or more dealy time will ensure the oscillator before the RESET goes high. BK group: Pins with bus keepers, hold previous state during reset. Following low-to-high transition of RESET, these pins go to their post reset logic state. BK group pins: A’[0], A[15:0], D[15:0], C[14:2], c0, GPIO5, DX1, and DX2. High group: Following low to high transition of RESET, these pins go to logic high state. High group pins: C1[HPI.HINT], XF Z group: Bidirectional pins which became input or output pins. Following low to high transition of RESET, these pins go to high impedance state. Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DX0, FSX0, FSX2, CLKX2, FSR2, DR2, CLKR2, FSX1, CLKX1, FSR1, DR1, CLKR1, A[20:16]. Estimated data based on 12 MHz crystal used with on-chip oscillator at 25C. This number will vary based on the actual crystal characteristics operating condition and the PC board layout and the parasitic. Following the clock generation domain idle, the INTx becomes level sensitive and stay that way until the low to high transaction of INTx following the CPU wake up. Holding the INTx low longer than minimum requirement will send more than one interrupt to the CPU. The number of interrupts sent to the CPU depends on the INTx low time following the CPU wake up from IDLE. AGPIO pins: A[15:0] EHPIGPIO pins: C13, C10, C7, C5, C4 , and C0 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 24 TABLE I. Electrical performance characteristics - Continued. 24/ 25/ 26/ 27/ 28/ 29/ 30/ 31/ 32/ 33/ 34/ 35/ 36/ 37/ 38/ 39/ 40/ 41/ 42/ 43/ 44/ 45/ 1/ Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use. For proper operation of the TIN/TOUT pin configured as an output, the timer period must be configured for at least 4 cycles. Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any signals is inverted, then the timing references of that signal are also inverted. T = CLKRX period = (1 + CLKGDV) * P C = CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D = CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even. See manufacturer data for a description of the DX enable (DXENA) and data delay features of the McBSP. For all SPI slave modes, CLKG is programmed as ½ of the CPU clock by setting CLKSM = CLKGDV = 1. T = CLKRX period = (1 + CLKGDV) * 2P C = CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active low slave enable output. As a slave, the active low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP. FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general purpose input. MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general purpose output. EHPI latency is dependent on the number of DMA channels active, their priorities and their source/destination ports. The latency shown assumes no competing CPU or DMA activity to the memory resource being accessed by the EHPI. A fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-ASCLH) = 1000 + 250 = 1250 ns (according to the Standard mode I2C Bus specification) before the SCL line is released. A device must internally provide a hold time for at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDA-SCLL) has only to bet met if the device does not stretch the LOW period [tw(SCLL)] of the SCL signal. 20 + 0.1Cb Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times are allowed. CL = 50 pF (tr/tf) x 100 tpx(1) x tpx(0) USB PLL is susceptible to power supply ripple, refer to recommended operating conditions for allowable supply ripple to meet the USB pea to peak jitter specification. 13*tc(SCLC) DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 25 Case X Symbol A A1 A2 A3 b c Dimensions Millimeters Symbol Min Max 1.35 1.45 1.60 0.25 TYP 0.05 0.17 0.27 0.13 NOM D/E D1/E1 D2/E2 e L Millimeters Min Max 21.80 22.20 19.80 20.20 17.50 TYP 0.50 BSC 0.45 0.75 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. FIGURE 1. Case outlines. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 26 Case X Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Signal Name VSS PU DP DN USBVDD GPIO7 VSS DVDD GPIO2 GPIO1 VSS GPIO0 X2/CLKIN X1 CLKOUT C0 C1 CVDD C2 C3 C4 C5 C6 DVDD C7 C8 C9 C11 CVDD CVDD C14 C12 VSS C10 C13 VSS Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Signal Name VSS A13 A12 A11 CVDD A10 A9 A8 VSS A7 A6 A5 DVDD A4 A3 A2 CVDD A1 A0 DVDD D0 D1 D2 VSS D3 D4 D5 VSS D6 D7 D8 CVDD D9 D10 D11 DVDD Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Signal Name VSS D12 D13 D14 D15 CVDD EMU0 EMU1/OFF TDO TDI CVDD TRST TCK TMS CVDD DVDD SDA SCL RESET USBPLLVSS INT0 INT1 USBPLLVDD INT2 INT3 DVDD INT4 VSS XF VSS ADVSS ADVDD AIN0 AIN1 AVDD AVSS Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Signal Name RDVDD RCVDD RTCINX2 RTCINX1 VSS VSS VSS DX2 FSX2 CVDD CLKX2 DR2 FSR2 VSS CLKR2 DX1 FSX1 DVDD CLKX1 DR1 FSR1 CLKR1 DX09 CVDD FSX0 CLKX0 DR0 FSR0 CLKR0 VSS DVDD TIN/TOUT0 GPIO6 GPIO4 GPIO3 VSS FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 27 NOTE: 1. Number of pins determined by package type. FIGURE 3. Functional block diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 28 NOTE: 1. The relationship of X2/CLKIN to CLKOUT depends on the PLL bypass divide factor chosen for the CLKMD register. The waveform relationship shown in this figure is intended to illustrate the timing parameters based on CLKOUT = ½(CLKIN) configuration. FIGURE 4. Timing waveforms. NOTE: 1. The relationship of X2/CLKIN to CLKOUT depends on the PLL multiply and divide factor chosen for the CLKMD register. The waveform relationship shown in this figure is intended to illustrate the timing parameters based on CLKOUT = 1xCLKIN configuration. FIGURE 5. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 29 FIGURE 6. Timing waveforms. NOTES: 1. CLKOUT is equal to CPU clock. 2. CEx becomes active depending on the memory address space being accessed. 3. A[13:0] for LQFP FIGURE 7. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 30 NOTES: 1. CLKOUT is equal to CPU clock. 2. CEx becomes active depending on the memory address space being accessed. 3. A[13:0] for LQFP FIGURE 8. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 31 NOTES: 1. The chip enable that becomes active depends on the address being accessed. 2. All BE 1: 0 signals are driven low (active) during reads. Byte manipulation of the read data is performed inside EMIF. These signals remain active until the next access that is not an SDRAM read occurs FIGURE 9. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 32 NOTES: 1. The chip enable that becomes active depends on the address being accessed. 2. All BE 1: 0 signals are driven low (active) during reads. Byte manipulation of the read data is performed inside EMIF. These signals remain active until the next access that is not an SDRAM read occurs FIGURE 10. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 33 NOTES: 1. The chip enable that becomes active depends on the address being accessed. 2. All BE 1: 0 signals are driven low (active) during reads. Byte manipulation of the read data is performed inside EMIF. These signals remain active until the next access that is not an SDRAM read occurs FIGURE 11. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 34 NOTES: 1. The chip enable that becomes active depends on the address being accessed. 2. All BE 1: 0 signals are driven low (active) during reads. Byte manipulation of the read data is performed inside EMIF. These signals remain active until the next access that is not an SDRAM read occurs FIGURE 12. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 35 NOTES: 1. The chip enable that becomes active depends on the address being accessed. 2. All BE 1: 0 signals are driven low (active) during reads. Byte manipulation of the read data is performed inside EMIF. These signals remain active until the next access that is not an SDRAM read occurs FIGURE 13 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 36 NOTES: 1. The chip enable that becomes active depends on the address being accessed. 2. All BE 1: 0 signals are driven low (active) during reads. Byte manipulation of the read data is performed inside EMIF. These signals remain active until the next access that is not an SDRAM read occurs. 3. Write burst length = 1 Read latency = 3 Burst type = 0 (serial) Burst length = 1 FIGURE 14 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 37 FIGURE 15 Timing waveforms. FIGURE 16 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 38 FIGURE 17 Timing waveforms. NOTES: 1. BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, DX1, and DX2. 2. High group pins: C1[HPI.HINT], XF. 3. Z group pins: c1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DFX0, FDSX0, FSX2, CLKX2, FSR2, DR2, CLKR2, FSX1, CLKX1, FSR1, DR1, CLKR1, a[20:16]. FIGURE 18 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 39 FIGURE 19 Timing waveforms. FIGURE 20 Timing waveforms. NOTES: 1. CLKOUT reflects the CPU clock. FIGURE 21 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 40 NOTES: 1. CLKOUT reflects the CPU clock. FIGURE 22 Timing waveforms. FIGURE 23 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 41 FIGURE 24. Timing waveforms. FIGURE 25. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 42 FIGURE 26. Timing waveforms. FIGURE 27. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 43 FIGURE 28. Timing waveforms. FIGURE 29. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 44 NOTES: 1. CLKOUT reflects the CPU clock. 2. MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general purpose input. 3. MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general purpose output FIGURE 30. Timing waveforms. FIGURE 31. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 45 NOTES: 1. Any non-multiplexed access with HCNTL0 low will result in HPIC register access. For data read or write, HCNTL0 must stay high during the EHPI access. 2. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state. FIGURE 32. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 46 NOTES: 1. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state. FIGURE 33. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 47 NOTES: 1. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host will always indicate the base address. 2. In autoincrement mode, if HBE 1: 0 are used to access the data as 8 bit wide units, the HPIA increments only following each high byte (HBE1 low) access. 3. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state. FIGURE 34. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 48 NOTES: 1. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host will always indicate the base address. 2. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state. FIGURE 35. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 49 NOTES: 1. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host will always indicate the base address. 2. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state. FIGURE 36. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 50 FIGURE 37. Timing waveforms. FIGURE 38. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 51 FIGURE 39. Timing waveforms. NOTES: 1. A full speed buffer is measured with the load shown. 2. CL = 50 pF FIGURE 40. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 52 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. 1/ Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/09647-01XA 01295 SM320VC5507PGESEP The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/09647 PAGE 53