Philips Semiconductors Product specification N-channel TrenchMOS transistor FEATURES IRF530N SYMBOL QUICK REFERENCE DATA • ’Trench’ technology • Low on-state resistance • Fast switching • Low thermal resistance d VDSS = 100 V ID = 17 A g RDS(ON) ≤ 110 mΩ s GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:• d.c. to d.c. converters • switched mode power supplies PINNING PIN SOT78 (TO220AB) DESCRIPTION 1 gate 2 drain 3 source tab tab drain 1 2 3 gate source drain drain The IRF530N is supplied in the SOT78 (TO220AB) conventional leaded package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 100 100 ± 20 17 12 68 79 175 V V V A A A W ˚C MIN. MAX. UNIT - 150 mJ - 17 A Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS EAS Non-repetitive avalanche energy Unclamped inductive load, IAS = 7.8 A; tp = 300 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer to fig:14 IAS Peak non-repetitive avalanche current August 1999 1 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor IRF530N THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air TYP. MAX. UNIT - - 1.9 K/W - 60 - K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) gfs IGSS IDSS Drain-source on-state resistance Forward transconductance Gate source leakage current Zero gate voltage drain current VGS = 10 V; ID = 9 A Tj = 175˚C VDS = 25 V; ID = 9 A VGS = ± 20 V; VDS = 0 V VDS = 100 V; VGS = 0 V VDS = 80 V; VGS = 0 V; Tj = 175˚C 100 89 2 1 6.4 - TYP. MAX. UNIT 3 80 11 10 0.05 - 4 6 110 275 100 10 250 V V V V V mΩ mΩ S nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 9 A; VDD = 80 V; VGS = 10 V - - 40 5.6 19 nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 50 V; RD = 2.7 Ω; VGS = 10 V; RG = 5.6 Ω Resistive load - 6 36 18 12 - ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 633 103 61 - pF pF pF REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge ISM August 1999 CONDITIONS MIN. TYP. MAX. UNIT - - 17 A - - 68 A IF = 17 A; VGS = 0 V - 0.92 1.2 V IF = 17 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V - 55 135 - ns nC 2 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor IRF530N Normalised Power Derating, PD (%) 10 100 Transient thermal impedance, Zth j-mb (K/W) 90 80 D = 0.5 1 70 0.2 60 0.1 50 0.05 40 0.1 P D 0.02 30 20 single pulse T 10 0.01 1E-06 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Drain Current, ID (A) 20 Normalised Current Derating, ID (%) 100 VGS = 10V 8V 18 90 Tj = 25 C 16 80 6V 14 70 12 60 50 10 40 8 30 6 20 4 10 5.4 V 5.2 V 5V 4.8 V 2 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 4.6 V 175 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 0.2 RDS(on) = VDS/ ID 1.8 2 Drain-Source On Resistance, RDS(on) (Ohms) 4.8V 0.18 tp = 10 us 4.6V 5.2 V 5V 0.16 10 Tj = 25 C 5.4 V 0.14 100 us 1 1.6 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) Peak Pulsed Drain Current, IDM (A) D.C. 4.4 V 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V 100 1E-05 D = tp/T tp 6V 0.12 0.1 1 ms 10 ms 0.08 8V 100 ms 0.06 VGS = 10V 0.04 0.02 0.1 0 1 10 100 Drain-Source Voltage, VDS (V) 1000 0 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp August 1999 2 4 6 8 10 12 Drain Current, ID (A) 14 16 18 20 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) 3 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor IRF530N Drain current, ID (A) 4.5 20 VDS > ID X RDS(ON) 18 Threshold Voltage, VGS(TO) (V) 4 16 3.5 14 3 12 maximum typical 2.5 10 minimum 2 8 175 C 6 1.5 Tj = 25 C 4 1 0.5 2 0 0 0 1 2 3 4 5 6 7 8 9 10 -60 -40 -20 Gate-source voltage, VGS (V) 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) Drain current, ID (A) 1.0E-01 VDS > ID X RDS(ON) Tj = 25 C 1.0E-02 175 C minimum 1.0E-03 typical 1.0E-04 maximum 1.0E-05 1.0E-06 0 2 4 6 8 10 12 14 Drain current, ID (A) 16 18 0 20 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised On-state Resistance 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 10000 Capacitances, Ciss, Coss, Crss (pF) Ciss 1000 Coss 100 Crss 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 0.1 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) August 1999 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor IRF530N Maximum Avalanche Current, IAS (A) Source-Drain Diode Current, IF (A) 100 20 VGS = 0 V 18 16 14 10 12 25 C 175 C 10 8 Tj = 25 C 1 6 Tj prior to avalanche = 150 C 4 2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0.1 0.001 1.2 Source-Drain Voltage, VSDS (V) 0.1 1 10 Avalanche time, tAV (ms) Fig.13. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj August 1999 0.01 Fig.14. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load 5 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor IRF530N MECHANICAL DATA Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 E SOT78 A A1 P q D1 D L1 L2(1) Q b1 L 1 2 e e 3 c b 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 c D D1 E mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 e L L1 2.54 15.0 13.5 3.30 2.79 L2 max. P q Q 3.0 3.8 3.6 3.0 2.7 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 TO-220 Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g) Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". August 1999 6 Rev 1.100 Philips Semiconductors Product specification N-channel TrenchMOS transistor IRF530N DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1999 7 Rev 1.100