Philips Semiconductors Product specification N-channel TrenchMOS transistor FEATURES PHX23NQ10T SYMBOL QUICK REFERENCE DATA • ’Trench’ technology • Low on-state resistance • Fast switching d VDSS = 100 V ID = 13 A g RDS(ON) ≤ 70 mΩ s GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic full pack envelope using ’trench’ technology. Applications:• d.c. to d.c. converters • switched mode power supplies • T.V. and computer monitor power supplies The PHX23NQ10T is supplied in the SOT186A (FPAK) conventional leaded package. PINNING SOT186A (FPAK) PIN DESCRIPTION case 1 gate 2 drain 3 source case isolated 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 100 100 ± 20 13 8 52 27 150 V V V A A A W ˚C September 1999 Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C 1 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX23NQ10T AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy IAS Peak non-repetitive avalanche current CONDITIONS MIN. MAX. UNIT - 93 mJ - 23 A Unclamped inductive load, IAS = 14 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer to fig:15 THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT186a package, in free air TYP. MAX. UNIT - - 4.6 K/W - 55 - K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) Drain-source breakdown voltage Gate threshold voltage CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C RDS(ON) IGSS IDSS Drain-source on-state VGS = 10 V; ID = 13 A resistance Gate source leakage current VGS = ± 10 V; VDS = 0 V Zero gate voltage drain VDS = 100 V; VGS = 0 V current Tj = 150˚C Tj = 150˚C MIN. TYP. MAX. UNIT 100 89 2 1.25 - 3 49 115 10 0.05 - 4 6 70 163 100 10 500 V V V V V mΩ mΩ nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 23 A; VDD = 80 V; VGS = 10 V - 22 5 10 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 50 V; RD = 2.2 Ω; VGS = 10 V; RG = 5.6 Ω Resistive load - 8 39 26 24 - ns ns ns ns Ld Ls Internal drain inductance Internal source inductance Measured from drain lead to centre of die Measured from source lead to source bond pad - 4.5 7.5 - nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 890 139 83 1187 167 109 pF pF pF September 1999 2 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX23NQ10T REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM CONDITIONS MIN. TYP. MAX. UNIT - - 13 A - - 92 A IF = 11 A; VGS = 0 V - 0.9 1.2 V IF = 11 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V - 64 120 - ns nC ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Visol R.M.S. isolation voltage from all three terminals to external heatsink f = 50-60 Hz; sinusoidal waveform; R.H. ≤ 65% ; clean and dustfree Cisol Capacitance from T2 to external f = 1 MHz heatsink September 1999 3 MIN. TYP. - - 10 MAX. UNIT 2500 V - pF Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX23NQ10T Normalised Power Derating, PD (%) Transient thermal impedance, Zth j-a (K/W) 10 100 90 D = 0.5 80 0.2 1 70 60 0.1 50 0.05 40 0.02 0.1 30 single pulse 20 10 0.01 1E-06 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 100 50 90 45 80 40 70 35 60 30 50 25 40 20 30 15 20 10 10 5 0 0 9V 1E-01 1E+00 1E+01 8V 7V 6V 5V 4V 0 150 1 2 3 4 5 6 7 8 9 10 Drain-Source Voltage, VDS (V) Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V 1000 1E-02 Drain Current, ID (A) 55 50 75 100 125 Mounting Base temperature, Tmb (C) 1E-03 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating, ID (%) 25 1E-04 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 0 1E-05 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) Drain-Source On Resistance, RDS(on) (Ohms) Peak Pulsed Drain Current, IDM (A) 0.8 0.7 RDS(on) = VDS/ ID 100 0.6 tp = 10 us 0.5 100us 0.4 1 ms 0.3 4V 10 D.C. 6V 6.5V 5V 10 ms 1 5.5V 0.2 100 ms 7V 8V 0.1 VGS =9 V 0.1 0 1 10 100 1000 0 Drain-Source Voltage, VDS (V) Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp September 1999 10 20 30 Drain Current, ID (A) 40 50 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) 4 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX23NQ10T ID / A 50 Threshold Voltage, VGS(TO) (V) 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 40 Tj / C = 25 30 150 20 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 Junction Temperature, Tj (C) 0 0 2 4 6 8 10 VGS / V Fig.7. Typical transfer characteristics. ID = f(VGS) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) 1.0E-01 20 Drain current, ID (A) Tj = 25 C 18 1.0E-02 16 14 minimum 1.0E-03 12 150 C 10 typical 8 1.0E-04 maximum 6 4 1.0E-05 2 0 1.0E-06 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Drain current, ID / (A) 0 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Capacitances, Ciss, Coss, Crss (pF) 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 10000 Normalised On-state Resistance. Ciss 1000 Coss 100 Crss -60 -40 -20 0 20 40 60 80 100 120 140 160 Junction temperature , Tj (C) 10 0.1 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) September 1999 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 5 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX23NQ10T Maximum Avalanche Current, IAS (A) 100 Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID = 23A Tj = 25 C VDD = 20 V 25 C 10 VDD = 80 V Tj prior to avalanche = 150 C 1 0 5 10 15 20 Gate charge, QG (nC) 25 30 0.1 0.001 35 0.01 0.1 1 10 Avalanche time, tAV (ms) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Source-Drain Diode Current, IF (A) 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 VGS = 0 V 150 C Tj = 25 C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Source-Drain Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj September 1999 6 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX23NQ10T MECHANICAL DATA Dimensions in mm Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 SOT186A Net Mass: 2 g E A A1 P q D1 T D j L2 L1 K Q b1 L b2 1 2 3 b c w M e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 b2 c D D1 E mm 4.6 4.0 2.9 2.5 0.9 0.7 1.1 0.9 1.4 1.2 0.7 0.4 15.8 15.2 6.5 6.3 10.3 9.7 e 2.54 e1 j K 5.08 2.7 2.3 0.6 0.4 L L1 14.4 3.30 13.5 2.79 L2 max. P Q q 3 3.2 3.0 2.6 2.3 3.0 2.6 (2) T 2.5 w 0.4 Notes 1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned. 2. Both recesses are ∅ 2.5 × 0.8 max. depth OUTLINE VERSION SOT186A REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 Fig.16. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". September 1999 7 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHX23NQ10T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 1999 8 Rev 1.000