Supertex inc. HV9803B LED Driver IC with Average-Mode Constant Current Control Features ►► ►► ►► ►► ►► ►► Fast average current control Correction for propagation delay and offset voltage Fixed off-time switching mode Linear dimming input PWM dimming input Output short circuit protection with programmable skip mode ►► Input under-voltage shutdown Applications General Description The HV9803B is an open loop average-mode current control LED driver IC operating in a constant off-time mode. The IC features ±2% current accuracy, tight line and load regulation of the LED current without any need for loop compensation or high-side current sensing. Its auto-zero circuit cancels the effect of both the input offset voltage and the propagation delay in the current sense comparator. The HV9803B can be powered from a 7.0 to 16V supply. The IC features fast PWM dimming response. The linear dimming input LD can accept a reference voltage from 0 to 3.0V. The IC is equipped with a current limit comparator for hiccup-mode output short circuit protection. It also features a programmable input under-voltage shutdown. ►► Backlighting of LCD Panels ►► General Lighting Typical Application Circuit +VIN 7.0~16V CDD R1 DIM CIN D1 L1 VDD PWMD Q1 GATE HV9803B REF LD CS UVLO RT RCS CSKIP R2 Doc.# DSFP-HV9803B B032114 GND RT Supertex inc. www.supertex.com HV9803B Pin Configuration Ordering Information Part Number Package Option Packing HV9803BLG-G 8-Lead SOIC 2500/Reel CS 1 8 LD VDD 2 7 UVLO GND 3 6 PWMD GATE 4 5 RT -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings* Parameter 8-Lead SOIC Value VDD, GATE, CS -0.3V to +17V LD, RT, PWMD, UVLO -0.3V to +6.0V Operating temperature range -40°C to +125°C Storage temperature range -65°C to +150°C Power dissipation @ 25°C 650mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Product Marking YWW 9803B LLLL Y = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging Package may or may not include the following marks: Si or 8-Lead SOIC Typical Thermal Resistance Package θja 8-Lead SOIC 101°C/W Electrical Characteristics (The * denotes specifications which apply over the full operating ambient temperature range of -40°C<TA<125°C. Otherwise specifications are at TA = 25°C. VDD = 12V, PWMD = 5.0V, unless otherwise noted) Sym Description Min Typ Max Units Conditions Input VDD Input DC supply voltage range * - - 16 V DC input voltage IDD Quiescent VDD supply current * - 1.5 2.5 mA VCS = 0V * 6.45 6.70 6.95 V VDD rising - - 500 - mV VDD falling VDD Under-Voltage Lockout VDD(UV) ΔVDD(UV) VDD under-voltage lockout threshold VDD under-voltage lockout hysteresis PWM Dimming VEN(LO) PWMD input low voltage * - - 1.0 V --- VEN(HI) PWMD input high voltage * 2.6 - - V --- Internal pull-down resistance at PWMD - 50 100 150 kΩ --- REN Doc.# DSFP-HV9803B B032114 2 Supertex inc. www.supertex.com HV9803B Electrical Characteristics (cont.) (The * denotes specifications which apply over the full operating ambient temperature range of -40°C<TA<125°C. Otherwise specifications are at TA = 25°C. VDD = 12V, PWMD = 5.0V, unless otherwise noted) Sym Description Min Typ Max Units - 0 - 3.0 V * 284 - 296 * 866 - 902 Conditions Current Sense Comparator VLD External reference voltage VCS CS reference voltage AV(LD) LD to CS voltage ratio - - 0.495 - - --- TBLANK Current sense blanking interval * 150 - 280 ns --- TON(MIN) Minimum on-time - - - 760 ns VCS = 0.5VLD +30mV Maximum steady-state duty cycle * 85 - - % Reduction in output LED current may occur beyond this duty cycle Internal current reference - 1.57 - 1.93 V --- Current limit delay CS-to-GATE - - - 150 ns VCS = VLIM +30mV RUVLO(R) UVLO skip timer reset switch resistance - - - 500 Ω --- VUVLO(R) UVLO skip timer reset voltage - 200 - 300 mV --- TON(MIN) Minimum on-time (short circuit) - - - 430 ns VCS = VLIM +30mV Off time - 6.7 9.0 11.3 μs RT = 250kΩ 0.8 1.0 1.2 μs RT = 25kΩ RT over-current threshold - - 2.8 - mA --- Gate sourcing current - 0.165 - - A VGATE = 0V ISINK Gate sinking current - 0.165 - - A VGATE = VDD tRISE GATE output rise time - - 30 50 ns CGATE = 500pF tFALL GATE output fall time - - 30 50 ns CGATE = 500pF UVLO Under-voltage threshold voltage * 1.17 - 1.29 V VUVLO rising ΔUVLO Under-voltage threshold voltage hysteresis - - 150 - mV VUVLO falling DMAX mV --VLD = 0.6V VLD = 1.8V Short Circuit Protection VLIM TDELAY TOFF Timer TOFF IRT(LIM) GATE Driver ISOURCE UVLO # Guaranteed by design * Limits over temperature are guaranteed by design and characterization Doc.# DSFP-HV9803B B032114 3 Supertex inc. www.supertex.com HV9803B Functional Block Diagram i + - IRT(LIM) VDD UVLO1 + - Reset VLD LD + 250mV Auto-REF xAV(LD) POR 10mV CS UVLO2 L/E Blanking IN SKIP Average-Mode Control Logic GATE OUT VLIM GND SKIP + Q Q S Q PWMD TOFF Timer Reset i Functional Description Current Mirror RT The HV9803B employs Supertex’ patented control scheme, achieving fast and very accurate control of average current in the buck inductor through sensing the switch current only. No compensation of the current control loop is required. The inductor current ripple amplitude does not affect this control scheme significantly, and therefore, the LED current is independent of the variation in inductance, switching frequency or output voltage. Constant off-time control of the buck converter is used for stability and to improve the LED current regulation over a wide range of input voltages. The IC features excellent PWM dimming response. Peak-current control of a buck converter is the most economical and simple way to regulate its output current. However, it suffers accuracy and regulation problems that arise from the peak-to-average current error, contributed to by the current ripple in the output inductor and the propagation delay in the current sense comparator. The full inductor current signal is unavailable for direct sensing at the ground potential in a buck converter when the control switch is referenced to the same ground potential. While it is very simple to detect the peak current in the switch, controlling the average inductor current is usually implemented by level-translating the current sense signal from the positive input supply rail. While this is practical for relatively low input voltage, this type of average-current control may become excessively complex and expensive in the case of input voltage in excess of 100V. Doc.# DSFP-HV9803B B032114 R S R HV9803B UVLO 4 Supertex inc. www.supertex.com HV9803B OFF Timer Short Circuit Protection In the HV9803B, the timing resistor connected to RT determines the off-time of the gate driver, and it must be wired to GND. The equation governing the off-time of the GATE output is given by: The HV9803B is equipped with a protection comparator having a CS threshold VLIM. When this second threshold is triggered, the GATE output shuts off for the duration of a restart delay, determined by the RC constant at UVLO. The capacitor CSKIP is discharged below 200mV. A restart delay due to charging CSKIP to the UVLO start threshold is calculated as: k • VIN - 0.30V TSKIP = k • R1 • CSKIP • ln k • VIN - 1.17V TOFF = RT • 40pF The RT input is protected from short circuit. Over-current condition at RT inhibits the IC. Current Sense Comparator and Timer Circuits The function of the HV9803B’s current sense comparator is similar to that of a peak current controller. However, the GATE pulse is not terminated immediately as the LD threshold is met. The GATE turn off in the nth cycle is delayed by a time T2,n determined by a timer circuit as follows: where k = R2 / (R1+R2). Under-Voltage Shutdown Under-voltage comparator input is provided to disable the IC, when the UVLO input is below a threshold. Hysteresis is provided to avoid oscillation. 1 T2,n = • (T1,n + T1,n-1) 2 where T1,n and T1,n-1 are the times to the LD threshold in any two consequent switching cycles. This iterative control law is needed for damping sub-harmonic oscillation. Failure Modes and Effects Analysis (FMEA) The HV9803B is designed to withstand short circuit between its adjacent pins without damage. The following table describes the effect of such incidental short circuit conditions. Note, that the above control law is only valid up to a maximum switching duty cycle Dmax= 0.85. Exceeding Dmax will cause reduction in the LED current. Propagation delay in the current sense comparator is one of the most significant contributors to the LED current error. It must be noted that the control scheme described above does not improve this deficiency of the peak-current control scheme by itself. Moreover, it samples the propagation delay during T1 and replicates it during T2, essentially doubling the error introduced by this delay. In order to eliminate this error, the reference voltage is corrected by an auto-zero circuit. In essence, the HV9803B samples its CS signal when the current sense comparator triggers, detects the difference between the sampled CS level and the reference input of the current sense comparator. The resulting difference is subtracted from the reference level to generate a new reference in the next switching cycle. Short Circuit Mode Effect CS to VDD The IC triggers the short circuit protection and operates in the autorestart mode continuously. VDD to GND Short circuit across the 12V should cause the external bias supply overcurrent protection. GND to GATE Should cause the external bias supply over-current protection. The power MOSFET Q1 is off. RT to PWMD GATE Output The GATE output of the HV9803B is used to drive an external MOSFET. It is recommended that the gate charge QG of the external MOSFET be less than 25nC for switching frequencies ≤100kHz and less than 15nC for switching frequencies >100kHz. The resulting LED current is calculated from the equation: ILED = Doc.# DSFP-HV9803B B032114 Case 1 – PWMD = Lo: The RT pin sources its maximum current. GATE = 0V, and Q1 is off. Case 2 – PWMD=Hi: The RT pin is pulled up, shutting off the timer. GATE is off. PWMD to UVLO This will overdrive the under-voltage threshold. However, since VIN UV condition is harmless to the IC, there is no effect. UVLO to LD LD overdrives the UVLO. If LD is lower than the UVLO threshold, the IC shuts off. No effect otherwise. 0.495 • VLD - 7mV RCS 5 Supertex inc. www.supertex.com HV9803B Pin Description (8-Lead SOIC) Pin Name 1 CS 2 VDD This is the power supply input for the GATE output and input of the low-voltage regulator powering the internal logic. It must be bypassed with a low ESR capacitor to GND (at least 0.1μF). 3 GND Ground return for all internal circuitry. This pin must be electrically connected to the ground of the power train. 4 GATE This pin is the output gate driver for an external N-channel power MOSFET. 5 RT 6 PWMD This is the PWM dimming input of the IC. When this pin is pulled to GND, the gate driver is turned off. When the pin is pulled high, the gate driver operates normally. 7 UVLO This pin is the under-voltage comparator input. It is also used to form a short-circuit protection skip delay. 8 LD Doc.# DSFP-HV9803B B032114 Description This pin is the current sense pin used to detect the MOSFET source current by means of an external sense resistor. A resistor connected between RT and GND programs the GATE off-time. This pin is the reference voltage input for programming the LED current. 6 Supertex inc. www.supertex.com HV9803B 8-Lead SOIC (Narrow Body) Package Outline (LG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch θ1 D 8 Note 1 (Index Area D/2 x E1/2) E1 E Gauge Plane L2 L 1 L1 Top View View B Note 1 Seating Plane θ View B h A h A A2 Seating Plane A1 e b Side View View A-A A Note: 1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 A2 b MIN 1.35* 0.10 1.25 0.31 NOM - - - - MAX 1.75 0.25 1.65* 0.51 D E E1 4.80* 5.80* 3.80* 4.90 6.00 3.90 5.00* 6.20* 4.00* e 1.27 BSC h L 0.25 0.40 - - 0.50 1.27 L1 L2 θ θ1 0 5O - - 8 15O O 1.04 REF 0.25 BSC O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version I041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV9803B B032114 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com