Outline Sheet No. 5-26-06 Advanced Information IRMCF341 High Performance Appliance Motor Control IC Features MCETM(Motion Control Engine) - Hardware based computation engine for high efficiency sinusoidal sensorless control for Permanent Magnet AC motors Built-in hardware peripheral for single shunt current feedback reconstruction Supports both interior and surface permanent magnet motor sensorless control No external current or voltage sensing OP amp circuit required Loss minimization Space Vector PWM Three-channel analog output (PWM) Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine control JTAG programming port for emulation/debugger Serial communication interface (UART) I2C/SPI serial interface Three general purpose timers/counters Three special timers: watchdog timer, periodic timer, capture timer Three general purpose timers/counters Product Summary Maximum clock input (fcrystal) 60 MHz Maximum internal clock (SYSCLK) 128 MHz Sensorless control computation time 11 µsec typ MCETM computation data range 16 bit signed Program RAM loaded from external EEPROM Data RAM GateKill latency (digital filtered) PWM carrier frequency A/D input channels 48K bytes 8K bytes 2 µsec 14 bits/ SYSCLK 8 A/D converter resolution 12 bits A/D converter conversion speed 2 µsec 8051 instruction execution speed 2 SYSCLK Analog output (PWM) resolution 8 bits UART baud rate (typ) 57.6K bps Number of I/O (max) 24 Package QFP64 External EEPROM and internal RAM facilitates debugging and code development Pin compatible with OTP ROM version Description IRMCF341 is a high performance RAM based motion control IC designed primarily for appliance applications. IRMCF341 is designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control. IRMCF341 contains two computation engines. One is the Motion Control Engine (MCETM) for sensorless control of permanent magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one monolithic chip. The MCETM contains a collection of control elements implemented in hardware such as Proportional plus Integral, Vector rotator, Angle estimator, Multiply/Divide, Low loss SVPWM and Single Shunt IFB. The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the complex sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique analog/digital circuit and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-cycle instruction execution (60MIPS at 120MHz). The MCE and 8051 microcontroller are connected via dual port RAM for signal monitoring and command input. An advanced graphic compiler for the MCETM is seamlessly integrated into the MATLAB/Simulink environment, while third party JTAG-based emulator tools are supported for 8051 software developments. IRMCF341 comes in a small QFP64 pin package. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCF341 1 Overview IRMCF341 is a new International Rectifier integrated circuit device primarily designed as a onechip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCF341 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCETM) for permanent magnet motors. The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCF341 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using the IRMCF341. IRMCF341 contains 48K bytes of program RAM, which can be loaded from external EEPROM for 8051 program execution. The IRMCF341 is intended for development purposes. For high volume production, the program RAM is replaced with 64K bytes of OTP ROM. Both the development and ROM versions come in a 64-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass production. Appliance Inverter Passive EMI Filter HVIC Gate Drive & Protection Circuit Multiple Output Power Supply 1.8 V PMSM IRMCF341 3.3 V 7 Analog Input Up to 24 Digital Input/Output I2C Interface to EEPROM UART interface to Front Panel Figure 1. Typical Application Block Diagram Using IRMCF341 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 2 IRMCF341 2 IRMCF341 Block Diagram and Main Functions IRMCF341 block diagram is shown in Figure 2. 8051 Microcontroller 3 Monitoring MCE (Motion Control Engine) D/A (PWM) Timer/ Counter 0,1,2 Low Loss Space Vector PWM Capture Timer Host Interface 2/4 Program RAM 48KB 2 I C / SPI 2 UART (8) Local RAM 2KB* PORT 1 (8) Digital I/Os PORT 2 (5) Crystal (4MHz) 4 MCE Code RAM 4KB* * Sizes are configurable PLL Single Shunt Current Reconstruction 3 Single Shunt AIN0 AIN1 A/D MUX S/H AIN2 AIN3 AIN4 AIN5 AIN6 Motion Control Sequencer PORT 5 JTAG 2 Motion Control Modules Interrupt Control PORT 3 Emulator Debugger Dual Port RAM 2KB* Motion Control Bus EEPROM Interface 8-bit uP Address/Data Bus Periodic Timer To IGBT Gate Drive GateKill 8 bit CPU Core Watchdog Timer 6 120MHz Figure 2. IRMCF341 Internal Block Diagram IRMCF341 contains the following functions for sensorless AC motor control applications: • Motion Control Engine (MCETM) o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 3 IRMCF341 • o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect o Transition o Multiply-divide (signed and unsigned) o Divide (signed and unsigned) o Adder o Subtractor o Comparator o Counter o Accumulator o Switch o Shift o ATAN (arc tangent) o Function block (any curve fitting, nonlinear function) o 16 bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) o MCETM program memory and dual port RAM (6K byte) o MCETM control sequencer 8051 microcontroller o Three 16 bit timer/counters o One 16 bit periodic timer o One 16 bit watchdog timer o One 16 bit capture timer o Up to twenty discrete I/Os o Eight-channel 12 bit A/D Buffered (current sensing) one channel (0 – 1.2V input) Unbuffered seven channels (0 – 1.2V input) o JTAG port (4 pins) o Up to three channels of analog output (8 bit PWM) o UART o I2C/SPI port o 48K byte program RAM loaded from external EEPROM o 2K byte data RAM This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 4 IRMCF341 P3.1/AOPWM2 P3.2/INT0 P3.3/INT1 P3.5/T1 VSS VDD1 SCL/SO-SI SDA/CS0 P5.1/TMS P5.2/TDO P5.3/TDI TCLK VSS RESET PLLVDD PLLVSS 3 Pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 XTAL0 1 48 P3.0/INT2/CS1 XTAL1 2 47 PWMUH P1.0/T2 3 46 PWMUL P1.1/RXD 4 45 PWMVH P1.2/TXD 5 44 PWMVL P1.3/SYNC/SCK 6 43 PWMWH P1.4/CAP 7 42 PWMWL P1.5 8 41 GATEKILL P1.6 9 40 VDD1 P1.7 10 39 VSS VDD2 11 38 VDD2 VSS 12 37 AIN6 VDD1 13 36 AIN5 P2.0/NMI 14 35 AIN4 P2.1 15 34 AIN3 P2.2 16 33 AIN2 IRMCF341 (Top View) IFBO IFB+ IFB- AREF CMEXT AIN1 AVSS AVDD AIN0 VSS VDD2 P2.6/AOPWM0 P2.7/AOPWM1 P2.5 P2.4 P2.3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. IRMCF341 Pin Configuration This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 5 IRMCF341 4 Application Connections Typical application connection is shown in Figure 4. All components necessary to implement a complete sensorless drive control algorithm are shown connected to IRMCF341. System Clock XTAL0 XTAL1 4MHz Crystal PLLVDD 1.8V PLLVSS Host Microcontroller (UART) Other Communication (I2C or SPI) P1.2/TXD P1.1/RXD System clock PWMUH PWMUL PWMVH UART SDA/CS0 SCL/SO-SI 3.3V PLL Logic Dual Port Memory (2KB) & MCE Code Memory (4KB) I2C/SPI P1.0/T2 P1.3/SYNC/SCK P1.4/CAP P1.5 P1.6 P1.7 PORT1 P2.0/NMI P2.1 P2.2 P2.3 P2.4 P2.5 Digital I/O Control Motion Control Modules Low Loss Space Vector PWM Washer IGBT Gate Drive (i.e.IRS2631D) PWMVL PWMWH PWMWL GATEKILL Motion Control Sequencer PORT2 IFBC+ P3.0/INT2/CS1 P3.2/INT0 P3.3/INT1 P3.5/T1 S/H PORT3 P2.6/AOPWM0 P2.7/AOPWM1 Analog Output P3.1/AOPWM2 Timers AIN0 PWM2 DC bus voltage AIN1 PWM0 Local RAM (2KB) Motor DC bus shunt resistor IFBCIFBCO Watchdog Timer PWM1 0.6V 12bit A/D & MUX AIN2 AIN3 Other analog input (0-1.2V) AIN4 AIN5 TSTMOD Test Mode RESET 3.3V 1.8V Program RAM (48KB) TCLK P5.3/TDI P5.1/TSM P5.2/TDO JTAG Control Test Mode Circuit VDD1 VDD2 VSS JTAG Port Interface 5 RESET System Reset 8051 CPU AIN6 AREF CMEXT Optional External Voltage Reference (0.6V) AVDD 1.8V AVSS IRMCF341 Figure 4. Application Connection of IRMCF341 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 6 IRMCF341 5 Package Dimensions Figure 5. Package Drawing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 7 IRMCF341 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 http://www.irf.com Data and specifications subject to change without notice. 5/26/2006 Sales Offices, Agents and Distributors in Major Cities Throughout the World. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 8