IRF IRMCK201

Data Sheet No. PD60224 Rev.B
IRMCK201
High Performance Configurable Digital AC
Servo Control IC
Features
Product Summary
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Complete closed loop current control
(Synchronously Rotating Frame Field Orientation)
Max. Clock Input (Sysclk)
Versatile Space Vector PWM
Max. PLL clock for current feedback
Direct interface to IR2175 current sensing high
voltage IC
Closed loop current control computation time 6 µsec max
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Direct Encoder interface with multiplexed/nonmultiplexed Hall A/B/C signals
Direct interface to IR213x 3-phase gate driver IC
Closed loop velocity control
Fast SPI interface
133.3 MHz
Closed loop current loop bandwidth (-3 dB)
Closed loop velocity loop update rate
PWM carrier frequency
PWM counter resolution
Configurable architecture
o Supports AC PM motor or Induction motor
Current feedback temp drift/offset
o Closed loop or open loop control
Asynchronous serial communication interface
(RS232C, RS422)
33.3 MHz
Max SPI clock
5.5 kHz
5 / 10 kHz
83.3 kHz max
12 bit
calibrated
8 MHz
Package: QFP100
4 channel 12-bit A/D interface with simultaneous
sample/hold
8-bit parallel bus interface for microcontroller
expansion (supports most 8-bit microprocessors)
Integrated brake IGBT control
TM
ServoDesigner
(Configuration Tool) available
Description
IRMCK201 is a complete AC servo motor control IC. It contains closed loop current control for sinusoidal AC current, and
closed loop velocity control based on encoder position feedback interface. A standard communication port is provided for
RS232C or RS422, in addition to a fast SPI communication interface. Unlike a traditional DSP or a microcontroller, the
IRMCK201 does not require any programming effort to complete the complex control algorithm. It allows users to configure
the algorithm for specific application needs. Permanent magnet motor or AC induction motor are supported. IRMCK201
facilitates high performance servo design together with the IR2175 current sensing IC and IR213x high voltage 3-phase gate
driver IC, which simplifies the hardware design while minimizing cost. For multi-axis applications, IRMCK201 can be used
as a multi-drop slave drive based on the SPI protocol. The package is available in a 100-pin QFP.
IRMCK201
Overview
IRMCK201 is a new International Rectifier integrated circuit device designed as a one-chip solution for complete
closed loop current control and velocity control for a high performance servo drive system. Unlike a traditional
microcontroller or DSP, IRMCK201 does not require any programming to complete complex AC servo algorithm
development. Combined with International Rectifier's high voltage gate drive and current sensing IC, the user can
implement a complete AC servo control with minimum component count and virtually no design effort. Although
IRMCK201 contains dedicated logic to perform closed loop control of AC current and velocity, it has a wide range of
application coverage through its flexible configuration ability. The drive can be easily configured for induction
machine closed loop vector control or permanent magnet motor servo drive. Rich motion peripherals, analog and
digital I/O can also be configured. Host communication logic contains an asynchronous RS232C or RS422
communication interface, a fast slave SPI interface and an 8-bit-wide Host Parallel Interface. All communication ports
have the same access capability to the host register set. The user can write to and read from the predefined registers to
configure and monitor the drive through these communication ports.
IRMCK201 Main Features
IRMCK201 contains the following functions for AC servo motor control applications:
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Complete closed loop current control based on Synchronously Rotating Frame Field Orientation
Configurable update rate with PWM carrier frequency
Configurable parameters (all PI controller gains, PI output limit range, current feedback scaling, encoder
feedback scaling)
Configurable control structure for Induction machine or AC Permanent Magnet machine (Disable/enable slip
gain)
Closed loop velocity control with configurable update rate
Enable/disable velocity loop
Selectable reference input for torque and speed input
Analog reference input
RS232C/RS422 reference input
Dynamic braking control for excess DC bus voltage
Cycle-by-cycle on/off Control for Brake IGBT
DC bus voltage feedback
Standard Encoder interface with Hall ABC support
A/B quadrature signal input up to 1 MHz
Choice of separate or multiplexed Hall A/B/C signal input
Auto-initialization with Hall A/B/C plus Z pulse input
Adaptable for any line count encoder from 200 PPR to 10,000 PPR
1/T counter (1 MHz) for low speed performance improvement
Space Vector PWM with deadtime insertion
IR2175 current sensing IC interface
IR213x high voltage gate driver IC interface
Low cost serial 12 bit A/D interface with multiplexer and sample/hold circuit
4 channel analog output by PWM
0-3.3 V, 120 kHz output
EEPROM for startup initialization of internal data/parameters through host register interface
AT24C01A, 128 x 8
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2
IRMCK201
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Versatile host communication interface
RS232C or RS422 host interface
Fast SPI slave host interface with multi-drop capability
Parallel Host interface (total 12 pins)
Multiplexed data/address bus
Address Enable
RD/WR
Discrete I/O
Start (Input)
Stop (Input)
IFBCAL (Input)
Fault Clear (Input)
Fault (Output)
SYNC (Output)
PWM Active (Output)
LED
Two-bit bi-color
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
3
IRMCK201
Table of Contents
Overview .......................................................................................................................................................................... 2
IRMCK201 Main Features ............................................................................................................................................ 2
IRMCK201 Block Diagrams .......................................................................................................................................... 7
Basic Block Diagram .................................................................................................................................................... 7
Detailed Block Diagram................................................................................................................................................ 8
Input/Output of IRMCK201 .......................................................................................................................................... 9
Typical Application Connections................................................................................................................................. 13
IC Crystal Clock Circuitry .......................................................................................................................................... 14
Low Pass Filter............................................................................................................................................................ 15
Implementing the Low Pass Filter Shield ............................................................................................................... 16
Cp Rp and Cs Component Values........................................................................................................................... 16
PLL Reset.................................................................................................................................................................... 16
DC Electrical Characteristics and Operating Conditions ......................................................................................... 17
Absolute Maximum Ratings........................................................................................................................................ 17
Recommended Operating Conditions ......................................................................................................................... 17
DC Characteristics ...................................................................................................................................................... 18
Common Quiescent and Leakage Current .................................................................................................................. 18
Input Characteristics – Non Schmitt Trigger Inputs ................................................................................................... 18
Input Characteristics – Schmitt Trigger Inputs ........................................................................................................... 18
Output Characteristics................................................................................................................................................. 18
Output Characteristics OSC2CLK .............................................................................................................................. 19
Pin and I/O Characteristic Table ................................................................................................................................. 20
Power Consumption .................................................................................................................................................... 22
AC Electrical Characteristics and Operating Conditions ......................................................................................... 23
System Level AC Characteristics................................................................................................................................ 23
Sync Pulse to Sync Pulse Timing............................................................................................................................ 23
FAULT and REDLED Response to GATEKILL ................................................................................................... 24
Host Interface AC Characteristics............................................................................................................................... 25
SPI Timing .............................................................................................................................................................. 25
Host Parallel Timing ................................................................................................................................................... 26
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4
IRMCK201
Host Parallel Read Cycle......................................................................................................................................... 26
Host Parallel Write Cycle........................................................................................................................................ 27
Discrete I/O Electrical Characteristics ........................................................................................................................ 28
Motion Peripheral Electrical Characteristics............................................................................................................... 29
PWM Electrical Characteristics .............................................................................................................................. 29
IR2175 Interface ..................................................................................................................................................... 29
Encoder Electrical Characteristics........................................................................................................................... 30
Analog To Digital Interface Electrical Characteristics ............................................................................................... 31
ADC Timing............................................................................................................................................................ 31
PLL Interface Electrical Characteristics...................................................................................................................... 33
Appendix A
Host Register Map ............................................................................................................................... 34
Host Parallel Access................................................................................................................................................ 34
SPI Register Access ................................................................................................................................................ 34
RS-232 Register Access.......................................................................................................................................... 34
Write Register Definitions .......................................................................................................................................... 40
QuadratureDecode Register Group (Write Registers)............................................................................................. 40
PwmConfig Register Group (Write Registers) ....................................................................................................... 41
CurrentFeedbackConfig Register Group (Write Registers) .................................................................................... 42
SystemControl Register Group (Write Registers)................................................................................................... 43
CurrentLoopConfig Register Group (Write Registers) ........................................................................................... 44
VelocityControl Register Group (Write Registers)................................................................................................. 45
FaultControl Register Group (Write Registers) ...................................................................................................... 47
SVPWMScaler Register Group (Write Registers) .................................................................................................. 47
DiagnosticPwmControl Register Group (Write Registers) ..................................................................................... 48
SystemConfig Register Group (Write Registers).................................................................................................... 49
DirectHostVoltageControl Register Group (Write Registers) ................................................................................ 49
32bitQuadDecode Register Group (Write Registers).............................................................................................. 50
EepromControl Registers (Write Registers)............................................................................................................ 51
HallSensorEncoderInit (Write Registers – EEPROM only) ................................................................................... 52
Read Register Definitions ........................................................................................................................................... 53
QuadratureDecodeStatus Register Group (Read Registers).................................................................................... 53
SystemStatus Register Group (Read Registers) ...................................................................................................... 53
DcBusVoltage Register Group (Read Registers) .................................................................................................... 54
FocDiagnosticData Register Group (Read Registers)............................................................................................. 54
FaultStatus Register Group (Read Registers).......................................................................................................... 56
VelocityStatus Register Group (Read Registers) .................................................................................................... 56
CurrentFeedbackOffset Register Group (Read Registers) ...................................................................................... 57
32bitQuadDecodeStatus Register Group (Read Registers)..................................................................................... 57
EepromStatus Registers (Read Registers)............................................................................................................... 58
FOCDiagnosticDataSupplement Register Group (Read Registers) ........................................................................ 59
Appendix B
Package ................................................................................................................................................. 60
Appendix C
Errata.................................................................................................................................................... 62
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IRMCK201
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Basic Block Diagram of IRMCK201............................................................................................................. 7
Detailed Block Diagram of IRMCK201 ........................................................................................................ 8
Input/Output of IRMCK201 .......................................................................................................................... 9
Typical Connection of IRMCK201.............................................................................................................. 13
Oscillator Circuit.......................................................................................................................................... 14
PLL Low Pass Filter Shielding .................................................................................................................... 15
System Level SYNC-to-SYNC Timing ....................................................................................................... 23
FAULT and REDLED Response to GATEKILL ........................................................................................ 24
SPI Timing ................................................................................................................................................... 25
Host Parallel Read Cycle Timing............................................................................................................... 26
Host Parallel Write Cycle Timing.............................................................................................................. 27
Discrete I/O Timing ................................................................................................................................... 28
PWM Timing ............................................................................................................................................. 29
IR2175 Interface ........................................................................................................................................ 29
Encoder Timing ......................................................................................................................................... 30
Top Level ADC Timing............................................................................................................................. 31
ADC Specific Timing ................................................................................................................................ 32
List of Tables
Table 1: Typical Values for the Clock Circuit ................................................................................................................ 14
Table 2: PLL Test Pin Assignments................................................................................................................................ 15
Table 3: PLL Low Pass Filter Values ............................................................................................................................. 16
Table 4: Absolute Maximum Ratings ............................................................................................................................. 17
Table 5: Recommended Operating Conditions ............................................................................................................... 17
Table 6: DC Characteristics ............................................................................................................................................ 18
Table 7: Non Schmitt Trigger Input Characteristics ....................................................................................................... 18
Table 8: Schmitt Trigger Input Characteristics ............................................................................................................... 18
Table 9: Output Characteristics....................................................................................................................................... 18
Table 10: Output Characteristics OSC2CLK .................................................................................................................. 19
Table 11 .......................................................................................................................................................................... 20
Table 12: Pin and I/O Characteristics ............................................................................................................................. 22
Table 13: IRMCK201 Power Consumption.................................................................................................................... 22
Table 14: System Level SYNC-to-SYNC Timing .......................................................................................................... 24
Table 15: FAULT and REDLED Response to GATEKILL ........................................................................................... 24
Table 16: SPI Timing ...................................................................................................................................................... 25
Table 17: Host Parallel Read Cycle Timing.................................................................................................................... 26
Table 18: Host Parallel Write Cycle Timing................................................................................................................... 27
Table 19: Discrete I/O Timing ........................................................................................................................................ 28
Table 20: PWM Timing .................................................................................................................................................. 29
Table 21: IR2175 Interface ............................................................................................................................................. 29
Table 22: Encoder Timing .............................................................................................................................................. 30
Table 23: Top Level ADC Timing.................................................................................................................................. 31
Table 24: ADC Specific Timing ..................................................................................................................................... 32
Table 25: PLL Electrical Characteristics......................................................................................................................... 33
Table 26: QFP100 Package............................................................................................................................................. 60
Table 27: QFP100 Dimensions ....................................................................................................................................... 61
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6
IRMCK201
IRMCK201 Block Diagrams
Basic Block Diagram
Figure 1 shows the basic block diagram of the IRMCK201 surrounded by various Accelerator ICs. Host
communications are provided over SPI, RS-232C or Host parallel ports. Two current sensing ICs (IR2175) and a
three phase high voltage gate drive typically implement the high voltage / current interface between the IRMCK201 IC
and motor.
The IRMCK201 can operate in a “stand-alone” mode without the host controller.
utilized to load motor-specific parameters into the IC.
A serial EEPROM could be
AC Power
EEPROM
IRMCK201
Multi-Axis
Host
other host
controller
+
+
-
Host
Register
Interface
jθ
-
e
+
Space
Vector
PWM
A/D
MUX
DC bus feedback
IGBT
module
BRAKE
IRAMX16UP60A
Dead
time
IR2136
or
select
A/D
interface
DC bus dynamic
brake control
RS232C
or
RS422
SPI
Interface
Analog Speed
Reference
TM
iMOTION Chip Set
FAULT
Parallel
Interface
Configuration
Registers
Ks
+
dt
+
Monitoring
Registers
jθ
e
1/T counter
speed
measurement
2/3
Period/Duty
counters
IR2175
Period/Duty
counters
IR2175
Quadrature
Decoding
Encoder
Figure 1.
Motor
Basic Block Diagram of IRMCK201
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7
IRMCK201
Detailed Block Diagram
Figure 2 shows a detailed block diagram or the IRMCK201. All logic and algorithms are pre-programmed, and the
user does not need to make any effort to develop code, alleviating the tedious design process. If needed, the user can
configure the drive to tailor the control per specific needs to meet the required specification. This configuration is
easily done by accessing the host register set through the communication interface.
Closed Loop Velocity Control, Sequencing Control
Update Rate = PWM carrier frequency / 2
EXT_REF
O
I1 x I2
I1
I3 I3
I2
Feedforward
path enable
REF scale
SPDKI
VQLIM
Sequence
Control
SYNC
RAMP
+
-
IDREF
IQLIM+
RS232C/
RS422
Interface
+
SPI
Slave
Interface
SDI
CS
e
Space Vector
PWM
VDS
Dea
d
time
- VDLIM
VD enable
VDLIM
Slip gain
4096
I2
I3
I1
I1 x I2
I3
Host Register
Interface
Parallel
Interface
Monitoring
Registers
SpdScale
+
dt
O
InitZval
3
+
Quadrature
Decoding
ID
3
IQ scale
4096
I2
I3
O
O
I1 x I2
I3
I1
I1 x I2
I1
I3 I3
ID scale
EncType
InitZ
Optional
CurrentSense
jθ
e
2/3
+/-4095 = +/-rated ID for IM field flux
Encoder
A/B/Z
Encoder
Hall A/B/C
Zpol
IV
IR2175
interface
Motor
Phase
Current V
IW
IR2175
interface
Motor
Phase
Current W
Current
Offset W
4096
+/-16383 = +/-4X of rated current for IQ
Figure 2.
FAULT
PWMmode
2Pen
Dtime
PWMen
AngleScale MaxEncCount
Slip gain
enable
I2
Communication Modules
Gate
Signals
INT_VD
IQ
17
BRAKE
6
VQS
jθ
VD
PI
-
Configuration
Registers
VQ
0
SCK
SDO
Data
Address
Control
+
PI
-
Decel
Rate
RTS
CTS
DATA
GSenseL
GSenseU
ModScl
CURKP
+
PI
IQLIMAccel Rate
FAULT
PWM ACTIVE
RCV
SND
8 channel
Serial
A/D
Interface
+
Reference
Select
STOP
DIR
FLTCLR
CNVST
CLK
DC bus dynamic
brake control
- VQLIM
CURKI
IQREF
INT_REF
START
2
Optional
Current Sense
4096
Velocity
Control
Enable
SPDKP
MUX
ADS7818
A/D
interface
DCV_FDBK
+/-16383 = +/-max_speed
INT_VQ
2
Closed Loop Current Control
Update Rate = PWM carrier frequency x1 or x 2
INT_DAC1
INT_DAC2
INT_DAC3
Current
Offset V
DAC_PWM1
4ch
DAC module
INT_DAC4
DAC_PWM2
DAC_PWM3
DAC_PWM4
Detailed Block Diagram of IRMCK201
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8
IRMCK201
Input/Output of IRMCK201
Figure 3 shows the interface signals divided into sub-groups. For detailed pin assignment, please refer to Table 12
in this data sheet.
PLL
&
System Clock
SYSCLK
RESETN
PWMUH
PWMUL
XPD
BYPASSMODE
BYPASSCLK
OSC1CLK
OSC2CLK
PWMVH
PWMVL
PWMWH
PWMWL
BRAKE
PLLTEST
CHGO
LPVSS
GATEKILL
IFB0
IFB1
SCLK
MISO
MOSI
CSN
Host
Communication
Interface
PWM gate signal
Interface
ENA
ENB
ENZ
HALLA
HP_nOE
HP_nWE
IRMCK201
HP_D[0-7]
HP_A
IR2175 Interface
Encoder Interface
HALLB
HALLC
HP_nCS
TX
RX
BAUDSEL
SYNC
ADCLK
ADOUT
ADCOVST
ADMUX0
ADMUX1
Discrete I/O
Serial EEPROM
START
STOP
IFBCAL
FLTCLR
PWMACTIVE
FAULT
A/D Interface
RESSAMPLE
REDLED
GREENLED
PID[0-1]
SCA
SCL
Figure 3.
LED
POWER ID
Input/Output of IRMCK201
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9
IRMCK201
Host Interface Group
SCLK
I
MISO
MOSI
CSN
HP_nOE
O
I
I
I
Low (L) /
High (H) True
Asserted
Positive edge
sensitive
L
L
HP_nWE
I
L
I/O
-
HP_A
I
H
HP_nCS
TX
RX
I
O
I
L
-
BAUDSEL
I
H
SYNC
O
L
Signal
HP_D [7:0]
Input (I) /
Output (O)
Function
SPI clock
Master input and slave output
Master output and slave input
SPI chip select
Parallel data output enable
Parallel data write cycle
identification
Parallel data
Parallel data address cycle
identification
Chip select
RS-232 data out
RS-232 data in
RS-232 baud rate: 0 = 57,600; 1
= 1,031,250 bps
Start of PWM cycle
Discrete I/O Group
Signal
IFBCAL
START
STOP
FLTCLR
PWMACTIVE
FAULT
Input (I) /
Output (O)
I
I
I
I
O
O
Low (L) /
High (H) True
Asserted
H
H
H
H
H
H
Function
Current offset calibration signal
Start command
Stop command
Fault clear command
PWM state
Fault state
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10
IRMCK201
Motion Peripheral Group
Signal
Input (I) /
Output (O)
PWMUH
PWMUL
PWMVH
PWHVL
PWMWH
PWMWL
BRAKE
O
O
O
O
O
O
O
GATEKILL
I
IFB0
IFB1
ENA
ENB
ENZ
HALLA
HALLB
HALLC
I
I
I
I
I
I
I
I
Low (L) /
High (H) True
Asserted
Varies, Based on
Write Register
0x0D
L
Varies, Based on
Write Register
0x0C Bit 7
-
Function
PWM phase U high side
PWM phase U low side
PWM phase V high side
PWM phase V low side
PWM phase W high side
PWM phase W low side
IGBT gate
When asserted, negates all six
PWM signals, host writeable
Channel 0 (phase V)
Channel 1 (phase W)
Encoder A
Encoder B
Encoder Z
Hall A
Hall B
Hall C
Analog Interface Group
Signal
Input (I) /
Output (O)
ADCLK
O
ADOUT
DAC [3:0]
ADCONVST
ADMUX0
ADMUX1
I
O
O
O
O
Low (L) /
High (H) True
Asserted
Negative Edge
Sensitive
L
H
H
Function
Clock to ADS7818
Serial data from ADS7818
Diagnostic DAC
Conversion start to ADS7818
Analog input mux select
Analog input mux select
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11
IRMCK201
PLL Interface Group
XPD
RESETN
I
I
Low (L) /
High (H) True
Asserted
L
L
BYPASSCLK
I
H
BYPASSMODE
I
H
OSC1CLK
OSC2CLK
I
I
-
PLLTEST
I
H
I/O
I/O
-
Signal
CHGO
LPVSS
Input (I) /
Output (O)
Function
PLL reset
Digital logic reset
Internal test pin – force to logic
low
Internal test pin – force to logic
low
33.33 MHz crystal input
33.33 MHz crystal input
Internal test pin – force to logic
low
Low pass filter
Low pass filter ground
Miscellaneous Group
Signal
Input (I) /
Output (O)
Low (L) /
High (H) True
Asserted
Varies, Based on
Write Register
0x0C Bit 1
Positive Edge
Sensitive
SD
O
SCA
I/O
SCL
O
PID[0:1]
I
-
GREENLED
REDLED
O
O
H
H
Function
Shut down, host writeable
EEPROM data
EEPROM clock
Power ID to SystemStatus
register, host readable
LED signal
LED signal
Power Supply Group
Signal
LVDD
AVCC
MVDD
VSSHC
Function
IC Logic +3.3V power supply
IC Analog +3.3V power supply
IC Phase +3.3V Lock Loop power supply
IC Phase Lock Loop power supply return
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12
IRMCK201
Typical Application Connections
Typical application connection is shown in Figure 4. In order to complete a high performance servo drive control,
all necessary components are shown in connection to IRMCK201.
System Clock
SYSCLK
33MHz
Crystal
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
BRAKE
SCLK
MISO
MOSI
CSN
SPI Interface
TX
RX
To PC
RS232C
FAULTCLR
BAUDSEL
8051
uP
Gate Drive
or
Intelligent IGBT
power module
(IRAMX16UP60A)
Isolator
5V
GATEKILL
MAX232A
Optional
Microcontroller
Isolator
Isolator
Isolator
Isolator
Isolator
Isolator
Isolator
Isolator
5V
PARALLEL DATA
CONTROL SIGNALS
IFB0
Isolator
PO
IR2175
PO
IR2175
5V
START
STOP
IFBCAL
FLTCLR
PWMACTIVE
SYNC
Input
Switches
IFB1
Anaog reference input
DC bus voltage
IRMCK201
Serial EEPROM
AT24C01A
Isolator
SCA
SCL
ADCLK
ADOUT
ADCONVST
1/4
ADS7818
4066
4052
REDLED
GREENLED
PID[0-1]
Bi-Color
LED
Motor Current
Sensing
1/4
4066
Optional Current
sensing
Optional Current
sensing
ADMUX0
ADMUX1
RESSAMPLE
HALLA
HALLB
HALLC
ENA
ENB
ENZ
Analog Output
DS3486
Encoder Interface
DS3486
DAC0
DAC1
DAC2
DAC3
DS3486
Figure 4.
Typical Connection of IRMCK201
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13
IRMCK201
IC Crystal Clock Circuitry
The clock input to the IC is a 33.33 MHz crystal oscillator.
required to terminate the crystal to the IC.
Two shunt capacitors and possibly a series resistor is
The values of the R/C will vary based on actual PCB attributes, and some empirical analysis may be required to get the
PLL to start oscillating. Once oscillating, verify that the signal waveforms at the OSC1CLK and OSC2CLK pins are
sinusoidal rather than trapezoidal. Refer to Table 1 for suggested R/C values. Most low-cost crystals can be used
in this application. An example is a Citizen Part number CM309B33.333MABJT available from Digi-Key under
part number 300-4160-1-ND.
OSC1CLK
IRMCK201
C1
XTAL
R2
OSC2CLK
R1
C2
Figure 5.
Component
XTAL
C1
C2
R1
R2
Oscillator Circuit
Value
33.33
5
5
0
3.9K
Units
MHz
pF
pF
Ω
Ω
Table 1: Typical Values for the Clock Circuit
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14
IRMCK201
PLL Clock Circuitry
The IRMCK201 contains a PLL that creates a 2X and 4X clock from the input 33.33 MHz input clock pin. There
are a number of pins on the IC allocated for factory testing purposes, which need to be left unconnected. Table 2
shows required PCB signal connections for these pins. Note that N/C is for factory use only.
Pin Number
1
2
7
15
16
17
18
23
24
25
41
45
56
89
PCB Connection
VSS
VSS
VSS
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Table 2: PLL Test Pin Assignments
Low Pass Filter
The low pass filter for this PLL resides between the CHGO and LPVSS pins. Three passive components are
required to implement this filter: Cp, Rp and Cs. Figure 6 shows how to place these components around the IC.
A shield should be placed below Rp, Cp and Cs made out of copper etch.
Shielded by LPVSS
CHGO
Rp
IRMCK201
Cs
Cp
LPVSS
Figure 6.
PLL Low Pass Filter Shielding
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
15
IRMCK201
Implementing the Low Pass Filter Shield
Make all connections between CHGO, Rp, Cp, Cs and LPVSS as short as possible. Create the underlining shield by
“copper filling” a larger area in the signal plane of the PCB. Connect this shield to the LPVSS pin of the IC. Do
not connect this shield to signal ground (VSS).
Cp Rp and Cs Component Values
For a typical FR4 PCB, the values of the passive components are shown in Table 3.
Component
Rp
Cp
Cs
Value
3.9K
1000
Not Installed
Units
Ω
pF
-
Table 3: PLL Low Pass Filter Values
PLL Reset
There are two reset pins on the IC, XPD and RESETN both low true. XPD holds the PLL circuitry in reset when
low. Upon XPD going high, the PLL circuitry begins to lock onto the 33.33 MHz clock input. The PLL circuit
may take up to 1 ms to become stable. RESETN asserted low holds the internal DSP logic in reset. Upon
RESETN going high, the IC digital logic becomes active.
RESETN should be held low during and at least 1 ms after XPD goes high false to hold the internal DSP logic in reset
while the PLL becomes stable.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
16
IRMCK201
DC Electrical Characteristics and Operating Conditions
Absolute Maximum Ratings
Note: VSS = 0 Volt
PARAMETER
SYMBOL
Power Supply
Voltage
VDD
Input Voltage
UNIT
S
LIMITS
VSS-0.3 to 4.0
V
VSS-0.3 to VDD+0.5
V
VSS-0.3 to 7
V
VSS-0.3 to VDD+0.5
V
NOTE
Non 5 Volt
Tolerant Pins
Only on 5 Volt
Tolerant Pins
VI
Output Voltage
Output Current
per Pin
Storage
Temperature
VO
IOUT
Tstg
+/- 30
mA
-65 to 150
°C
Table 4: Absolute Maximum Ratings
Recommended Operating Conditions
Note: VSS = 0 Volt
PARAMETER
Power Supply
Voltage
SYMBOL
MIN
TYP
MAX
UNITS
VDD
3.0
3.3
3.6
V
VDD
V
Input Voltage
VI
VSS
-
5.5
V
Ambient
Temperature
Ta
-40
-
85
°C
NOTE
Non 5 Volt Tolerant Pins
Only on 5 Volt Tolerant
Pins
Note 1
Table 5: Recommended Operating Conditions
Notes:
1. The ambient temperature range is recommended for Tj = -40 to 125 °C
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
17
IRMCK201
DC Characteristics
Common Quiescent and Leakage Current
PARAMETER
SYMBOL
Quiescent
Current
IDDS
Input Leakage
Current
ILI
CONDITIONS
VI=VDD or VSS
VDD=MAX
IOH=IOL=0
Ta=Tj=85°C
VDD=MAX
VIH=VDD
VIL=VSS
MIN
TYP
MAX
UNITS
-
-
0.35
uA
-1
-
1
uA
Table 6: DC Characteristics
Input Characteristics – Non Schmitt Trigger Inputs
PARAMETER
High Level
Input Voltage
Low Level
Input Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VIH1
VDD=MAX
2.0
-
-
V
VIL1
VDD=MIN
-
-
0.8
V
Table 7: Non Schmitt Trigger Input Characteristics
Input Characteristics – Schmitt Trigger Inputs
PARAMETER
High Level
Input Voltage
Low Level
Input Voltage
Hysteresis
Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VT1+
VDD=MAX
1.1
-
2.4
V
VT1-
VDD=MIN
0.6
-
1.8
V
VH1
VDD=MIN
0.1
-
-
V
Table 8: Schmitt Trigger Input Characteristics
Output Characteristics
PARAMETER
High Level
Output Voltage
Low Level
Output Voltage
SYMBOL
VOH3
VOL3
CONDITIONS
VDD=MIN
IOH=-12mA
VDD=MIN
IOH = 12mA
MIN
TYP
MAX
UNIT
S
VDD - 0.4
-
-
V
-
-
VSS + 0.4
V
Table 9: Output Characteristics
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
18
IRMCK201
Output Characteristics OSC2CLK
PARAMETER
High Level
Output Voltage
Low Level
Output Voltage
SYMBOL
LVOH
LVOL
CONDITIONS
VDD=MIN
IOH=-530uA
VDD=MIN
IOH = 730uA
MIN
VDD - 0.4
TYP
-
MAX
-
UNITS
V
-
-
VSS + 0.4
V
Table 10: Output Characteristics OSC2CLK
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
19
IRMCK201
Pin and I/O Characteristic Table
Pin
Number
Pin Name
1
BYPASSMODE
2
BYPASSCLK
3
4
5
6
OSC1CLK
LVDD
OSC2CLK
VSS
7
PLLTEST
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
XPD
VSSHC
MVDD
VSSHC
AVDD
CHGO
LPVSS
N.C. (CLKI)
N.C. (CLKSEL)
N.C. (CPT0)
N.C. (CPT1)
LVDD
REDLED
GREENLED
VSS
N.C. (TSTCLK)
N.C. (TSTSEL)
N.C. (OLAP)
PWMWL
PWMWH
PWMVL
LVDD
PWMVH
PWMUL
VSS
PWMUH
BRAKE
35
RESETN
36
FLTCLR
37
GATEKILL
38
39
IFB0
IFB1
INTERNAL IC
RESISTOR
TERMINATION
40K-240K Pull
Down
40K-240K Pull
Down
20K-120K Pull
Down
20K -120K Pull
Up
20K -120K Pull
Up
Pin
Type
5.50 VOLT
TOLERANT
INPUT
INPUT DC
CHARACTERISTIC
TABLE
OUTPUT DC
CHARACTERISTIC
TABLE
I
-
Table 8
-
I
-
Table 8
-
I
P
O
P
-
Table 7
-
Table 11
-
I
-
Table 7
-
I
P
P
P
P
O
P
I
I
I
I
P
O
O
P
I
I
I
O
O
O
P
O
O
P
O
O
-
Table 7
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
-
Table 9
Table 9
Table 9
Table 9
Table 9
Table 9
Table 9
Table 9
Table 9
I
-
Table 8
-
O
-
-
Table 9
I
-
Table 8
-
I
I
YES
YES
Table 8
Table 8
-
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
20
IRMCK201
Pin
Number
Pin Name
40
41
SD
N.C. (D0)
42
PID0
43
PID1
44
45
46
47
48
49
50
51
52
LVDD
N.C. (D3)
CSN
VSS
MOSI
MISO
SCLK
TX
RX
53
BAUDSEL
54
55
56
57
58
59
60
61
62
63
64
LVDD
ADMUX0
N.C. (N2)
VSS
ADMUX1
RESSAMPLE
ADCONVST
ADCLK
ADOUT
SYNC
FAULT
65
START
66
STOP
67
IFBCAL
68
FLTCLR
69
70
71
72
73
74
75
LVDD
PWMACTIVE
DAC[3]
VSS
DAC[2]
DAC[1]
DAC[0]
76
HP_D[0]
77
HP_D[1]
INTERNAL IC
RESISTOR
TERMINATION
20K -120K Pull
Up
20K -120K Pull
Up
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Down
O
I
5.50 VOLT
TOLERANT
INPUT
-
INPUT DC
CHARACTERISTIC
TABLE
Table 8
OUTPUT DC
CHARACTERISTIC
TABLE
Table 9
-
I
-
Table 8
-
I
-
Table 8
-
P
I
I
P
I
O
I
O
I
YES
YES
YES
YES
Table 8
Table 8
-
Table 8
Table 8
Table 8
Table 9
Table 9
-
I
YES
Table 7
-
P
O
I
P
O
O
O
O
I
O
O
YES
-
Table 8
Table 8
-
Table 9
Table 9
Table 9
Table 9
Table 9
Table 9
Table 9
I
YES
Table 8
-
I
YES
Table 8
-
I
YES
Table 8
-
I
YES
Table 8
-
P
O
O
P
O
O
O
-
-
Table 9
Table 9
Table 9
Table 9
Table 9
B
-
Table 7
Table 9
B
-
Table 7
Table 9
Pin
Type
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
21
IRMCK201
Pin
Number
Pin Name
78
HP_D[2]
79
VDD
80
HP_D[3]
81
HP_D[4]
82
VSS
83
HP_D[5]
84
HP_D[6]
85
HP_D[7]
86
87
88
89
90
91
92
93
94
95
96
97
98
99
HP_nOE
HP_nWE
HP_A
N.C. (N11)
HP_nCS
ENCZ
ENCB
ENCA
LVDD
HALLC
HALLB
VSS
HALLA
SCL
100
SDA
INTERNAL IC
RESISTOR
TERMINATION
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Down
20K -120K Pull
Up
Pin
Type
5.50 VOLT
TOLERANT
INPUT
INPUT DC
CHARACTERISTIC
TABLE
OUTPUT DC
CHARACTERISTIC
TABLE
B
-
Table 7
Table 9
P
-
-
-
B
-
Table 7
Table 9
B
-
Table 7
Table 9
P
-
-
-
B
-
Table 7
Table 9
B
-
Table 7
Table 9
B
-
Table 7
Table 9
I
I
I
I
I
I
I
I
P
I
I
P
I
O
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
-
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
-
-
Table 9
B
-
Table 7
Table 9
-
Table 12: Pin and I/O Characteristics
Power Consumption
PARAMETER
PTotal
SYMBOL
PTOTAL
CONDITIONS
VDD=3.3V
MIN
-
TYP
0.927
MAX
-
UNITS
WATT
Table 13: IRMCK201 Power Consumption
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
22
AC Electrical Characteristics and Operating Conditions
System Level AC Characteristics
Sync Pulse to Sync Pulse Timing
-5
-4
-3
-2
-1
0
1
2
4
3
5
6
7
8
t3
SYNC
t1
t2
SAMPLE DELAY
END OF PROCESSING
WAIT FOR NEXT SYNC
PULSE
SPEED LOOP
CURRENT REGULATOR
SPACE VECTOR
MODULATION
Critical Path Timing Including PWM Calculation Time
Figure 7.
System Level SYNC-to-SYNC Timing
SYMBOL
t1
t2
t3
DESCRIPTION
Current Feedback Sample Delay from SYNC Pulse
Falling Edge
Closed Loop Computation Time
(current control only including PWM computation)
Closed Loop Computation Time (current and
velocity control including PWM calculation time)
Minimum SYNC-to-SYNC time
(current control only including PWM calculation
time)
Minimum SYNC-to-SYNC time
(current and velocity control including PWM
calculation time)
TIME
UNITS
4.32
µs
6.33
µs
7.68
10.65
µs
12.0
Table 14: System Level SYNC-to-SYNC Timing
FAULT and REDLED Response to GATEKILL
GATEKILL
t3
t1
FAULT
t2
REDLED
t4
FLTCLR
Figure 8.
SYMBOL
t1
t2
t3
t4
FAULT and REDLED Response to GATEKILL
DESCRIPTION
FAULT Response to GATEKILL
REDLED Response to
GATEKILL
FAULT Response to FLTCLR
REDLED Response to FLTCLR
TYP
685
715
UNITS
ns
ns
145
175
ns
ns
Table 15: FAULT and REDLED Response to GATEKILL
IRMCK201
Host Interface AC Characteristics
SPI Timing
tSCLK
SCLK
CS
tCSS
tMOSIS
MOSI
MISO
tMISO
Figure 9.
SYMBOL
fSCLK
tSCLK
tCSS
tMOSIS
tMISO
tMIOZ
DESCRIPTION
ADC Clock Frequency
ADC Clock Period
CS to SCLK high Setup
MOSI to SCLK low Setup
SCLK to MISO Valid
CS to MISO High Impedance
tMISOZ
SPI Timing
MIN
125
20
20
72
15
MAX
8
35
UNITS
MHz
ns
ns
ns
ns
ns
Table 16: SPI Timing
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
25
IRMCK201
Host Parallel Timing
Host Parallel Read Cycle
tHPCSN
HP_nCS
HP_nWE
tHPWENS
tHPA
HP_A
tHPAS
tAHPD
HP_D[7:0]
tHPOENS
tHPOENH
Figure 10.
tHPCSN
tHPWENS
tHPAS
tAHPD
THPZD
tHPDZ
tHPOENH
tHPOENS
tHPOEN
tHPDZ
tHPOEN
HP_nOE
SYMBOL
VALID
tHPZD
DESCRIPTION
HP_nCS Period
HP_nWE Setup
HP_A Setup
HP_D [7:0] Access
HP_D [7:0] Active
HP_D [7:0] High Impedance
HP_nOE Hold
HP_nOE Setup
HP_nOE Period
Host Parallel Read Cycle Timing
MIN
MAX
70
10
10
60
0
0
10
10
70
105
9
6
UNIT
S
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
Note 3
Note 3
Table 17: Host Parallel Read Cycle Timing
Note:
3. HP_nOE must be stable before and after the high to low transition of HP_nCS.
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26
IRMCK201
Host Parallel Write Cycle
tHPCSN
HP_nCS
t HPWENS
tH PWEN
HP_nWE
tHPAS
tH PA
HP_A
tHPD[7:0]
HP_D[7:0]
t HPD[7:0]S
t HPOEN
HP_nOE
t HPOENS
Figure 11.
SYMBOL
tHPCSN
tHPWENS
tHPWEN
tHPAS
tHPA
tHPD[7:0]
tHPOENS
tHPOEN
Host Parallel Write Cycle Timing
DESCRIPTION
HP_nCS Period
HP_nWE Setup
HP_nWE Period
HP_A Setup
HP_A Period
HP_D [7:0] Setup
HP_nOE Setup
HP_nOE Period
MIN
70
10
70
-10
70
-10
10
70
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
Note 4
Table 18: Host Parallel Write Cycle Timing
Note:
4.
HP_nOE must be asserted high while HP_nCS low during a Host Parallel Write Cycle.
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27
IRMCK201
Discrete I/O Electrical Characteristics
IFBCAL
START
STOP
FLTCLR
GATEKILL
tL
Figure 12.
SYMBOL
tL
Discrete I/O Timing
DESCRIPTION
Pulse Width IFBCAL
Pulse Width START
Pulse Width STOP
Pulse Width FLTCLR
Pulse Width GATEKILL
MIN
100
100
100
1
490
UNITS
ms
ns
ns
us
ns
NOTE
Note 5
Table 19: Discrete I/O Timing
Note:
5.
GATEKILL can be programmed to be low or high true.
specification is the same.
Shown above is a low true gate kill.
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The timing
28
IRMCK201
Motion Peripheral Electrical Characteristics
PWM Electrical Characteristics
tDEADTIMERESOLUTION
tDEADTIMERESOLUTION
SYNC
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
Figure 13.
SYMBOL
tDEADTIMERESOLUTION
PWM Timing
DESCRIPTION
Deadtime Insertion Logic Resolution
VALUE
30
UNITS
ns
Table 20: PWM Timing
IR2175 Interface
tIFB
tIFBH
IFB0
IFB1
tIFBL
Figure 14.
SYMBOL
fIFB
tIFB
tIBH
tIFBH
DESCRIPTION
Current Feedback Input Frequency
Current Feedback Period
Current Feedback High Pulse Width
Current Feedback Low Pulse Width
IR2175 Interface
MIN
95
10.52
500 ns
500 ns
MAX
165
6.06
10 us
10 us
UNITS
kHz
µs
Table 21: IR2175 Interface
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29
IRMCK201
Encoder Electrical Characteristics
Table 22 shows the input timing characteristics of the encoder inputs. Please refer to the IRMCK201 Application
Developer’s Guide for an example encoder input circuit that drives the IRMCK201.
tENCODER
tENCH
ENA
ENB
ENZ
tENCL
HALLA
HALLB
HALLC
VALID
tHALLABCS
RESETN
Figure 15.
SYMBOL
fENCODER
tENCODER
tENCL
tENCH
tHALLABCS
DESCRIPTION
Encoder Input Frequency
ENA ENB ENZ Period
ENA ENB ENZ Pulse Width
ENA ENB ENZ Pulse Width
HALLA HALLB HALLC Setup to
RESETN
Encoder Timing
MIN
TYP
MAX
1
1
500
500
1
UNITS
MHz
µs
ns
ns
µs
Table 22: Encoder Timing
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30
Analog To Digital Interface Electrical Characteristics
ADC Timing
System Level Timing
The IRMCK201 contains logic to drive an ADC Converter, Analog MUX and associated Sample and Hold circuits. Figure 16 and Table 23 show the system
level timing of these elements. Figure 17 and Table 24 show specific timing parameters associated with the ADC Converter. Refer to the Application
Developers Guide for a detailed description of ADC, MUX and Sample and Hold signal system level protocol. The IRMCK201 ADC interface has been
designed for interfacing to the Burr-Brown ADS7818 ADC and Texas Instruments CD4052 MUX.
tSYNC
SYNC
RESSAMPLE
ADCONVST
tADCONVST
ADMUX0
tADMUX
tADMUX1S
ADMUX1
ADCLK
tADCLK
tADCLK
Figure 16.
SYMBOL
tSYNC
tRESSAMPLES
tADMUX0S
tADMUX1S
tADCONVSTS
Top Level ADC Timing
DESCRIPTION
SYNC Pulse Width
SYNC Falling Edge to
RESSAMPLE Valid
ADCONVST to ADMUX0 Valid
ADCONVST to ADMUX1 Valid
ADCONVST to ADCLK
MIN
-10
10
UNITS
µs
ns
40
40
71
61
61
91
ns
ns
ns
Table 23: Top Level ADC Timing
TYP
3
MAX
IRMCK201
Converter Level Timing
tADCLK
t1
ADCLK
tADOUTS
D11
ADOUT
t2
D10
D1
D2
D0
tHADOUT
ADCONVST
RESSAMPLE
t3
ADMUX0
ADMUX1
Figure 17.
SYMBOL
fADCLK
tADCLK
t1
t2
t3
TADOUTS
THADOUT
DESCRIPTION
ADC Clock Frequency
ADC Clock Period
RESSAMPLE to ADCLK
RESSAMPLE to ADCONVST
RESSAMPLE to ADMUX0,
ADMUX1
ADOUT to ADCLK Setup
ADOUT to ADCLK Hold
ADC Specific Timing
VALUE
8.33
120
MIN
MAX
91
40
UNITS
MHz
ns
ns
ns
64
ns
19.7
2
ns
Table 24: ADC Specific Timing
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32
PLL Interface Electrical Characteristics
PARAMETER
Current
Consumption
Current
Consumption
Peak jitter
Cycle jitter
Lock-up Time
PLL Reset
Period
SYMBOL
CONDITION
S
MIN
TYP
MAX
UNITS
IDDS
Static
-
-
170
µA
IDD
Dynamic
-
5
-
mA
Tpj
Tcj
Tlock
Recommended
operating
condition
-500
-
-
1000
+500
1
ps
ps
ms
10
-
-
ns
Trst
Table 25: PLL Electrical Characteristics
IRMCK201
Appendix A
Host Register Map
A host computer controls the IRMCK201 using its slave-mode Full-Duplex SPI port, a standard RS-232 port or a 8-bit
parallel port for connection to a microprocessor. All interfaces are always active and can be used interchangeably,
although not simultaneously. Control/status registers are mapped into a 128-byte address space.
Host Parallel Access
The IRMCK201 contains an address register that is updated with the Host Register address when HP_A = 1. After
each subsequent data byte is either read or written, the internal address register is incremented. The diagram below
shows that Data Bytes 0 to N would access register locations initially specified by the Address Byte. The Address
Bye with the HP_A signal can be asserted at any time.
Address Byte
Data Byte 0
HP_A = 1
HP_A = 0
…………….
Data Byte N
HP_A = 0
HP_A = 0
Host Parallel Data Transfer Format
SPI Register Access
When configured as an SPI device read only and read/write operations are performed using the following transfer
format:
Command Byte
Data Byte 0
…………….
Data Byte N
Data Transfer Format
7
6
Read
Only
5
Bit Position
4
3
2
1
0
Register Map Starting Address
Command Byte Format
Data transfers begin at the address specified in the command byte and proceed sequentially until the SPI transfer
completes. As in the Host Parallel Access, the internal address register is incremented after each SPI byte is
transferred. Note that accesses are read/write unless the “read only” bit is set.
RS-232 Register Access
The IRMCK201 includes an RS-232 interface channel that allows operation using a direct connection to the host PC.
This interface implements a simple protocol that checks the validity of data prior to being written into a register. The
protocol is explained below.
RS-232 Register Write Access
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34
IRMCK201
A Register write operation consists of a command/address byte, byte count, register data and checksum. When the
IRMCK201 receives the register data, it validates the checksum, writes the register data, and transmits and
acknowledgement to the host.
Command / Address Byte
Byte Count
1-6 bytes of register data
Checksum
Register Write Operation
Command Acknowledgement Byte
Checksum
Register Write Acknowledgement
7
6
5
1=Read/
0=Write
Bit Position
4
3
2
1
0
1
0
Register Map Starting Address
Command/Address Byte Format
7
1=Error/
0=OK
6
5
Bit Position
4
3
2
Register Map Starting Address
Command Acknowledgement Byte Format
The following example shows a command sequence sent from the host to the IRMCO201 requesting a two-byte
register write operation:
0x2F
Write operation beginning at offset 0x2F
0x02
Byte count of register data is 2
0x00
Data byte 1
0x04
Data byte 2
0x35
Checksum (sum of preceding bytes, overflow discarded)
A good reply from the IRMCK201 would appear as follows:
0x2F
Write completed OK at offset 0x2F
0x2F
Checksum
An error reply to the command would have the following format:
0xAF
Write at offset 0x2F completed in error
0xAF
Checksum
RS-232 Register Read Access
A register read operation consists of a command/address byte, byte count and checksum. When the IRMCK201
receives the command, it validates the checksum and transmits the register data to the host.
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35
IRMCK201
Command / Address Byte
Byte Count
Checksum
Register Read Operation
Command Acknowledgement Byte
Register Data
(Byte Count bytes)
Checksum
Register Read Acknowledgement (transfer OK)
Command Acknowledgement Byte
Checksum
Register Read Acknowledgement (error)
The following example shows a command sequence sent from the host to the IRMCK201 requesting four bytes of read
register data:
0xA0
Read operation beginning at offset 0x20 (high-order bit selects read operation)
0x04
Requested data byte count is 4
0xA4
Checksum
A good reply from the IRMCK201 might appear as follows:
0x20
Read completed OK at offset 0x20
0x11
Data byte 1
0x22
Data byte 2
0x33
Data byte 3
0x44
Data byte 4
0xCA
Checksum
An error reply to the command would have the following format:
0xA0
Read at offset 0x20 completed in error
0xA0
Checksum
RS-232 Timeout
The IRMCK201 receiver includes a timer that automatically terminates transfers from the host to the IRMCK201 after
a period of 32 msec.
RS-232 Transfer Examples
The following example shows a normal exchange executing a register write access.
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37
IRMCK201
The example below shows a normal register read access exchange.
The following example shows a register write request that is repeated by the host due to a negative acknowledgement
from the IRMCK201.
In the final example, the host repeats a register read access request when it receives no response to its first attempt.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
38
IRMCK201
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
39
IRMCK201
Write Register Definitions
QuadratureDecode Register Group (Write Registers)
Byte
Offset
7
6
5
Bit Position
4
3
0x0
EncCntW (LSBs)
(W)
0x1
EncCntW (MSBs)
(W)
0x3
MaxEncCnt (LSBs)
(W)
0x4
MaxEncCnt (MSBs)
(W)
0x6
ZEncCnt (LSBs)
(W)
0x7
ZEncCnt (MSBs)
(W)
0x9
EncAngScl (LSBs)
(W)
0xA
EncAngScl (MSBs)
(W)
0xB
SPARE
RedSig
(W)
PwrOn
RedSig
(W)
2
1
0
ZPulse
Enb
(W)
ZPulsePol
(W)
CntEnb
(W)
QuadratureDecode Write Register Map
Field
Name
EncCntW
Access
(R/W)
W
MaxEncCnt
W
ZEncCnt
W
Field Description
New value for 16-bit Quadrature Decoder counter.
Maximum value of 16-bit Quadrature Decoder counter. The
encoder count is reset to 0 after this count has been reached.
This maximum should be set to correspond to a 360-degree
physical angle.
Encoder count value when the Z-pulse occurs. This value is
loaded automatically in hardware when the Z-pulse occurs.
(See ZPulseEnb and ZPulsePol fields below.)
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
40
IRMCK201
Field
Name
Access
(R/W)
Field Description
This value should be set to ((MtrPoles / 2) * (4096 * 4096) /
(MaxEncCnt + 1), where MtrPoles is the number of motor
W
poles. The value is used to convert the encoder count to an
angle ranging from 0 - 4095 using the equation: Angle =
((MtrPoles / 2) * 4096 * (encoder count) / (MaxEncCnt + 1))
MOD 4096. (The current encoder count can be read from
the EncCntR feld of the QuadratureDecodeStatus read
register group.)
W
Encoder counter enable.
W
ZPULSE polarity. 1= load ZEncCnt on rising Z-pulse edge.
0= load ZEncCnt on falling Z-pulse edge.
ZPULSE count initialization enable. When this bit is set, the
encoder count is set to the ZEncCnt value at each Z-pulse
W
edge as determined by the ZPulsePol field.
PowerOn Reduced signal enable.
Set this bit in the
EEPROM to enable EEPROM standalone initialization for a
W
wire-saving encoder. When this bit is set, the EEPROM
initialization uses the PwrOnHallA, PwrOnHallB, PwrOnHallC
bits instead of the HallA, HallB, HallC bits to determine initial
motor angle.
(The Hall bits can be read from the
QuadratureDecodeStatus read register group.)
W
Reduced signal encoder enable. 1 = read Hall A/B/C fields
from encoder A/B/Z wires.
QuadratureDecode Write Register Field Definitions
EncAngScl
CntEnb
ZPulsePol
ZPulseEnb
PwrOnRedSig
RedSig
PwmConfig Register Group (Write Registers)
Byte
Offset
7
0xC
Gatekill
Sns
(W)
5
SPARE
Gate
SnsL
(W)
0xF
Gate
SnsU
(W)
2
SPARE
1
0
SD
(W)
SPARE
PwmPeriod (LSBs)
(W)
0xD
0xE
Bit Position
4
3
6
SPARE
PwmConfig
(W)
PwmPeriod (MSBs)
(W)
PwmDeadTm
(W)
PwmConfig Write Register Map
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
41
IRMCK201
Field
Name
SD
GateSnsU
Access
(R/W)
W
W
GateSnsL
W
GatekillSns
W
PwmPeriod
W
PwmConfig
W
PwmDeadTm
W
Field Description
Shutdown control output to IR213x.
Upper IGBT gate sense. 1 = active high gate control, 0 = active low
gate control.
Lower IGBT gate sense. 1 = active high gate control, 0 = active low
gate control.
GATEKILL signal sense. 1 = active high GATEKILL, 0 = active low
GATEKILL.
This field is used to set the desired PWM frequency using the
following equation:
PwmPeriod = 33,333,000 / ( 2 * (PWM frequency)) – 1,
where 33,333,000 is the system clock frequency (33.333MHz).
Note that while "PwmPeriod" is the name of this field, the actual
PWM carrier period is 2 * (PwmPeriod + 1) * (System Clock Period
= 30ns).
PWM Configuration. 0 = Asymmetrical center aligned PWM, 1 =
Symmetrical Center aligned PWM.
Gate drive dead time in units of system clock cycles (e.g., 30 ns
with 33 MHz clock).
PwmConfig Write Register Field Definitions
CurrentFeedbackConfig Register Group (Write Registers)
Byte
Offset
7
6
5
2
1
0
IfbOffsV (LSBs)
(W)
0x10
0x11
Bit Position
4
3
IfbOffsW (LSBs)
(W)
IfbOffsV (MSBs)
(W)
0x12
IfbOffsW (MSBs)
(W)
0x13
IdScl (LSB)
(W)
0x14
IdScl (MSB)
(W)
0x15
IqScl (LSB)
(W)
0x16
IqScl (MSB)
(W)
CurrentFeedbackConfig Write Register Map
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
42
IRMCK201
Field
Name
Access
(R/W)
Field Description
12-bit signed value for V phase current feedback offset. When the
IfbOffsEnb bit in the SystemControl write register group is "0" this
value is automatically added to each current measurement in
hardware.
12-bit signed value for W phase current feedback offset. When the
IfbOffsEnb bit in the SystemControl write register group is "0” this
W
value is automatically added to each current measurement in
hardware.
Rotating frame Id component current feedback scale factor. Constant
used to scale current measurements before they are used in the field
W
orientation calculation. This is a 15-bit fixed-point signed number with
10 fractional bits that ranges from –16 to + 16 + 1023 / 1024.
Rotating frame Iq component current feedback scale factor. Constant
used to scale current measurements before they are used in the field
W
orientation calculation. This is a 15-bit fixed-point signed number with
10 fractional bits that ranges from –16 to + 16 + 1023 / 1024.
CurrentFeedbackConfig Write Register Field Definitions
IfbOffsV
W
IfbOffsW
IdScl
IqScl
SystemControl Register Group (Write Registers)
Byte
Offset
0x17
7
6
5
DcComp
Enb
IfbOffs
Enb
Bit Position
4
3
SPARE
2
1
0
Reserved
Foc
EnbW
Pwm
EnbW
SystemControl Write Register Map
Field
Name
Access
(R/W)
PwmEnbW
W
FocEnbW
W
Reserved
W
Field Description
PWM Enable bit. Setting this bit to 1 or 0 sets the IGBT gate control
signals to their active or inactive states. At power up the gate control
output signals remain in a high-Z state. After PwmEnbW is set for the
first time, the gate controls are driven to their active or inactive states
according to the value of PwmEnbW. A fault condition clears this bit
automatically in hardware.
Field Orientated Control Enable bit. Setting this bit to 1 enables the
FOC algorithm. Setting this bit to 0 resets the FOC algorithm and
causes zero output voltage to be applied to the motor. A fault
condition clears this bit automatically in hardware.
This field should is reserved and should be set to 0.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
43
IRMCK201
Field
Name
Access
(R/W)
Field Description
When IFB PwmEnbW = 1, and FocEnbW = 0, the Current feedback
offset is calculated and saved in the CurrentFeedbackOffset read
register group. When IfbOffsEnb = 1, the Current feedback offset
W
values in the CurrentFeedbackOffset Read registers are applied to
each current feedback measurement. When IfbOffsEnb = 0, the
Current feedback offset values in the CurrentFeedbackConfig Write
registers are applied to each current feedback measurement.
DC Bus Compensation enable. When this bit is set to "1", PWM
output is compensated for using the following formula:
W
PWM (comp) = PWM * 310 / DCBUSVOLTS
where PWM (comp) is the compensated PWM output voltage; PWM
is the uncompensated PWM output voltage; 310 is the nominal DC
bus voltage; and DCBUSVOLTS is the actual DC bus voltage.
SystemControl Write Register Field Definitions
IfbOffsEnb
DcCompEnb
CurrentLoopConfig Register Group (Write Registers)
Byte
Offset
7
0x18
6
5
Bit Position
4
3
IqRefW – Quadrature Reference Current
(W)
2
IqRefW – Quadrature Reference Current (MSBs)
(W)
0x1A
KpIreg – Current Loop Proportional Gain (LSBs)
(W)
0x1B
KpIreg – Current Loop Proportional Gain (MSBs)
(W)
0x1C
KxIreg – Current Loop Integral Gain (LSBs)
(W)
0x1D
KxIreg – Current Loop Integral Gain (MSBs)
(W)
0x1F
IdRef – Direct/Magnetizing Reference Current
(W)
0
(LSBs)
0x19
0x1E
1
(LSBs)
IdRef – Direct/Magnetizing Reference Current (MSBs)
(W)
0x20
SlipGn (LSBs)
(W)
0x21
SlipGn (MSBs)
(W)
0x22
VqLim – Quadrature Current Output Limit (LSBs)
(W)
0x23
VqLim – Quadrature Current Output Limit (MSBs)
(W)
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44
IRMCK201
Byte
Offset
7
6
5
Bit Position
4
3
2
0x26
VdLim – Direct Current Output Limit (LSBs)
(W)
0x27
VdLim – Direct Current Output Limit (MSBs)
(W)
1
0
CurrentLoopConfig Write Register Map
Field
Name
IqRefW
KpIreg
Access
(R/W)
W
W
KxIreg
W
IdRef
W
SlipGn
W
VqLim
VdLim
W
W
Field Description
15-bit signed quadrature current reference input from velocity loop.
15-bit signed current loop PI controller proportional gain. Scaled with
14 fractional bits for an effective range of 0 – 1.
15-bit signed current loop PI controller integral gain. Scaled with 19
fractional bits for an effective range of 0 - .03125.
15-bit signed direct/magnetized current to D-axis current loop PI
controller.
This parameter controls the slip speed for induction motor
applications. SlipGn should be set to 2048 * 2048 * (Rated slip
speed in Hz) / (Current loop update frequency). SlipGn MUST be
set to 0 if slip is not desired.
16-bit Quadrature current PI controller voltage output limit.
16-bit Direct current PI controller voltage output limit.
CurrentLoopConfig Write Register Field Definitions
VelocityControl Register Group (Write Registers)
Byte
Offset
7
0x31
6
5
SPARE
Bit Position
4
3
2
1
SpdLpRate
0x32
KpSreg – Velocity loop proportional gain (LSBs)
(W)
0x33
KpSreg – Velocity loop proportional gain (MSBs)
(W)
0x34
KxSreg – Velocity loop integral gain (LSBs)
(W)
0x35
KxSreg – Velocity loop integral gain (MSBs)
(W)
0x36
SregLimP – Velocity loop positive Limit (LSBs)
(W)
0x37
SregLimP – Velocity loop positive Limit (MSBs)
(W)
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
0
SpdLpEnb
45
IRMCK201
Byte
Offset
7
6
Bit Position
4
3
5
2
0x38
SregLimN – Velocity loop negative Limit (LSBs)
(W)
0x39
SregLimN – Velocity loop negative Limit (MSBs)
(W)
0x3A
SpdScl – Speed Scale Factor (LSBs)
0x3B
SpdScl – Speed Scale Factor (MSBs)
0x3C
TargetSpd – Setpoint/target speed (LSBs)
0x3D
TargetSpd – Setpoint/target speed (MSBs)
0x3E
SpdAccRate – Acceleration
0x3F
SpdDecRate – Deceleration
1
0
VelocityControl Write Register Map
Field
Name
SpdLpEnb
Access
(R/W)
W
SpdLpRate
W
KpSreg
W
KxSreg
W
SregLimP
SregLimN
W
W
SpdScl
W
TargetSpd
W
SpdAccRate
W
SpdDecRate
W
Field Description
Speed loop enable: 1 = enable speed loop PI controller. 0 = Reset
Speed loop PI controller.
Speed loop update rate: 0 = disabled, N = update speed loop
immediately before every Nth current loop update.
15-bit velocity loop proportional gain, in fixed point with 5 fractional
bits. Range = 0 - 512.
15-bit velocity loop integral gain, in fixed point with 13 fractional bits.
Range = 0 - 2.
16-bit speed PI controller output positive limit.
16-bit speed PI controller output negative limit (2's complement).
Motor Speed Scale factor. The user should set SpdScl = 60 *
16383 * (33.333MHz/32) / (Max RPM * Encoder PPR) / 2, which will
result in a Speed value ranging ±16384 corresponding to ± Max
RPM.
Velocity loop speed setpoint in SPEED units, which are determined
by the user via the SpdScl register setting.
Velocity loop acceleration in units of SPEED / Velocity loop execution
or SPEED / (SpdLpRate / PWM period).
Velocity loop deceleration in units of SPEED / Velocity loop execution
or SPEED / (SpdLpRate / PWM period).
VelocityControl Write Register Field Definitions
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46
IRMCK201
FaultControl Register Group (Write Registers)
Byte
Offset
7
6
Bit Position
4
3
5
2
1
0
FltClr
DcBusM
Enb
SPARE
0x42
FaultControl Write Register Map
Field
Name
Access
(R/W)
DcBusMEnb
W
FltClr
W
Field Description
DC Bus monitor enable. 1 = Monitor DC bus voltage and generate
appropriate brake signal control and disable PWM output when
voltage fault conditions occur. GatekillFlt and OvrSpdFlt faults
cannot be disabled. DC bus voltage thresholds are as follows:
Overvoltage – 410V
Brake On – 380V
Brake Off – 360V
Nominal – 310V
Undervoltage off – 140V
Undervoltage – 120V
This bit clears all active fault conditions. The user should monitor
the FaultStatus read register group to determine fault status and set
this bit to “1” to clear any faults that have occurred. A fault condition
automatically clears the PwmEnbW and FocEnbW bits in the
SystemControl write register group. Note that this bit also directly
controls the output 2137 FLTCLR pin. After clearing a fault, the
user must explicitly set this bit to “0” to re-enable fault processing.
FaultControl Write Register Field Definitions
SVPWMScaler Register Group (Write Registers)
Byte
Offset
7
6
5
Bit Position
4
3
0x44
ModScl (LSBs)
(W)
0x45
ModScl (MSBs)
(W)
2
1
0
SVPWMScaler Write Register Map
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47
IRMCK201
Field
Name
Access
(R/W)
Field Description
Space vector modulator scale factor.
This register, which
depends on the PWM carrier frequency, should be set as follows:
W
ModScl = PwmPeriod * sqrt(3) * 4096 / 2355
where PwmPeriod is the value in the PwmConfig write register
group’s PwmPeriod register.
SVPWMScaler Write Register Field Definitions
ModScl
DiagnosticPwmControl Register Group (Write Registers)
Byte
Offset
7
6
5
Bit Position
4
3
2
1
0x4E
PwmData1Sel
PwmData0Sel
0x4F
PwmData3Sel
PwmData2Sel
0
DiagnosticPwmControl Write Register Map
Field
Name
PwmData0Sel,
PwmData1Sel,
PwmData2Sel,
PwmData3Sel
Access
(R/W)
Field Description
Selects diagnostic data items for output on DAC PWM pins 0-3.
These pins are intended for use with external RC filters for
oscilloscope diagnostic display:
1 = DC Bus Voltage
2 = V phase current
3 = W phase current
5 = Speed PI Reference
W
6 = Speed PI Feedback
7 = Speed PI Error
8 = IQ Ref
9 = Q axis voltage Qv
10 = D axis voltage Dv
11 = 12-bit electrical angle
12 = Q axis current Qi
13 = D axis current Di
14 = A axis (stationary frame) voltage Av
15 = B axis (stationary frame) voltage Bv
DiagnosticPwmControl Write Register Field Definitions
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48
IRMCK201
SystemConfig Register Group (Write Registers)
Byte
Offset
7
0x50
6
ExtCtrlW
5
SpdRefSel
Bit Position
4
3
IqRefSel
2
1
0
HostAng
Enb
HostVd
Enb
RmpRef
Sel
SystemConfig Write Register Map
Field
Name
RmpRefSel
Access
(R/W)
W
HostVdEnb
W
HostAngEnb
W
IqRefSel
W
SpdRefSel
W
ExtCtrlW
W
Field Description
Speed Ramp reference select. 0= TargetSpd field of the
VelocityControl write register group, 1 = External analog reference.
Host D-Axis current control enable. When this bit is set, the D-Axis
PI Controller is disconnected from the forward path vector rotator,
which then takes its input from the VdSfwd field of the
DirectHostVoltageControl write register group.
Host electrical angle control enable. When this bit is set, the vector
rotator takes its angle input from the ElecAngW field of the
DirectHostVoltageControl write register group.
Selects the source for the Q-Axis PI controller IQREF input:
0 = Speed PI controller output
1 = IqRefW field of the CurrentLoopConfig write register group
2 = Reference A/D converter input.
Selects the source for the Speed PI controller reference input:
0 = Internal Accel/Deccel ramp generator
1 = TargetSpd field of the VelocityControl write register group
2 = Reference A/D converter input.
Setting this bit to “1” enables direct control of basic motor operation
via the external User Interface pins. When this bit is “1”, the
FocEnbW and PwmEnbW bits in the SystemControl write register
group are ignored.
SystemConfig Write Register Field Definitions
DirectHostVoltageControl Register Group (Write Registers)
Byte
Offset
7
6
5
2
1
0
VdSfwd (LSBs)
(W)
0x52
0x53
Bit Position
4
3
VqSfwd (LSBs)
(W)
VdSfwd (MSBs)
(W)
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49
IRMCK201
Byte
Offset
7
6
5
Bit Position
4
3
0x54
VqSfwd (MSBs)
(W)
0x55
ElecAngW (LSBs)
(W)
SPARE
0x56
2
1
0
ElecAngW (MSBs)
(W)
DirectHostVoltage Control Write Register Map
Field
Name
VdSfwd
Access
(R/W)
W
Field Description
12-bit signed value for synchronous frame direct current
when host direct current control is enabled. This field is
typically used for V/Hz control.
W
12-bit signed value for synchronous frame quadrature
voltage that is added to the Q-Axis PI-controller output.
This field is typically used for feedforward or V/Hz control.
W
12-bit electrical angle used when host electrical angle control
is enabled. This field is typically used for V/Hz control.
DirectHostVoltageControl Write Register Field Definitions
VqSfwd
ElecAngW
32bitQuadDecode Register Group (Write Registers)
Byte
Offset
7
6
5
Bit Position
4
3
0x58
EncCnt32bW (bits 0-7)
(W)
0x59
EncCnt32bW (bits 8-15)
(W)
0x5A
EncCnt32bW (bits 16-23)
(W)
0x5B
EncCnt32bW (bits 24-31)
(W)
2
1
0
32bitQuadDecode Write Register Map
Field
Name
EncCnt32bW
Access Field Description
(R/W)
W
New value for 32-bit Quadrature Decoder counter.
32bitQuadDecode Write Register Field Definitions
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50
IRMCK201
EepromControl Registers (Write Registers)
At power up, the write registers can be optionally initialized with values stored in EEPROM. The EepromControl
write register group and EepromStatus read register group are used to read and write these EEPROM values. Since
the EeAddrW write register (which selects the EEPROM offset to read or write) does not require initialization at
power up, the location corresponding to that register in EEPROM (at offset 0x5D) is used to store a register map
version code. At power on, the IRMCK201 initializes the write registers from EEPROM only if the version code
stored at this offset in EEPROM matches its internal register map version code (which can be read from the
RegMapVer field of the EepromStatus read register group).
To enable write register initialization at power up, write the appropriate register map version code to EEPROM at
offset 0x5D. To disable write register initialization at power up, write a zero (or any non-matching version code) to
offset 0x5D of the EEPROM.
Byte
Offset
7
6
Bit Position
4
3
5
SPARE
0x5C
0x5D
EeAddrW / RegMapVersCode
(W)
0x5E
EeDataW
(W)
2
1
0
EeWrite
EeRead
EeRst
EepromControl Write Register Map
Field
Name
EeRst
Access
(R/W)
W
EeRead
W
EeWrite
W
EeAddrW
W
EeDataW
W
Field Description
Self-clearing EEPROM reset. Writing a "1" to this bit resets the I2C
EEPROM interface.
Self-clearing I2c EEPROM Read. Writing a "1" to this bit initiates an
EEPROM read from the byte located at EEPROM address EeAddrW.
After setting this bit the user should poll the EeBusy bit in the
EepromStatus read register group to determine when the read
completes and then read the data from EeDataR in the
EepromStatus read register group.
Self-clearing EEPROM Write. Writing a "1" to this bit initiates an
EEPROM write from the data byte in EeDataW to the EEPROM
address EeAddrW.
EEPROM Address Register. Contains the address for the next
EEPROM read or write operation.
EEPROM Data Register. Contains the data for the next EEPROM
write operation.
EepromControl Write Register Field Definitions
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51
IRMCK201
HallSensorEncoderInit (Write Registers – EEPROM only)
These values must be set in the EEPROM for initial encoder count/angle initialization in the EEPROM standalone (i.e.
operation without a host program). EEPROM initialization logic automatically loads the appropriate value into the
encoder counter at power-on based on the HALL A/B/C sensor values. These values are present only in the
EEPROM since they serve no purpose after power on.
Byte
Offset
7
6
Bit Position
4
3
5
0x72
HallCBA001(LSBs)
0x73
HallCBA001(MSBs)
0x74
HallCBA010 (LSBs)
0x75
HallCBA010 (MSBs)
0x76
HallCBA011(LSBs)
0x77
HallCBA011(MSBs)
0x78
HallCBA100 (LSBs)
0x79
HallCBA100 (MSBs)
0x7A
HallCBA101(LSBs)
0x7B
HallCBA101(MSBs)
0x7C
HallCBA110 (LSBs)
0x7D
HallCBA 110 (MSBs)
2
1
0
HallSensorEncoderInit Register Map
Field
Name
HallCBAnnn
Access
(R/W)
W
(EEPROM
ONLY)
Field Description
Initial encoder count for Hall Sensor [C, B, A] value [n, n, n].
HallSensorEncoderInit Field Definitions
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52
IRMCK201
Read Register Definitions
QuadratureDecodeStatus Register Group (Read Registers)
Byte
Offset
7
6
Bit Position
4
3
5
0x0
EncCntR (LSBs)
(R)
0x1
EncCntR (MSBs)
(R)
0x3
SPARE
PwrOn
HallC
PwrOn
HallB
PwrOn
HallA
SPARE
2
1
0
HallC
HallB
HallA
QuadratureDecodeStatus Read Register Map
Field
Name
EncCntR
HallA, HallB,
HallC
PwrOnHallA,
PwrOnHallB,
PwrOnHallC
Access
(R/W)
R
R
Field Description
Current value of 16-bit Quadrature Decoder counter.
Hall Sensor A/B/C values.
Hall Sensor A/B/C values at power-on for reduced-wire encoder
interface.
R
QuadratureDecodeStatus Read Register Field Definitions
SystemStatus Register Group (Read Registers)
Byte
Offset
0x7
7
6
5
Bit Position
4
3
2
1
0
Start
Stop
SPARE
PwrID
GateKill
Foc
EnbR
Pwm
EnbR
0x8
RevCode (LSBs)
0x9
RevCode (MSBs)
SystemStatus Read Register Map
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53
IRMCK201
Field
Name
PwmEnbR
FocEnbR
GateKill
Access
(R/W)
R
R
R
PwrID
Stop
Start
RevCode
R
R
R
R
Field Description
PWM Enable bit status.
FOC Enable bit status.
GATEKILL status. This bit is set by the Gatekill input from the
IR2137. Once set, this bit remains set until it is cleared by writing a
“1” to the FaultClr bit in the FaultControl write register group.
Power ID. 0 = 3 kW, 1 = 2 kW, 2 = 500 W.
User Interface "STOP" digital input status.
User Interface "START" digital input status.
IC Revision Code. Revision code format is “XX.XX”, where each “X”
is a 4-bit hexadecimal number.
SystemStatus Read Register Field Definitions
DcBusVoltage Register Group (Read Registers)
Byte
Offset
7
6
5
Bit Position
4
3
2
1
0
DcBusVolts (LSBs)
0xA
SPARE
0xB
Brake
DcBusVolts (MSBs)
DcBusVoltage Read Register Map
Field
Name
DcBusVolts
Access
(R/W)
R
Brake
R
Field Description
DC Bus Voltage. Data range is 0 - 4095, which corresponds to a
DC bus voltage between 0 and 500 volts.
Brake signal status. 0 = Brake signal active.
DcBusVoltage Read Register Field Definitions
FocDiagnosticData Register Group (Read Registers)
Byte
Offset
7
0xC
0xD
6
5
Bit Position
4
3
2
1
0
IvFbk - V Phase IFB Raw Current (LSBs)
(R)
IwFbk - W Phase IFB Raw Current (LSBs)
(R)
IvFbk - V Phase IFB Raw Current (MSBs)
(R)
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
54
IRMCK201
Byte
Offset
7
6
5
Bit Position
4
3
2
0xE
IwFbk - W Phase IFB Raw Current (MSBs)
(R)
0xF
Id – Synchronous Frame Direct Current (LSBs)
(R)
0x10
Id – Synchronous Frame Direct Current (MSBs)
(R)
0x11
Iq – Synchronous Frame Quadrature Current (LSBs)
(R)
0x12
Iq – Synchronous Frame Quadrature Current (MSBs)
(R)
0x13
Ud – Synchronous Frame Direct Voltage (LSBs)
(R)
0x14
Ud – Synchronous Frame Direct Voltage (MSBs)
(R)
0x15
Uq – Synchronous Frame Quadrature Voltage (LSBs)
(R)
0x16
Uq – Synchronous Frame Quadrature Voltage (MSBs)
(R)
0x17
UAlpha – Stationary Frame Alpha Voltage (LSBs)
(R)
0x18
UBeta – Stationary Frame Beta Voltage (LSBs)
(R)
1
0
UAlpha – Stationary Frame Alpha Voltage (MSBs)
(R)
UBeta – Stationary Frame Beta Voltage (MSBs)
(R)
0x19
FocDiagnosticData Read Register Map
Field
Name
Access
(R/W)
IvFbk, IwFbk
R
Id, Iq
R
Ud, Uq
R
Field Description
Offset-corrected V and W phase raw current from the IR2175 current
sensor. Values range from 0 - 4096, where 2048 corresponds to 0
current. The current feedback scale factors IdScl and IqScl in the
CurrentFeedbackConfig write register group and the current sense
resistor value determine the full scale current value.
Synchronous or rotating frame direct and quadrature current values
in 2’s complement representation. The full scale current values range
from –16384 to 16383.
Synchronous or rotating frame direct and quadrature voltage values
in 2’s complement representation. Data ranges are ± VdLim for Ud
and ± VqLim for Uq as specified in the CurrentLoopConfig write
register group.
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55
IRMCK201
UAlpha,
UBeta
R
Stationary frame Alpha and Beta voltage output component values.
Data range is ± VdLim or ± VqLim (as specified in the
CurrentLoopConfig write register group), whichever is larger.
FocDiagnosticData Read Register Field Definitions
FaultStatus Register Group (Read Registers)
The Fault Status register records fault conditions that occur during drive operation. When any of these fault
conditions occur, the PWM output is automatically disabled. The user should monitor this register continuously for
fault conditions. A fault condition can be cleared by writing a “1” to the FaultClr bit in the FaultControl write
register group. (This does not automatically re-enable PWM output.)
Byte
Offset
7
6
5
SPARE
0x1E
Bit Position
4
3
ExecTm
Flt
OvrSpdFlt
2
1
0
OvFlt
LvFlt
GatekillFlt
FaultStatus Read Register Map
Field
Name
GatekillFlt
LvFlt
Access
(R/W)
R
R
OvFlt
R
OvrSpdFlt
R
ExecTmFlt
R
Field Description
Filtered and latched version of IR213x FAULT output.
DC bus low voltage fault. This fault occurs if the DC bus drops
below 120V.
DC bus overvoltage fault. This fault occurs if the DC bus voltage
exceeds 410V.
Over speed fault. This fault occurs whenever the motor reaches the
positive or negative limits. The user should use the scale factor in
the SpdScl field of the VelocityControl write register group to scale
the motor speed so that it falls between -16384 and +16383 with
these limits as the over speed condition.
Execution time fault.
FaultStatus Read Register Field Definitions
VelocityStatus Register Group (Read Registers)
Byte
Offset
7
6
5
Bit Position
4
3
0x26
Spd (LSBs)
0x27
Spd (MSBs)
2
1
0
VelocityStatus Read Register Map
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
56
IRMCK201
Field
Name
Spd
Access
(R/W)
R
Field Description
Current motor speed in SPEED units. (See the description of SpdScl
in the VelocityControl write register group.)
VelocityStatus Read Register Field Definitions
CurrentFeedbackOffset Register Group (Read Registers)
Byte
Offset
7
6
Bit Position
4
3
5
2
1
0
IfbVOffs (LSBs)
(R)
0x30
IfbWOffs (LSBs)
(R)
0x31
IfbVOffs (MSBs)
(R)
IfbWOffs (MSBs)
(R)
0x32
CurrentFeedbackOffset Read Register Map
Field
Name
Access
(R/W)
Field Description
Current feedback offset values from the last IFB Offset calculation.
These values are automatically applied to each current feedback
measurement value whenever the IfbOffsEnb bit in the
SystemControl write register group is set.
CurrentFeedbackOffset Read Register Field Definitions
IfbVOffs,
IfbWOffs
R
32bitQuadDecodeStatus Register Group (Read Registers)
Byte
Offset
7
6
5
Bit Position
4
3
0x34
EncCnt32bR (bits 0-7)
(R)
0x35
EncCnt32bR (bits 8-15)
(R)
0x36
EncCnt32bR (bits 16-23)
(R)
0x37
EncCnt32bR (bits 24-31)
(R)
2
1
0
32bitQuadDecodeStatus Read Register Map
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
57
IRMCK201
Field
Name
EncCnt32bR
Access
Field Description
(R/W)
R
Current value of 32-bit Quadrature Decoder counter.
32bitQuadDecodeStatus Read Register Field Definitions
EepromStatus Registers (Read Registers)
Byte
Offset
7
6
Bit Position
4
3
5
2
1
SPARE
0x38
0x39
EeDataR
(R)
0x3A
EeAddrR
(R)
0x3B
RegMapVer
(R)
0
EeBusy
EepromStatus Read Register Map
Field
Name
EeBusy
EeDataR
EeAddrR
RegMapVer
Access
(R/W)
R
Field Description
I2C EEPROM Interface busy bit. The user should wait for this bit to
clear before initiating EEPROM read or write operations.
R
EEPROM Data Register. Contains the data from the last EEPROM
read operation.
Note that writing to the EeRst field in the
EepromControl write register group invalidates this register.
R
EEPROM Address read register shows the value stored in EEPROM
at the offset of the EeAddrW write register (0x5D). Since this
address in the EEPROM contains the IRMCK201 register map
version, the user can read this field to determine whether or not the
write registers were initialized at power on.
R
Current register map version code.
EepromStatus Read Register Field Definitions
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58
IRMCK201
FOCDiagnosticDataSupplement Register Group (Read Registers)
Byte
Offset
7
6
5
2
1
0
ElecAngR (LSBs)
(R)
0x3C
0x3D
Bit Position
4
3
SPARE
ElecAngR (MSBs)
(R)
0x3E
SpdRef (LSBs)
(R)
0x3F
SpdRef (MSBs)
(R)
0x40
SpdErr (LSBs)
(R)
0x41
SpdErr (MSBs)
(R)
0x42
IqRefR (LSBs)
(R)
0x43
IqRefR (MSBs)
(R)
FOCDiagnosticDataSupplement Read Register Map
Field
Name
ElecAngR
SpdRef
SpdErr
IqRefR
Access Field Description
(R/W)
R
Electrical angle.
R
Speed PI controller reference input.
R
Speed PI controller error.
R
Speed PI controller output.
FOCDiagnosticDataSupplement Read Register Field Definitions
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59
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IRMCK201
DIMENSION IN MILIMETERS
DIMENSION IN INCHES*
SYMBOL
Min.
Nom.
Max.
Min.
Nom.
Max.
E
13.9
14
14.1
(0.548)
(0.551)
(0.555)
D
13.9
14
14.1
(0.548)
(0.551)
(0.555)
A
1.7
A1
A2
(0.066)
0.1
1.3
e
(0.004)
1.4
1.5
(0.052)
0.5
(0.055)
(0.059)
(0.020)
b
0.13
0.18
0.28
(0.006)
(0.007)
(0.011)
C
0.1
0.125
0.175
(0.004)
(0.005)
(0.006)
θ
0º
10º
(0º)
L
0.3
0.7
(0.012)
0.5
(10º)
(0.20)
L1
1
(0.039)
L2
0.5
(0.020)
(0.027)
HE
15.6
16
16.4
(0.615)
(0.630)
(0.645)
HD
15.6
16
16.4
(0.615)
(0.630)
(0.645)
O2
12º
(12º)
O3
12º
(12º)
R
0.2
(0.008)
R1
0.2
(0.008)
Table 27: QFP100 Dimensions
* For reference
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61
IRMCK201
Appendix C
Errata
1.
Using the ADS7818 A/D converter interface as the current feedback source is not supported
2.
The scaling is too large by a factor of 16 for the following Diagnostic DAC PWM selections: Reference Speed
(PWM data select value of 5), Motor Speed (PWM data select value of 6), IQREF (PWM data select value of 8).
The scaling is too large by a factor of 8 for the following Diagnostic DAC PWM selections: IQ (PWM data select
value of 12), ID (PWM data select value of 13).
The scaling is too large by a factor of 4 for the following Diagnostic DAC PWM selections: Av (PWM data select
value of 14), Bv (PWM data select value of 15).
These values will work at small data ranges, but overflow otherwise.
use the parallel port and diagnostic data registers.
3.
To extract the correct data for these items,
When the IRMCK201 is implemented in conjunction with the ADS7818, note that the IRMCK201 ADCLK is
specified at 120 ns while the ADS7818 is specified at 125 ns.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
62
IRMCK201
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
http://www.irf.com
Data and specifications subject to change without notice. 6/1/2004
Sales Offices, Agents and Distributors in Major Cities Throughout the World.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
63