STA8089FG
Fully Integrated GPS/Galileo/Glonass/BeiDou/QZSS Receiver
with embedded RF and in-package Flash
Data brief
• Operating condition:
– Main voltage regulator (VINL): 1.8 V ± 5%
– Backup voltage (VINB): 1.6 V to 4.3 V
– Digital voltage (VDD): 1.2 V ± 10%
– RF core voltage (VCC): 1.2 V ± 10%
– IO Ring Voltage (VddIO): 1.8 V ± 5% or
3.3 V ± 10%
VFQFPN56
(7x7x0.85mm)
• Package:
– VFQFPN56 (7 x 7 x 0.85 mm) 0.4 mm
pitch
• Ambient temperature range: -40/+85°C
Features
• STMicroelectronics® positioning receiver with
48 tracking channels and 2 fast acquisition
channels supporting GPS, Galileo, Glonass,
BeiDou and QZSS systems
• Pin to pin compatible with STA8088FG
• Single die standalone receiver embedding RF
Front-End and low noise amplifier
• -162 dBm indoor sensitivity (tracking mode)
• Fast TTFF < 1 s in Hot start and 30 s in Cold
Start
• High performance ARM946 MCU (up to
196 MHz)
Description
STA8089FG is a single die standalone positioning
receiver IC working on multiple constellations
(GPS/Galileo/Glonass/BeiDou/QZSS).
The device is backward compatible with
STA8088FG, this enables fast customer
application migration.
The device is offered with a complete GNSS
firmware which performs all GNSS operations
including tracking, acquisition, navigation and
data output with no need of external memories.
• 256 Kbyte embedded SRAM
• In-package SQI Flash Memory (16 Mbits)
• Real Time Clock (RTC) circuit
• 32-bit Watch-dog timer
• 3 UARTs
• 1 I2C master interface
• 1 Synchronous Serial Port (SSP, Motorola-SPI
supported)
• USB2.0 full speed (12 MHz) with integrated
physical layer transceiver
• 2 Controller Area Network (CAN)
• 2 channels ADC (10 bits)
December 2014
DocID025732 Rev 3
For further information contact your local STMicroelectronics sales office.
1/17
www.st.com
Contents
STA8089FG
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
2.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
VFQFPN56 pin configuration
2.3
Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Communication interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8
RF front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
.................................. 7
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
VFQFPN56 7 x 7 x 0.85 mm package information . . . . . . . . . . . . . . . . . . 13
4
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
DocID025732 Rev 3
STA8089FG
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Communication interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RF front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VFQFPN56 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DocID025732 Rev 3
3/17
3
List of figures
STA8089FG
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
4/17
STA8089FG system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VFQFPN56 connection diagram (with CAN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VFQFPN56 connection diagram (no CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VFQFPN56 7 x 7 x 0.85 mm package dimension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DocID025732 Rev 3
STA8089FG
1
Overview
Overview
STA8089FG is a highly integrated single-chip standalone GNSS receiver designed for
positioning system applications.
STA8089FG embeds the new ST GNSS positioning engine capable of receiving signals
from multiple satellite navigation systems, including the US GPS, European Galileo,
Russia's Glonass, Chinese BeiDou and Japan's QZSS.
The STA8089FG ability of tracking simultaneously the signals from multiple satellites
regardless of their constellation, make this chip capable of delivering exceptional accuracy
in urban canyons and in the environments where buildings and other obstructions make
satellite visibility challenging.
The STA8089FG is backward compatible with STA8088FG, enabling fast customer
application migration.
The STA8089FG combines a high performance ARM946 microprocessor with I/O cpabilities
and enhanced peripherals. It supports USB2.0 standard at full speed (12 Mbps) with on-chip
PHY.
The device is offered with a complete firmware performing all positioning operations
including acquisition, tracking, navigation and data output with no need of external
memories.
The device powered with 1.8V enables the on-chip voltage regulators to internally supply
the RF front-end, core logic and the backup logic. The device can be directly powered with
1.2 V bypassing the embedded voltage regulators which will be put in power down mode.
I/O lines are compatible with 1.8 V and 3.3 V.
The STA8089FG, using STMicroelectronics CMOSRF Technology, is housed in a
VFQFPN-56 (7 x 7 x 0.85 mm) package with stacked 16 Mbit Flash memory.
DocID025732 Rev 3
5/17
16
Pin description
STA8089FG
2
Pin description
2.1
Block diagram
Figure 1. STA8089FG system block diagram
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6/17
DocID025732 Rev 3
STA8089FG
VFQFPN56 pin configuration
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2.2
Pin description
("1($'5
DocID025732 Rev 3
7/17
16
Pin description
STA8089FG
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2.3
Power supply pins
Table 1. Power supply pins
Symbol
I/O voltage
VCC_CHAIN
1.2 V
PWR Analog supply voltage for RF chain (1.2 V)
16
VCC_PLL
1.2 V
PWR Analog supply voltage for PLL RF (1.2 V)
18
VCC_RF
1.2 V
PWR Analog supply voltage for RF (1.2 V)
8
VDD_SQI
1.8 V
PWR Digital supply voltage for SQI
34
VDDD
1.1 V
PWR
VDDIO_R1
VDDIO_R2
8/17
I/O
Description
Digital supply voltage. This value can be configured to 1.0 V,
1.1 V (default) or 1.2 V
1.8 V or 3.3 V PWR Digital supply voltage for I/O ring 1 (1.8 V or 3.3 V)
3.3 V
PWR Digital supply voltage for I/O ring 2 (3.3 V)
DocID025732 Rev 3
STA8089FG
22,47
44
52
STA8089FG
Pin description
Table 1. Power supply pins (continued)
Symbol
I/O voltage
VINB
1.6 V - 4.3 V
VINL1
1.8 V
VINL2
1.6 V to 4.3 V
VOB
I/O
Description
STA8089FG
PWR Backup LDO input supply voltage (1.6 V to 4.3 V)
29
PWR LDO1 and ADC input supply voltage
31
PWR LDO2 input supply voltage (1.6 V to 4.3 V)
13
1.0 V
PWR LDO backup output voltage (1.0 V)
21
VOL1
1.1 V
PWR
VOL2
1.2 V
PWR LDO2 output voltage (1.2 V)
12
GND
GND
GND Ground
EP
GND_LNA
GND
GND Ground
10
2.4
LDO1 output voltage (1.2 V), it can be also configured to
1.0 V or 1.2 V
30
Main function pins
Table 2. Main function pins
Symbol
I/O voltage
I/O
ADC_IN1
1.4 V – 0 V typ range
I
ADC Analog input [1]
32
ADC_IN2
1.4 V – 0 V typ range
I
ADC Analog input [2]
33
RSTn
1.0 V
I
Reset Input with Schmitt-Trigger characteristics
and noise filter.
25
RTC_XTI
1.0 V (max)
I
Input of the 32 KHz oscillator amplifier circuit and
input of the internal real time clock circuit.
27
RTC_XTO
1.0 V (max)
O
Output of the oscillator amplifier circuit.
28
STDBY_OUT
1.0 V
O
When low, indicates the chip is in Standby mode
23
STDBYn
1.0 V
I
When low, the chip is forced in Standby Mode All pins in high impedance except the ones
powered by Backup supply
24
WAKEUP
1.0 V
I
WAKEUP from STANDBY mode
26
2.5
Description
STA8089FG
Test/emulated dedicated pins
Table 3. Test/emulated dedicated pins
Symbol
I/O voltage
I/O
Description
TCK
VDDIO_R2
I
JTAG Test Clock
56
TDI
VDDIO_R2
I
JTAG Test Data In
53
TDO
VDDIO_R2
O
JTAG Test Data Out
50
TMS
VDDIO_R2
I
JTAG Test Mode Select
2
TRSTn
VDDIO_R2
I
JTAG Test Circuit Reset
3
DocID025732 Rev 3
STA8089FG
9/17
16
Pin description
STA8089FG
Table 3. Test/emulated dedicated pins (continued)
Symbol
I/O voltage
I/O
TP_IF_N
1.2 V
O
Diff. Test Point for IF – Negative
6
TP_IF_P
1.2 V
O
Diff. Test Point for IF – Positive
5
2.6
Description
STA8089FG
Communication interface pins
Table 4. Communication interface pins
Symbol
I/O voltage
CAN0_RX(1) VDDIO_R2
CAN0_TX(1) VDDIO_R2
CAN1_RX(1)
I/O
Alternative
function
Function
I
AF0
(default)
CAN0_RX(1)
CAN0 receive data input
I
AF1
UART0_RX
UART0 Rx data
I/O
AF2
TSENSE
External temperature capture
port
I/O
AF3
I2C_SD
I2C serial data
O
AF0
(default)
CAN0_TX(1)
CAN0 transmit data output
O
AF1
UART0_TX
UART0 Tx data
I/O
AF2
GPIO7
O
AF3
I2C_CLK
I2C clock
I/O
AF0
I2C_SD
I2C serial data
I/O
AF1
GPIO9
General purpose I/O #9
I
AF2
(default)
CAN1_RX(1)
CAN1 receive data input
O
AF3
SPI_CSN
SPI chip select active low
O
AF0
I2C_CLK
I2C clock
I/O
AF1
GPIO8
O
AF2
(default)
CAN1_TX(1)
O
AF3
SPI_CLK
SPI clock
O
AF0
(default)
SPI_CLK
SPI clock
I/O
AF1
GPIO25
General purpose I/O #25
O
AF2
SQI_CLK
O
AF3
MMC_CLK
VDDIO_R2
10/17
VDDIO_R1
STA8089FG
54
CAN1_TX(1) VDDIO_R2
SPI_CLK
Description
51
General purpose I/O #7
55
General purpose I/O #8
1
CAN1 transmit data output
SQI Flash clock
Multimedia Clock line
DocID025732 Rev 3
41
STA8089FG
Pin description
Table 4. Communication interface pins (continued)
Symbol
SPI_CSN
SPI_DI
SPI_DO
UART0_RX
UART0_TX
UART2_RX
UART2_TX
I/O voltage
VDDIO_R1
VDDIO_R1
VDDIO_R1
I/O
Alternative
function
Function
O
AF0
(default)
SPI_CSN
SPI chip select active low/
IO_Power Sel Ring 1
I/O
AF1
GPIO24
General purpose I/O #24
O
AF2
SQI_CEN
I/O
AF3
MMC_CMD
I
AF0
(default)
SPI_DI
SPI serial data input/ BOOT2
I/O
AF1
TSENSE
External temperature capture
port
I/O
AF2
SQI_SIO0/SI
I/O
AF3
MMC_D0
Multimedia card data 0
O
AF0
(default)
SPI_DO
SPI serial data output
I/O
AF1
GPIO27
General purpose I/O #27
I/O
AF2
SQI_SIO1/SO
I/O
AF3
MMC_D1
I
AF0
(default)
UART0_RX
O
AF1
SPI_DO
I/O
AF2
SQI_SIO2
I
AF3
Timer_ICAPA
O
AF0
(default)
UART0_TX
I
AF1
SPI_DI
SPI serial data input
I/O
AF2
SQI_SIO3
SQI Flash data IO 3
O
AF3
Timer_OCMPA
I
AF0
(default)
UART2_RX
I/O
AF1
GPIO28
General purpose I/O #28
I/O
AF2
I2C_SD
I2C serial data
I/O
AF3
MMC_D2
O
AF0
(default)
UART2_TX
UART2 Tx data / BOOT0
I/O
AF1
GPIO29
General purpose I/O #29
O
AF2
I2C_CLK
I2C clock
I/O
AF3
MMC_D3
Multimedia card data 2
Description
Multimedia card command line
42
SQI Flash data IO 0 / ser. I
43
SQI Flash data IO 1 / ser. O
Multimedia card data 1
UART0 Rx data
SPI serial data output
38
SQI Flash data IO 2
Extended Function Timer - Input
Capture A
UART0 Tx data / BOOT1
VDDIO_R1
VDDIO_R1
40
SQI Flash chip enable
VDDIO_R1
VDDIO_R1
STA8089FG
39
Extended Function Timer –
Output Compare A
UART2 Rx data
36
Multimedia card data 2
DocID025732 Rev 3
37
11/17
16
Pin description
STA8089FG
Table 4. Communication interface pins (continued)
Symbol
I/O
Alternative
function
Function
USB
AF0
USB_DM
I
AF1
(default)
UART1_RX
UART1 Rx data
I
AF2
CAN1_RX(1)
CAN 1 receive data input
I/O
AF3
I2C_SD
I2C serial data
USB
AF0
USB_DP
USB D+ signal
O
AF1
(default)
UART1_TX
UART1 Tx data
O
AF2
CAN1_TX(1)
CAN 1 transmit data output
O
AF3
I2C_CLK
I/O voltage
USB_DM
VDDIO_R2
USB_DP
VDDIO_R2
Description
STA8089FG
USB D- signal
49
48
I2C clock
1. Only for STA8089FGB.
2.7
General purpose pins
Table 5. General purpose pins
Symbol
I/O voltage
GPIO1
2.8
I/O
Alternative
function
Function
I/O
AF0 (default)
GPIO1
I
AF1
i2s_in_sdata
O
AF2
PPS_OUT
I/O
AF3
TSENSE
Description
STA8089FG
General purpose I/O #1/
BOOT3
MSP serial data input
VDDIO_R1
35
Pulse per second output
External temperature
capture port
RF front-end pins
Table 6. RF front-end pins
Symbol
I/O voltage
I/O
LNA_IN
1.2 V
I
Low Noise Amplifier Input
9
XTAL_IN
1.2 V
I
Input Side of Crystal Oscillator or TCXO Input
19
XTAL_OUT
1.2 V
O
Output Side of Crystal Oscillator
20
12/17
Description
DocID025732 Rev 3
STA8089FG
STA8089FG
Package and packing information
3
Package and packing information
3.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
3.2
VFQFPN56 7 x 7 x 0.85 mm package information
Table 7. VFQFPN56 package dimensions
Symbol
Min.
Typ.
Max
Common dimensions
A
0.80
0.85
0.90
A1
0
0.01
0.05
A2
0.60
0.65
0.70
A3
b
0.20 REF
0.15
0.20
D
7.00 BSC
D1
6.75 BSC
D2
5.0
5.1
E
7.00 BSC
E1
6.75 BSC
E2
5.0
e
5.1
0.25
5.2
5.2
0.40 BSC
θ
0°
L
0.30
12°
0.40
N
56
Nd
14
Ne
14
0.50
P
0.24
0.42
0.60
Q
0.30
0.40
0.65
R
0.13
0.17
0.23
DocID025732 Rev 3
13/17
16
Package and packing information
STA8089FG
Figure 4. VFQFPN56 7 x 7 x 0.85 mm package dimension
("1($'5
14/17
DocID025732 Rev 3
STA8089FG
4
Ordering information
Ordering information
Figure 5. Ordering information scheme
Example code:
STA8089FG
Family identifier
B
Qualified Grade/CAN Bus
TR
Packing
TR = Tape and Reel
<blank> = Tray
B = Industrial Grade (with CAN)
<blank> = Industrial Grade (no CAN)
SAL with Stacked Flash
DocID025732 Rev 3
15/17
16
Revision history
5
STA8089FG
Revision history
Table 8. Document revision history
Date
Revision
19-Dec-2013
1
Initial release.
2
Updated Features list
Updated following chapters:
– Chapter 1: Overview
– Chapter 2: Pin description
– Chapter 3: Package and packing information
– Chapter 4: Ordering information
3
Updated Features list
Updated Figure 2: VFQFPN56 connection diagram (with CAN) and
Figure 3: VFQFPN56 connection diagram (no CAN)
Table 1: Power supply pins:
– Alternate function: removed column
– VINL1: updated description
– VINL2: updated I/O voltage
– VOL2: updated I/O voltage and description
– VDDD: updated description
Table 2: Main function pins:
– Alternate function: removed column
– RTC_XTI, RTC_XTO: updated I/O voltage
Table 3: Test/emulated dedicated pins:
– Alternate function: removed column
– TDI, TMS: updated description
Table 4: Communication interface pins:
– CAN0_RX: added note on CAN0_RX function; updated I/O type
for TSENSE function
– CAN0_TX: added note on CAN0_TX function
– CAN1_RX: added note on CAN1_RX function; changed I/O
type, function and description for AF3 function
– CAN1_TX: added note on CAN1_TX function; changed function
and description for AF3
– SPI_CSN: updated I/O type for SQI_CEN function
– SPI_DI: updated AF0 description; changed AF1 function
– UART0_TX, UART0_RX: changed AF1 I/O type and function
– USB_DM, USB_DP: updated
Updated Table 4: Communication interface pins
Table 6: RF front-end pins:
– Alternate function: removed column
31-Jan-2014
04-Dec-2014
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Changes
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STA8089FG
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