STMICROELECTRONICS STR711FR1T6

STR71xF
ARM7TDMI™ 16/32-BIT MCU WITH FLASH, USB, CAN
5 TIMERS, ADC, 10 COMMUNICATIONS INTERFACES
PRELIMINARY DATA
■
■
■
■
■
Memories
– Up to 256+16 Kbytes Flash memory (100,000
cycles endurance, 20 yrs retention)
– Up to 64 Kbytes RAM
– External Memory Interface (EMI) for up to 4
banks of SRAM, Flash, ROM.
– Multi-boot capability
Clock, Reset and Supply Management
– 3.3V application supply and I/O interface
– Internal 1.8V voltage regulator for core supply
– 0 to 16 MHz external main oscillator
– 32 kHz external backup oscillator
– Embedded PLL for CPU clock
– Up to 50 MHz CPU operating frequency when
executing from Flash
– Realtime Clock for clock-calendar function
– 4 power saving modes: SLOW, WAIT, STOP
and STANDBY modes
Nested interrupt controller
– Fast interrupt handling with multiple vectors
– 32 vectors with 16 IRQ priority levels
– 2 maskable FIQ sources
Up to 48 I/O ports
– 30/32/48 multifunctional bidirectional I/O lines
– 14 ports with interrupt capability
5 Timers
– 16-bit watchdog timer
– 4 16-bit timers with: 2 input captures, 2 output
compares, PWM and pulse counter modes
TQFP64
10 x 10
TQFP144
20 x 20
LFBGA64 8 8x x8 8x x1.7
LFBGA64
1.7
■
■
■
LFBGA144 10 x 10 x 1.7
10 Communications Interfaces
– 2 I2C interfaces (1 multiplexed with SPI)
– 4 UART asynchronous serial interfaces
– Smart Card ISO7816-3 interface on UART1
– 2 BSPI synchronous serial interfaces
– CAN interface (2.0B Active)
– USB v 2.0 Full Speed (12Mbit/s) Device Function with Suspend and Resume support
– HDLC synchronous communications
4-channel 12-bit A/D Converter
– Conversion time:
– 4 channels: up to 500 Hz (2 ms)
– 1 channel: up to 1 kHz (1 ms)
– Conversion range: 0 to 2.5V
Development Tools Support
– JTAG with debug mode trigger request
Table 1. Device Summary
Features
FLASH - Kbytes
RAM - Kbytes
Peripheral Functions
STR710FZ
1
2
128+16
256+16
32
64
CAN, EMI, USB,
48 I/Os
Operating Voltage
16
32
64
16
USB, 30 I/Os
32
64
CAN, 32 I/Os
STR715FR
0
64+16
16
32 I/Os
3.0 to 3.6V (optional 1.8V for core)
Operating Temp.
Packages
STR711FR
STR712FR
0
1
2
0
1
2
64+16 128+16 256+16 64+16 128+16 256+16
-40 to +85°C
T=TQFP144 20 x 20
H=LFBGA144 10 x10
T=TQFP64 10 x10 / H=LFBGA64 8 x 8 x 1.7
Rev. 6
April 2005
1/49
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Pin Description for 144-Pin Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Pin Description for 64-Pin Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5 External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6 I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3 LVD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6 nRSTIN Input Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.7 Oscillator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.8 PLL Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.9 Flash Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.10 External Memory Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.11 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.1 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 ORDER CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Note: For detailed information on the STR71xF Microcontroller memory, registers and
peripherals. please refer to the STR71xF Reference Manual.
49
2/49
1
STR71xF - INTRODUCTION
1 INTRODUCTION
This Preliminary Data provides the STR71x Ordering Information, Mechanical and Electrical
Device Characteristics.
For complete information on the STR71xF Microcontroller memory, registers and peripherals.
please refer to the STR71xF Reference Manual.
For information on programming, erasing and protection of the internal Flash memory please
refer to the STR7 Flash Programming Reference Manual
For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference
Manual.
1.1 Overview
ARM® core with embedded Flash & RAM
The STR71xF series is a family of ARM-powered 16/32-bit Microcontrollers with embedded
Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive range
of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed
single voltage FLASH memory and high-speed RAM. The STR71xF family has an embedded
ARM core and is therefore compatible with all ARM tools and software.
For information on the ARM Realview Developer Kit for ST and third-party development
tools, please refer to the http://www.st.com website
Package Choice: Low Pin-Count 64-pin or Feature-Rich 144-pin TQFP or BGA
The STR71xF family is available in 4 main versions.
The 144-pin versions have the full set of all features including CAN, USB and External
Memory Interface.
•
STR710F: 144-pin BGA or TQFP with CAN, USB and EMI
The three 64-pin versions (BGA or TQFP) do not include External Memory Interface.
•
STR715F: 64-pin BGA or TQFP without CAN or USB
•
STR711F: 64-pin BGA or TQFP with USB
•
STR712F: 64-pin BGA or TQFP with CAN
3/49
1
STR71xF - INTRODUCTION
Optional External Memory (STR710F)
The non-multiplexed 16-bit data/24-bit address bus available on the STR710F (144-pin)
supports four 16-Mbyte banks of external memory. Wait states are programmable individually
for each bank allowing different memory types (Flash, EPROM, ROM, SRAM etc.) to be used
to store programs or data.
Figure 1 shows the general block diagram of the device family.
Flexible Power Management
To minimize power consumption, you can program the STR71xF to switch to SLOW, WAIT
FOR INTERRUPT, STOP or STANDBY mode depending on the current system activity in the
application.
Flexible Clock Control
Two external clock sources can be used, a main clock and a 32 kHz backup clock. The
embedded PLL allows the internal system clock (up to 50 MHz) to be generated from a main
clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a
wide selection of multipliers and dividers.
Voltage Regulators
The STR71xF requires an external 3.0-3.6V power supply. There are two internal Voltage
Regulators for generating the 1.8V power supply for the core and peripherals. The main VR is
switched off and the Low Power VR switched on when the application puts the STR71xF in
Standby or Low Power Wait for Interrupt (LPWFI) mode.
Low Voltage Detectors
Each voltage regulator has an embedded LVD that monitors the internal 1.8V supply. If the
voltage drops below a certain threshold, the LVD will reset the STR71xF.
On-Chip Peripherals
CAN Interface (STR710F and STR712F)
The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate can
be programmed up to 1 MBaud.
USB Interface (STR710F and STR711F)
The full-speed USB interface is USB V2.0 compliant and provides up to 8 bidirectional/16
unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer and USB
Suspend/Resume functions.
4/49
1
STR71xF - INTRODUCTION
Standard Timers
Each of the four timers have a 16-bit free-running counter with 7-bit prescaler, up to two input
capture/output compare functions, a pulse counter function, and a PWM channel with
selectable frequency.
Realtime Clock (RTC)
The RTC provides a set of continuously running counters driven by a low power 32kHz
internal oscillator. The RTC can be used as a general timebase or clock/calendar/alarm
function. When the STR71xF is in Standby mode the RTC can be kept running, powered by
the low power voltage regulator and driven by the 32kHz internal oscillator.
UARTs
The 4 UARTs allow full duplex, asynchronous, communications with external devices with
independently programmable TX and RX baud rates up to 625 kb/s.
Smart Card Interface
UART1 is configurable to function either as a general purpose UART or as an asynchronous
Smart Card interface as defined by ISO 7816-3. It includes Smart Card clock generation and
provides support features for synchronous cards.
Buffered Serial Peripheral Interfaces (BSPI)
Each of the two SPIs allow full duplex, synchronous communications with external devices,
master or slave communication at up to 5.5Mb/s in Master mode and 4 Mb/s in Slave mode.
I2C Interfaces
The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C
mode (400 kHz) and 7 or 10-bit addressing modes.
One I2C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may be
used at a time.
HDLC interface
The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ,
NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator.
A/D Converter
The Analog to Digital Converter, converts in single channel or up to 4 channels in single-shot
or continuous conversion modes. Resolution is 12-bit with a sample rate of 0.5 kHz (1 kHz in
single channel mode). The input voltage range is 0-2.5V.
5/49
STR71xF - INTRODUCTION
Watchdog
The 16-bit Watchdog Timer protects the application against hardware or software failures and
ensures recovery by generating a reset.
I/O Ports
The 48 I/O ports are programmable as Inputs or Outputs.
External Interrupts
Up to 14 external interrupts are available for application use or to wake-up the application from
STOP mode.
6/49
STR71xF - INTRODUCTION
Figure 1. STR71xF Block Diagram
A[19:0]
D[15:0]
RDN
WEN[1:0]
JTDI
JTCK
JTMS
JTRST
JTDO
DBGRQS
BOOTEN
PRCCU/PLL
EXT. MEM.
INTERFACE (EMI)
ARM7TDMI
CPU
FLASH
MEMORY
64/128/256K
ARM7 NATIVE BUS
CK
CKOUT
RSTIN
A[23:20]
CS[3:0)
JTAG
16K RWW FLASH
RAM
16/32/64K
APB
BRIDGE 1
V18[1:0]
V33[6:0]
VSS[9:0]
V18BKP
AVDD
AVSS
POWER SUPPLY
VREG
INTERRUPT CTL(EIC)
I2C1
2 AF
A/D
BSPI0
4 AF
TIMER0
BSPI1
4 AF
4 AF
TIMER1
UART0
2 AF
2 AF
TIMER2
UART1 /
SMART CARD
3 AF
4 AF
TIMER3
UART2
2 AF
RTC
UART3
2 AF
EXT INT (XTI)
HDLC
3 AF
OSC
14 AF
APB BUS
2 AF
APB BUS
I2C0
4 AF
STDBY
RTCXTO
RTCXTI
WAKEUP
APB
BRIDGE 2
WATCHDOG
USB
P0[15:0]
I/O PORT 0
P1[15:0]
I/O PORT 1
P2[15:0]
I/O PORT 2
USBDP
USBDN
1 AF
CAN
2 AF
AF: alternate function on I/O port pin
7/49
STR71xF - INTRODUCTION
1.2 Related Documentation
Available from www.arm.com:
ARM7TDMI Technical Reference Manual
Available from http://www.st.com:
STR71x Reference Manual
STR7 Flash Programming Reference Manual
AN1774 - Getting Started with STR71xF Software development
AN1775 - Getting Started with STR71xF Hardware development
AN1776 - STR71xF Enhanced Interrupt Controller
AN1777 - STR71xF Memory Mapping
AN1778 - STR71xF Multi-ICE Setup
AN1780 - Real Time Clock with STR71xF
AN1781 - Four 7 Segment Display Drive Using the STR71xF
The above is a selected list only, a full list STR71x application notes can be viewed at
http://www.st.com.
8/49
STR71xF - INTRODUCTION
1.3 Pin Description for 144-Pin Packages
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P0.9/U0.TX/BOOT.0
P0.8/U0.RX/U0.TX
P0.7/S1.SSN
P0.6/S1.SCLK
P0.5/S1.MOSI
VSS
V33
WEn.0
WEn.1
A.19
A.18
A.17
A.16
A.15
A.14
V18
VSS18
P0.4/S1.MISO
P0.3/S0.SSN/I1.SDA
P0.2/S0.SCLK/I1.SCL
P0.1/S0.MOSI/U3.RX
P0.0/S0.MISO/U3.TX
A.13
A.12
A.11
A.10
A.9
A.8
A.7
A.6
A.5
V33
VSS
P1.15/HTXD
N.C.
N.C.
Figure 2. STR710 TQFP Pinout
TQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P1.14/HRXD/I0.SDA
P1.13/HCLK/I0.SCL
P1.10/USBCLK
P1.9
V33
VSS
A.4
A.3
A.2
A.1
A.0
D.15
D.14
D.13
D.12
D.11
D.10
USBDN
USBDP
P1.12/CANTX
P1.11/CANRX
N.C.
P1.8
P1.7/T1.OCMPA
VSSIO-PLL
V33IO-PLL
D.9
D.8
D.7
D.6
D.5
P1.6/T1.OCMPB
P1.5/T1.ICAPB
P1.4/T1.ICAPA
P1.3/T3.ICAPB/AIN.3
P1.2/T3.OCMPA/AIN.2
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
N.C.
TEST
N.C.
V33IO-PLL
N.C.
VSSIO-PLL
N.C.
DBGRQS
CKOUT
CK
P0.15/WAKEUP
N.C.
RTCXTI
RTCXTO
STDBYn
RSTINn
N.C.
VSSBKP
V18BKP
N.C.
N.C.
V18
VSS18
N.C.
D.0
D.1
D.2
D.3
D.4
AVDD
AVSS
N.C.
N.C.
N.C.
P1.0/T3.OCMPB/AIN.0
P1.1/T3.ICAPA/AIN.1
P0.10/U1.RX/U1.TX/SCDATA
RDn
P0.11/U1.TX/BOOT.1
P0.12/SCCLK
VSS
V33
P2.0/CSn.0
P2.1/CSn.1
P0.13/U2.RX/T2.OCMPA
P0.14/U2.TX/T2.ICAPA
P2.2/CSn.2
P2.3/CSn.3
P2.4/A.20
P2.5/A.21
P2.6/A.22
BOOTEN
P2.7/A.23
P2.8
N.C.
N.C.
VSS
V33
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
JTDI
JTMS
JTCK
JTDO
JTRSTn
NU
TEST
9/49
STR71xF - INTRODUCTION
Table 2. STR710 BGA Ball Connections
A
B
C
D
E
F
H
J
K
L
M
P2.12
P2.13
P2.15
JTDI
N.C.
P2.8
G
BOOT
EN
P2.9
1
P0.10
P2.0
P2.1
VSS
P2.2
P2.6
2
VSS
RDn
P0.11
V33
P2.3
JTMS
JTRSTn
TEST
TEST
P2.4
VSS
P2.10
JTCK
NU
V33
N.C.
N.C.
DBG
RQS
3
V33
P0.9
P0.12
P0.13
4
P0.6
P0.7
P0.8
P0.14
P2.5
N.C.
P2.11
JTDO
CK
CKOUT
VSSIOPLL
N.C.
5
A.19
WEn.1
WEn.0
P0.5
P2.7
N.C.
P2.14
nc
nc
P0.15
6
P0.3
A.15
A.16
A.17
A.18
V33
V18
N.C.
7
P0.2
P0.1
P0.4
VSS18
V18
A.14
D.12
8
A.9
A.10
A.11
A.13
P0.0
A.0
9
10
11
VSS
A.8
A.7
V33
N.C.
N.C.
A.5
P1.15
P1.14
A.6
P1.13
P1.10
V33
VSS
A.2
D.15
D.14
D.13
12
A.12
A.4
A.3
P1.9
A.1
N.C.
10/49
D.1
P1.12/
D.11
CANTX
D.10
P1.8
USBDN P1.7
USBDP
VSS
P1.11/ V33IOCANRX
PLL
RTCXRTCXTI
TO
VSS
STDBYn
BKP
VSS18 RSTINn
N.C.
V18BKP
D.0
nc
N.C.
AVSS
D.3
D.2
D.9
D.8
D.5
P1.0
P1.5
P1.4
N.C.
P1.1
P1.3
N.C.
D.4
AVDD
P1.6
D.7
D.6
P1.2
STR71xF - INTRODUCTION
Legend / Abbreviations for Table 3:
Type:
I = input, O = output, S = supply, HiZ= high impedance,
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.8V / 2V with input trigger
TT= TTL 0.3VDD/0.7VDD with input trigger
C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V
Port and control configuration:
– Input:
pu/pd= software enabled internal pull-up or pull down
pu= in reset state, the internal 100kΩ weak pull-up is enabled.
pd = in reset state, the internal 100kΩ weak pull-down is enabled.
– Output:
OD = open drain (logic level)
PP = push-pull
T = true OD, (P-Buffer and protection diode to VDD not implemented), 5V tolerant.
Active in Stdby
PP
OD
Output
Capability
interrupt
Input
Input Level
Pin Name
Type
BGA144
TQFP144
Pin n°
Input Reset State1)
Table 3. STR710 Pin Description
Main
function
(after
reset)
Alternate function
UART1: Receive
Data input
UART1: Transmit data
output.
1
A1
P0.10/U1.RX/
U1.TX/
SC.DATA
I/O pd CT
2
B2
RD
O
3
C2
P0.11/
BOOT.1/
U1.TX
I/O pd CT
4
C3
P0.12/SC.CLK I/O pd CT
5
D1
VSS
S
Ground voltage for digital I/Os
6
D2
V33
S
Supply voltage for digital I/Os
Port
0.10
X 4mA T
4mA X
Note: This pin may be used for Smartcard
DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function
Output. The pin will be tri-stated except when
UART transmission is in progress
X
External Memory Interface: Active low read signal for
external memory. It maps to the OE_N input of the external components.
X
Port
0.11
Select Boot Con- UART1: Transmit data
figuration input
output.
Port
0.12
Smartcard reference clock output
4mA
External Memory Interface: Select Memory
Bank 0 output
7
B1
P2.0/CS.0
I/O pu CT
8mA X
X
Port 2.0
8
C1
P2.1/CS.1
pu
I/O 2) CT
8mA X
X
Port 2.1
External Memory Interface: Select Memory
Bank 1 output
9
D3
P0.13/U2.RX/
T2.OCMPA
I/O pu CT
X 4mA X
X
Port
0.13
UART2: Receive
Data input
10
D4
P0.14/U2.TX/
T2.ICAPA
I/O pu CT
4mA X
X
Port
0.14
UART2: Transmit Timer2: Input Capture A
data output
input
11
E1
P2.2/CS.2
pu
I/O 2) CT
8mA X
X
Port 2.2
External Memory Interface: Select Memory
Bank 3 output
Note: This pin is forced to output mode at reset to allow boot from external memory
Timer2: Output Compare
A output
11/49
STR71xF - INTRODUCTION
Active in Stdby
Alternate function
External Memory Interface: Select Memory
Bank 4 output
12
E2
P2.3/CS.3
pu
I/O 2) CT
8mA X
X
Port 2.3
13
E3
P2.4/A.20
pd
I/O 3) CT
8mA X
X
Port 2.4
14
E4
P2.5/A.21
pd
I/O 3) CT
8mA X
X
Port 2.5 External Memory Interface: address bus
15
F1
P2.6/A.22
pd
I/O 3) CT
8mA X
X
Port 2.6
16
G1 BOOTEN
Pin Name
I
interrupt
PP
Main
function
(after
reset)
OD
Capability
Output
BGA144
Input Level
Input
TQFP144
Type
Pin n°
Input Reset State1)
Table 3. STR710 Pin Description
CT
pd
Boot control input. Enables sampling of BOOT[1:0] pins
17
E5
P2.7/A.23
I/O 3)
CT
8mA X
X
Port 2.7 External Memory Interface: address bus
18
F2
P2.8
I/O pu CT
X 4mA X
X
Port 2.8 External interrupt INT2
19
F4
N.C.
Not connected (not bonded)
20
F5
N.C.
Not connected (not bonded)
21
F3
VSS
S
22
F6
V33
S
23
G2 P2.9
I/O pu CT
X 4mA X
X
Port 2.9 External interrupt INT3
24
G3 P2.10
I/O pu CT
X 4mA X
X
Port
2.10
External interrupt INT4
25
G4 P2.11
I/O pu CT
X 4mA X
X
Port
2.11
External interrupt INT5
26
H1
P2.12
I/O pu CT
4mA X
X
Port
2.12
27
J1
P2.13
I/O pu CT
4mA X
X
Port
2.13
28
G5 P2.14
I/O pu CT
4mA X
X
Port
2.14
29
K1
P2.15
I/O pu CT
4mA X
X
Port
2.15
30
L1
JTDI
I
TT
JTAG Data input. External pull-up required.
31
H2
JTMS
I
TT
JTAG Mode Selection Input. External pull-up required.
32
H3
JTCK
I
C
JTAG Clock Input. External pull-up or pull-down required.
33
H4
JTDO
O
34
J2
JTRST
I
35
J3
NU
36
K2
TEST
Reserved, must be forced to ground.
37
L3
N.C.
Not connected (not bonded)
38
L2
TEST
Reserved, must be forced to ground.
39
M1 N.C.
12/49
Ground voltage for digital I/Os
Supply voltage for digital I/Os
8mA
TT
X
JTAG Data output. Note: Reset state = HiZ.
JTAG Reset Input. External pull-up required.
Reserved, must be forced to ground.
Not connected (not bonded)
STR71xF - INTRODUCTION
42
Active in Stdby
PP
OD
Output
Capability
41
interrupt
K3
Input
Input Level
BGA144
40
Pin Name
Type
TQFP144
Pin n°
Input Reset State1)
Table 3. STR710 Pin Description
Main
function
(after
reset)
Alternate function
S
Supply voltage for digital I/O circuitry and for PLL reference
M2 N.C.
Not connected (not bonded)
L4
S
Ground voltage for digital I/O circuitry and for PLL reference
V33IO-PLL
VSSIO-PLL
43
M4 N.C.
44
M3 DBGRQS
I
Not connected (not bonded)
45
K4
CKOUT
O
46
J4
CK
I
C
47
P0.15/WAKEM5
UP
I
pu TT
48
L5
CT
Debug Mode request input (active high)
8mA
Clock output (fPCLK2) Note: Enabled by CKDIS register
in APB Bridge 2
X
Reference clock input
X 4mA
X
Port
0.15
Wakeup from Standby mode input.
N.C.
Not connected (not bonded)
49
K5
RTCXTI
Realtime Clock input and input of 32 kHz oscillator amplifier circuit
50
J5
RTCXTO
Output of 32 kHz oscillator amplifier circuit
Input: Hardware Standby mode entry input active low.
Caution: External pull-up to V33 required to select normal mode.
51
M6 STDBY
I/O
CT
4mA X
Output: Standby mode active low output following SoftX ware Standby mode entry.
Note: In Standby mode all pins are in high impedance
except those marked Active in Stdby
52
M7 RSTIN
53
J6
N.C.
54
L6
VSSBKP
I
CT
X Reset input
S
X Stabilisation for low power voltage regulator.
S
Stabilisation for low power voltage regulator. Requires
external capacitors of at least 1µF between V18BKP and
X VSS18BKP. See Figure 5.
Note: If the low power voltage regulator is bypassed,
this pin can be connected to an external 1.8V supply.
Not connected (not bonded)
55
K6
V18BKP
56
H5
N.C.
Not connected (not bonded)
57
H6
N.C.
Not connected (not bonded)
58
G6 V18
S
Stabilisation for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and
VSS18. See Figure 5.
59
L7
VSS18
S
Stabilisation for main voltage regulator.
60
K7
N.C.
Not connected (not bonded)
13/49
STR71xF - INTRODUCTION
I/O
8mA
62
H7
D.1
I/O
8mA
63
M8 D.2
I/O
8mA
64
L8
Active in Stdby
D.0
PP
J7
interrupt
61
Pin Name
OD
Capability
Output
BGA144
Input Level
Input
TQFP144
Type
Pin n°
Input Reset State1)
Table 3. STR710 Pin Description
Main
function
(after
reset)
Alternate function
External Memory Interface: data bus
D.3
I/O
8mA
65 M10 D.4
I/O
8mA
66 M11 VDDA
S
Supply voltage for A/D Converter
67
S
Ground voltage for A/D Converter
K8
VSSA
68
J8
N.C.
Not connected (not bonded)
69
L9
N.C.
Not connected (not bonded)
70
M9 N.C.
Not connected (not bonded)
71
K9
P1.0/T3.OCMPB/AIN.0
I/O pu CT
4mA X
X
Port 1.0
P1.1/T3.ICA72 L10 PA/T3.EXTCLK/AIN.1
I/O pu CT
4mA X
X
Timer 3: Input
Port 1.1 Capture A or Ex- ADC: Analog input 1
ternal Clock input
P1.2/T3.OCMI/O pu CT
PA/AIN.2
4mA X
X
Port 1.2
Timer 3: Output
Compare A
ADC: Analog input 2
73 M12
Timer 3: Output
Compare B
ADC: Analog input 0
P1.3/
74 L11 T3.ICAPB/
AIN.3
I/O pu CT
4mA X
X
Port 1.3
Timer 3: Input
Capture B
ADC: Analog input 3
P1.4/T1.ICA75 K11 PA/T1.EXTCLK
I/O pu CT
4mA X
X
Port 1.4
Timer 1: Input
Capture A
Timer 1: External Clock
input
76 K10
P1.5/
T1.ICAPB
I/O pu CT
4mA X
X
Port 1.5
Timer 1: Input
Capture B
77 J12
P1.6/T1.OCMPB
I/O pu CT
4mA X
X
Port 1.6
Timer 1: Output
Compare B
78 J11 D.5
I/O
8mA
79 L12 D.6
I/O
8mA
80 K12 D.7
I/O
8mA
81 J10 D.8
I/O
8mA
82
I/O
8mA
J9
D.9
External Memory Interface: data bus
83 H12 V33IO-PLL
S
Supply voltage for digital I/O circuitry and for PLL reference
84 H11 VSSIO-PLL
S
Ground voltage for digital I/O circuitry and for PLL reference
85 H10
P1.7/T1.OCMI/O pu CT
PA
4mA X
X
Port 1.7
86
P1.8
4mA X
X
Port 1.8
H9
87 F12 N.C.
14/49
I/O pd CT
Timer 1: Output
Compare A
Not connected (not bonded)
STR71xF - INTRODUCTION
Alternate function
PP
Main
function
(after
reset)
OD
Active in Stdby
Output
Capability
interrupt
Input
Input Level
Pin Name
Type
BGA144
TQFP144
Pin n°
Input Reset State1)
Table 3. STR710 Pin Description
88 G12 P1.11/CANRX
I/O pu CT X 4mA X
X
Port
1.11
CAN: receive data input
Note: On STR710 and STR712 only
89
I/O pu CT X 4mA X
X
Port
1.12
CAN: Transmit data output
H8
P1.12/CANTX
Note: On STR710 and STR712 only
USB bidirectional data (data +). Reset state = HiZ
Note: On STR710 and STR711 only
90 G11 USBDP
I/O
CT
91 G10 USBDN
I/O
CT
92
G9 D.10
I/O
8mA
93
G8 D.11
I/O
8mA
94
This pin requires an external pull-up to V33 to maintain
a high level.
USB bidirectional data (data -). Reset state = HiZ
Note: On STR710 and STR711 only.
G7 D.12
I/O
8mA
95 F11 D.13
I/O
8mA
96 F10 D.14
I/O
8mA
97
F9
D.15
I/O
8mA
98
F8
A.0
O
8mA
99 E12 A.1
O
8mA
100 E11 A.2
O
8mA
101 C12 A.3
O
8mA
102 B12 A.4
O
8mA
103 E10 VSS
S
104 E9
S
V33
105 D12 P1.9
External Memory Interface: data bus
External Memory Interface: address bus
Ground voltage for digital I/O circuitry
Supply voltage for digital I/O circuitry
I/O pd CT
4mA X
X
Port 1.9
106 D11
P1.10/USBCLK
I/O pu C/T
4mA X
X
Port
1.10
USB: 48 MHZ
clock input
107 D10
P1.13/HCLK/
I0.SCL
I/O pu CT X 4mA X
X
Port
1.13
HDLC: reference
clock input
I2C clock
108 C11
P1.14/HRXD/
I0.SDA
I/O pu CT X 4mA X
X
Port
1.14
HDLC: Receive
data input
I2C serial data
109 B11 N.C.
Not connected (not bonded)
110 B10 N.C.
Not connected (not bonded)
111 C10 P1.15/HTXD
I/O pu CT X 4mA X
Port
1.15
112 A9
VSS
S
Ground voltage for digital I/O circuitry
113 B9
V33
S
Supply voltage for digital I/O circuitry
X
HDLC: Transmit data output
15/49
STR71xF - INTRODUCTION
114 C9
A.5
115 D9
O
A.6
O
8mA
O
8mA
117 A10 A.8
O
8mA
118 A8
O
8mA
119 B8
A.10
O
8mA
120 C8
A.11
O
8mA
121 A12 A.12
O
8mA
122 D8
O
8mA
123 E8
A.13
P0.0/S0.MISO/
I/O pu CT
U3.TX
4mA X
P0.1/S0.MOSI/
I/O pu CT X 4mA X
U3.RX
125 A7
P0.2/
S0.SCLK/
I1.SCL
126 A6
127 C7
P0.4/S1.MISO
128 D7
Active in Stdby
PP
Alternate function
External Memory Interface: address bus
SPI0 Master in/
Slave out data
124 B7
P0.3/S0.SS/
I1.SDA
Main
function
(after
reset)
8mA
116 A11 A.7
A.9
OD
Output
Capability
interrupt
Input
Input Level
Pin Name
Type
BGA144
TQFP144
Pin n°
Input Reset State1)
Table 3. STR710 Pin Description
X
Port 0.0 Note: Programming AF function selects
UART by default. BSPI must be enabled by
SPI_EN bit in the BOOTCR register.
BSPI0: Master
out/Slave in data
X
X
UART3: Receive Data input
Port 0.1 Note: Programming AF function selects
UART by default. BSPI must be enabled by
SPI_EN bit in the BOOTCR register.
BSPI0: Serial
Clock
I/O pu CT X 4mA X
UART3 Transmit data
output
I2C1: Serial clock
Port 0.2 Note: Programming AF function selects I2C
by default. BSPI must be enabled by SPI_EN
bit in the BOOTCR register.
SPI0: Slave Select input active
low.
I2C1: Serial Data
I/O pu CT
4mA X
X
Port 0.3
4mA X
X
Port 0.4 SPI1: Master in/Slave out data
VSS18
I/O pu CT
S
129 E7
V18
S
130 F7
A.14
O
8mA
131 B6
A.15
O
8mA
132 C6
A.16
O
8mA
133 D6
A.17
O
8mA
134 E6
A.18
O
8mA
135 A5
A.19
O
8mA
16/49
Note: Programming AF function selects I2C
by default. BSPI must be enabled by SPI_EN
bit in the BOOTCR register.
Stabilisation for main voltage regulator.
Stabilisation for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and
VSS18. See Figure 5.
External Memory Interface: address bus
STR71xF - INTRODUCTION
Active in Stdby
PP
OD
Output
Capability
interrupt
Input
Input Level
Pin Name
Type
BGA144
TQFP144
Pin n°
Input Reset State1)
Table 3. STR710 Pin Description
Main
function
(after
reset)
Alternate function
136 B5
WE.1
O
8mA
External Memory Interface: active low MSB write enable output
137 C5
WE.0
O
8mA
External Memory Interface: active low LSB write enable
output
138 A3
V33
S
139 A2
VSS
S
140 D5
P0.5/S1.MOSI
Supply voltage for digital I/Os
Ground voltage for digital I/Os
X
141 A4
I/O pu CT
4mA X
P0.6/S1.SCLK I/O pu CT X 4mA X
X
Port 0.6 SPI1: Serial Clock
142 B4
P0.7/S1.SS
X
Port 0.7 SPI1: Slave Select input active low
I/O pu CT
4mA X
Port 0.5 SPI1: Master out/Slave In data
Port 0.8
143 C4
P0.8/U0.RX/
U0.TX
I/O pd CT
X 4mA T
144 B3
P0.9/U0.TX/
BOOT.0
I/O pd CT
4mA X
UART0: Receive
Data input
UART0: Transmit data
output.
Note: This pin may be used for single wire UART (half
duplex) if programmed as Alternate Function Output.
The pin will be tri-stated except when UART transmission is in progress
X
Port 0.9
Select Boot Con- UART0: Transmit data
figuration input
output
1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to
Table 7, “Port Bit Configuration Table,” on page 26. The Port bit configuration at reset is
PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column
which specifies whether the pull-up or pull-down is enabled at reset
2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must
be configured by software as Alternate Function (see Table 7, “Port Bit Configuration Table,”
on page 26) to be used by the External Memory Interface.
3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output
Address 0x0000 0000 using the External Memory Interface. To access memory banks greater
than 1Mbyte, they need to be configured by software as Alternate Function (see Table 7, “Port
Bit Configuration Table,” on page 26).
17/49
STR71xF - INTRODUCTION
1.4 Pin Description for 64-Pin Packages
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P0.9/U0.TX/BOOT.0
P0.8/U0.RX/U0.TX
P0.7/S1.SSN
P0.6/S1.SCLK
P0.5/S1.MOSI
VSS
V18
VSS18
P0.4/S1.MISO
P0.3/S0.SSN/I1.SDA
P0.2/S0.SCLK/I1.SCL
P0.1/S0.MOSI/U3.RX
P0.0/S0.MISO/U3.TX
V33
VSS
P1.15/HTXD
Figure 3. STR712F/STR715F TQFP64 Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TQFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.14/HRXD/I0.SDA
P1.13/HCLK/I0.SCL
P1.10
P1.9
VSS
P1.12/CANTX1)
P1.11/CANRX1)
P1.8
P1.7/T1.OCMPA
VSSIO-PLL
V33IO-PLL
P1.6/T1.OCMPB
P1.5/T1.ICAPB
P1.4/T1.ICAPA
P1.3/T3.ICAPB/AIN.3
P1.2/T3.OCMPA/AIN.2
V33IO-PLL
VSSIO-PLL
CK
P0.15/WAKEUP
RTCXTI
RTCXTO
nSTDBY
nRSTIN
VSSBKP
V18BKP
V18
VSS18
AVDD
AVSS
P1.0/T3.OCMPB/AIN.0
P1.1/T3.ICAPA/AIN.1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P0.10/U1.RX/U1.TX/SCDATA
P0.11/U1.TX/BOOT.1
P0.12/SCCLK
VSS
P0.13/U2.RX/T2.OCMPA
P0.14/U2.TX/T2.ICAPA
BOOTEN
VSS
V33
JTDI
JTMS
JTCK
JTDO
nJTRST
NU
TEST
1)
18/49
CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os.
STR71xF - INTRODUCTION
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P0.9/U0.TX/BOOT.0
P0.8/U0.RX/U0.TX
P0.7/S1.SSN
P0.6/S1.SCLK
P0.5/S1.MOSI
VSS
V18
VSS18
P0.4/S1.MISO
P0.3/S0.SSN/I1.SDA
P0.2/S0.SCLK/I1.SCL
P0.1/S0.MOSI/U3.RX
P0.0/S0.MISO/U3.TX
V33
VSS
P1.15/HTXD
Figure 4. STR711F TQFP64 Pinout
TQFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.14/HRXD/I0.SDA
P1.13/HCLK/I0.SCL
P1.10/USBCLK
P1.9
VSS
USBDN
USBDP
P1.8
P1.7/T1.OCMPA
VSSIO-PLL
V33IO-PLL
P1.6/T1.OCMPB
P1.5/T1.ICAPB
P1.4/T1.ICAPA
P1.3/T3.ICAPB/AIN.3
P1.2/T3.OCMPA/AIN.2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V33IO-PLL
VSSIO-PLL
CK
P0.15/WAKEUP
RTCXTI
RTCXTO
nSTDBY
nRSTIN
VSSBKP
V18BKP
V18
VSS18
AVDD
AVSS
P1.0/T3.OCMPB/AIN.0
P1.1/T3.ICAPA/AIN.1
P0.10/U1.RX/U1.TX/SCDATA
P0.11/U1.TX/BOOT.1
P0.12/SCCLK
VSS
P0.13/U2.RX/T2.OCMPA
P0.14/U2.TX/T2.ICAPA
BOOTEN
VSS
V33
JTDI
JTMS
JTCK
JTDO
nJTRST
NU
TEST
19/49
STR71xF - INTRODUCTION
Table 4. STR711F BGA Ball Connections
1
2
3
4
5
6
7
8
A
P0.10
P0.9
P0.5
VSS18
P0.2
V33
VSS
P1.15
B
P0.11
VSS
P0.7
VSS
P0.4
P0.1
P0.0
P1.14
C
P0.12
P0.13
BOOTEN
P0.8
V18
P0.3
P1.10
VSS
D
P0.14
VSS
JTDI
JTDO
P0.6
P1.13
USBDN
P1.8
E
V33
JTMS
NU
AVDD
P1.9
USBDP
P1.7
V33IO-PLL
F
JTCK
JTRSTn
STDBYn
V18BKP
P1.0
VSSIO-PLL
P1.6
P1.4
G
TEST
P0.15
RTCXTI
RSTINn
V18
AVSS
P1.5
P1.3
H
V33IO-PLL
VSSIO-PLL
CK
RTCXTO
VSSBKP
VSS18
P1.1
P1.2
E
V33
JTMS
NU
AVDD
P1.9
P1.11/
CANRX1)
F
JTCK
JTRSTn
STDBYn
V18BKP
P1.0
G
TEST
P0.15
RTCXTI
RSTINn
V18
H
V33IO-PLL
VSSIO-PLL
CK
RTCXTO
VSSBKP
VSSIO-PLL
AVSS
VSS18
P1.7
P1.6
P1.5
P1.1
V33IO-PLL
P1.4
P1.3
P1.2
Table 5. STR712F/715F BGA Ball Connections
1
2
3
4
5
A
P0.10
P0.9
P0.5
VSS18
P0.2
B
P0.11
VSS
P0.7
VSS
P0.4
C
P0.12
P0.13
BOOTEN
P0.8
V18
D
P0.14
VSS
JTDI
JTDO
P0.6
6
V33
P0.1
P0.3
P1.13
7
VSS
P0.0
P1.10
8
P1.15
P1.14
VSS
1)CANTX
20/49
P1.12/
CANTX1)
P1.8
and CANRX in STR712F only, in STR715F they are general purpose I/Os.
STR71xF - INTRODUCTION
Legend / Abbreviations for Table 3:
Type:
I = input, O = output, S = supply, HiZ= high impedance,
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.8V / 2V with input trigger
TT= TTL 0.3VDD/0.7VDD with input trigger
C/T = Programmable levels: CMOS 0.3VDD/0.7VDD or TTL 0.8V / 2V
Port and control configuration:
– Input:
pu/pd= software enabled internal pull-up or pull down
pu= in reset state, the internal 100kΩ weak pull-up is enabled.
pd = in reset state, the internal 100kΩ weak pull-down is enabled.
– Output:
OD = open drain (logic level)
PP = push-pull
T = true OD, (P-Buffer and protection diode to VDD not implemented), 5V tolerant.
Active in Stdby
PP
OD
Output
Capability
interrupt
Input
Input Level
Pin Name
Type
BGA64
TQFP64
Pin n°
Input Reset State1)
Table 6. STR711/STR712/STR715 Pin Description
Main
function
(after
reset)
Alternate function
UART1: Receive
Data input
UART1: Transmit data
output.
1
P0.10/U1.RX/
A1 U1.TX/
SC.DATA
I/O pd CT
X 4mA T
2
P0.11/
B1 BOOT.1/
U1.TX
I/O pd CT
4mA X
3
C1 P0.12/SC.CLK I/O pd CT
4
B2 VSS
P0.13/U2.RX/
C2
T2.OCMPA
I/O pu CT
X 4mA X
X
Port
0.13
UART2: Receive
Data input
P0.14/U2.TX/
T2.ICAPA
I/O pu CT
4mA X
X
Port
0.14
UART2: Transmit Timer2: Input Capture A
data output
input
5
6
D1
7
C3 BOOTEN
8
D2 VSS
E1 V33
9
X
4mA
S
I
Port
0.10
Note: This pin may be used for Smartcard
DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function
Output. The pin will be tri-stated except when
UART transmission is in progress
Port
0.11
Select Boot Con- UART1: Transmit data
figuration input
output.
Port
0.12
Smartcard reference clock output
Ground voltage for digital I/Os
CT
Timer2: Output Compare
A output
Boot control input. Enables sampling of BOOT[1:0] pins
S
Ground voltage for digital I/Os
S
Supply voltage for digital I/Os
10 D3 JTDI
I
TT
JTAG Data input. External pull-up required.
11 E2 JTMS
I
TT
JTAG Mode Selection Input. External pull-up required.
12
F1 JTCK
I
C
JTAG Clock Input. External pull-up or pull-down required.
13 D4 JTDO
O
14
I
F2 JTRST
15 E3 NU
8mA
TT
X
JTAG Data output. Note: Reset state = HiZ.
JTAG Reset Input. External pull-up required.
Reserved, must be forced to ground.
21/49
STR71xF - INTRODUCTION
16 G1 TEST
Active in Stdby
PP
OD
Output
Capability
interrupt
Input
Input Level
Pin Name
Type
BGA64
TQFP64
Pin n°
Input Reset State1)
Table 6. STR711/STR712/STR715 Pin Description
Main
function
(after
reset)
Alternate function
Reserved, must be forced to ground.
17 H1 V33IO-PLL
S
Supply voltage for digital I/O circuitry and for PLL reference
18 H2 VSSIO-PLL
S
Ground voltage for digital I/O circuitry and for PLL reference
19 H3 CK
P0.15/WAKE20 G2
UP
I
I
C
pu TT
Reference clock input
Port
X
0.15
X 4mA
Wakeup from Standby mode input.
Realtime Clock input and input of 32 kHz oscillator amplifier circuit
21 G3 RTCXTI
22 H4 RTCXTO
Output of 32 kHz oscillator amplifier circuit
Input: Hardware Standby mode entry input active low.
Caution: External pull-up to V33 required to select normal mode.
23
F3 STDBY
I/O
CT
Output: Standby mode active low output following SoftX ware Standby mode entry.
4mA X
Note: In Standby mode all pins are in high impedance
except those marked Active in Stdby
24 G4 RSTIN
I
25 H5 VSSBKP
26
F4 V18BKP
CT
X Reset input
S
X Stabilisation for low power voltage regulator.
S
Stabilisation for low power voltage regulator. Requires
external capacitors of at least 1µF between V18BKP and
X VSS18BKP. See Figure 5.
Note: If the low power voltage regulator is bypassed,
this pin can be connected to an external 1.8V supply.
27 G5 V18
S
Stabilisation for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and
VSS18. See Figure 5.
28 H6 VSS18
S
Stabilisation for main voltage regulator.
29 E4 VDDA
30 G6 VSSA
S
Supply voltage for A/D Converter
S
Ground voltage for A/D Converter
P1.0/T3.OCMPB/AIN.0
I/O pu CT
4mA X
X
Port 1.0
P1.1/T3.ICA32 H7 PA/T3.EXTCLK/AIN.1
I/O pu CT
4mA X
X
Timer 3: Input
Port 1.1 Capture A or Ex- ADC: Analog input 1
ternal Clock input
P1.2/T3.OCMI/O pu CT
PA/AIN.2
4mA X
X
Port 1.2
Timer 3: Output
Compare A
ADC: Analog input 2
4mA X
X
Port 1.3
Timer 3: Input
Capture B
ADC: Analog input 3
31
F5
33 H8
P1.3/
34 G8 T3.ICAPB/
AIN.3
22/49
I/O pu CT
Timer 3: Output
Compare B
ADC: Analog input 0
STR71xF - INTRODUCTION
Alternate function
PP
Main
function
(after
reset)
OD
Active in Stdby
Output
Capability
interrupt
P1.4/T1.ICAF8 PA/T1.EXTCLK
Input
Input Level
BGA64
35
Pin Name
Type
TQFP64
Pin n°
Input Reset State1)
Table 6. STR711/STR712/STR715 Pin Description
I/O pu CT
4mA X
X
Port 1.4
Timer 1: Input
Capture A
36 G7
P1.5/
T1.ICAPB
I/O pu CT
4mA X
X
Port 1.5
Timer 1: Input
Capture B
37
P1.6/T1.OCMPB
I/O pu CT
4mA X
X
Port 1.6
Timer 1: Output
Compare B
F7
Timer 1: External Clock
input
38 E8 V33IO-PLL
S
Supply voltage for digital I/O circuitry and for PLL reference
39
S
Ground voltage for digital I/O circuitry and for PLL reference
F6 VSSIO-PLL
40 E7
P1.7/T1.OCMI/O pu CT
PA
4mA X
X
Port 1.7
Timer 1: Output
Compare A
41 D8 P1.8
I/O pd CT
4mA X
X
Port 1.8
42 E6 P1.11/CANRX
I/O pu CT X 4mA X
X
Port
1.11
CAN: receive data input
Note: On STR710 and STR712 only
43 D7 P1.12/CANTX
I/O pu CT X 4mA X
X
Port
1.12
CAN: Transmit data output
Note: On STR710 and STR712 only
USB bidirectional data (data +). Reset state = HiZ
42 E6 USBDP
I/O
CT
43 D7 USBDN
I/O
CT
44 C8 VSS
45 E5 P1.9
S
P1.10/USB46 C7
CLK
Note: On STR710 and STR711 only
This pin requires an external pull-up to V33 to maintain
a high level.
USB bidirectional data (data -). Reset state = HiZ
Note: On STR710 and STR711 only.
Ground voltage for digital I/O circuitry
I/O pd CT
4mA X
X
Port 1.9
I/O pu C/T
4mA X
X
Port
1.10
USB: 48 MHZ
clock input
47 D6
P1.13/HCLK/
I0.SCL
I/O pu CT X 4mA X
X
Port
1.13
HDLC: reference
clock input
I2C clock
48 B8
P1.14/HRXD/
I0.SDA
I/O pu CT X 4mA X
X
Port
1.14
HDLC: Receive
data input
I2C serial data
49 A8 P1.15/HTXD
I/O pu CT X 4mA X
X
Port
1.15
HDLC: Transmit data output
50 A7 VSS
51 A6 V33
S
Ground voltage for digital I/O circuitry
S
Supply voltage for digital I/O circuitry
52 B7
P0.0/S0.MISO/
I/O pu CT
U3.TX
SPI0 Master in/
Slave out data
4mA X
X
UART3 Transmit data
output
Port 0.0 Note: Programming AF function selects
UART by default. BSPI must be enabled by
SPI_EN bit in the BOOTCR register.
23/49
STR71xF - INTRODUCTION
53 B6
P0.1/S0.MOSI/
I/O pu CT X 4mA X
U3.RX
P0.2/
54 A5 S0.SCLK/
I1.SCL
P0.3/S0.SS/
55 C6
I1.SDA
Active in Stdby
PP
OD
Output
Capability
interrupt
Input
Input Level
Pin Name
Type
BGA64
TQFP64
Pin n°
Input Reset State1)
Table 6. STR711/STR712/STR715 Pin Description
Main
function
(after
reset)
Alternate function
BSPI0: Master
out/Slave in data
X
Port 0.1 Note: Programming AF function selects
UART by default. BSPI must be enabled by
SPI_EN bit in the BOOTCR register.
BSPI0: Serial
Clock
I/O pu CT X 4mA X
X
UART3: Receive Data input
I2C1: Serial clock
Port 0.2 Note: Programming AF function selects I2C
by default. BSPI must be enabled by SPI_EN
bit in the BOOTCR register.
SPI0: Slave Select input active
low.
I2C1: Serial Data
I/O pu CT
4mA X
X
Port 0.3
4mA X
X
Port 0.4 SPI1: Master in/Slave out data
57 A4 VSS18
I/O pu CT
S
58 C5 V18
S
Stabilisation for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V18 and
VSS18. See Figure 5.
59 B4 VSS
60 A3 P0.5/S1.MOSI
S
Ground voltage for digital I/Os
56 B5 P0.4/S1.MISO
I/O pu CT
Note: Programming AF function selects I2C
by default. BSPI must be enabled by SPI_EN
bit in the BOOTCR register.
Stabilisation for main voltage regulator.
4mA X
X
61 D5 P0.6/S1.SCLK I/O pu CT X 4mA X
X
Port 0.6 SPI1: Serial Clock
62 B3 P0.7/S1.SS
X
Port 0.7 SPI1: Slave Select input active low
I/O pu CT
4mA X
Port 0.5 SPI1: Master out/Slave In data
Port 0.8
63 C4
P0.8/U0.RX/
U0.TX
I/O pd CT
X 4mA T
64 A2
P0.9/U0.TX/
BOOT.0
I/O pd CT
4mA X
UART0: Receive
Data input
UART0: Transmit data
output.
Note: This pin may be used for single wire UART (half
duplex) if programmed as Alternate Function Output.
The pin will be tri-stated except when UART transmission is in progress
X
Port 0.9
Select Boot Con- UART0: Transmit data
figuration input
output
1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to
Table 7, “Port Bit Configuration Table,” on page 26. The Port bit configuration at reset is
PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column
which specifies whether the pull-up or pull-down is enabled at reset
2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must
be configured by software as Alternate Function (see Table 7, “Port Bit Configuration Table,”
on page 26) to be used by the External Memory Interface.
24/49
STR71xF - INTRODUCTION
3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output
Address 0x0000 0000 using the External Memory Interface. To access memory banks greater
than 1Mbyte, they need to be configured by software as Alternate Function (see Table 7, “Port
Bit Configuration Table,” on page 26).
25/49
STR71xF - INTRODUCTION
1.5 External Connections
Figure 5. Recommended External Connection of V18 and V18BKP pins
33 nF
33 nF
129 128
58 57
V18
V18
TQFP144
V18BKP
TQFP64
V18
V18BKP
54 55 58 59
1µF
V18
25 26 27 28
10 µF
10 µF
1µF
1.6 I/O Port Configuration
Table 7. Port Bit Configuration Table
Port Configuration
Registers (bit)
Values
PC0(n)
0
1
0
1
0
1
0
1
PC1(n)
0
0
1
1
0
0
1
1
PC2(n)
0
0
0
0
1
1
1
1
HiZ/AIN
IN
IN
IPUPD
OUT
OUT
AF
AF
Output
TRI
TRI
TRI
WP
OD
PP
OD
PP
Input
AIN
TTL
CMOS
CMOS
N.A.
N.A.
CMOS
CMOS
Configuration
Notes:
AF: Alternate Function
AIN: Analog Input
IPUPD: Input Pull Up /Pull Down
CMOS: CMOS Input levels
HiZ: High impedance
IN: Input
N.A. not applicable. In Output mode, a read access to the
port gets the output latch value).
26/49
OD: Open Drain
OUT: Output
PP: Push-Pull
TRI: Tristate
TTL: TTL Input levels
WP: Weak Push-Pull
STR71xF - INTRODUCTION
1.7 Memory Mapping
Figure 6. Memory Map
APB Memory Space
0xFFFF FFFF
Addressable Memory Space
4 Gbytes
0xFFFF FFFF
EIC
0xFFFF F800
0xE000 E000
4K
0xFFFF F800
EIC
4K
WDG
4K
RTC
4K
TIMER 3
4K
TIMER 2
4K
TIMER 1
4K
TIMER 0
4K
CLKOUT
4K
ADC
4K
0xE000 D000
0xE000 C000
7
0xE000 B000
0xE000 0000
64K
APB2
0xE000 A000
0xE000 9000
0xE000 8000
6
0xE000 7000
0xC000 0000
64K
APB1
0xE000 6000
FLASH Memory Space
272 Kbytes + regs
0xE000 5000
0x4010 DFBF
FLASH Registers
5
20b
0xE000 4000
0x4010 0000
reserved
4K
IOPORT 2
4K
IOPORT 1
4K
IOPORT 0
4K
reserved
4K
XTI
4K
APB BRIDGE 2 REGS
4K
0xE000 3000
0xA000 0000
reserved
1K
PRCCU
0xE000 2000
0x400C 4000
0xE000 1000
B1F1
8K
0xE000 0000
4
0x400C 2000
B1F0
0x8000 0000
Reserved
4K
0xC001 0000
reserved
0xC000 F000
0x4004 0000
3
reserved
8K
0x400C 0000
0xC000 E000
0xC000 D000
0x6000 0000
EXTMEM
B0F7
1K
64K
0xC000 C000
0xC000 B000
reserved
4K
HDLC + RAM
4K
reserved
4K
reserved
4K
BSPI 1
4K
BSPI 0
4K
CAN
4K
USB + RAM
4K
UART 3
4K
UART 2
4K
UART 1
4K
UART 0
4K
reserved
4K
I2C 1
4K
I2C 0
4K
APB BRIDGE 1 REGS
4K
0x4003 0000
0xC000 A000
2
B0F6
0x4000 0000
64K
256K+16K+32b
FLASH
0xC000 8000
0x4002 0000
0xC000 7000
0xC000 6000
1
B0F5
0x2000 0000
0xC000 9000
64K
64K
RAM
0xC000 5000
0xC000 4000
0x4001 0000
0xC000 3000
0
0x0000 0000
FLASH/RAM/EMI
0x4000
0x4000
0x4000
0x4000
0x4000
8000
6000
4000
2000
0000
B0F4
32K
B0F3
B0F2
B0F1
B0F0
8K
8K
8K
8K
0xC000 2000
0xC000 1000
0xC000 0000
(*) FLASH aliased at 0x0000 0000h
by system decoder for booting with
valid instruction upon RESET
from Block B0 (8 Kbytes)
Reserved
27/49
STR71xF - INTRODUCTION
Figure 7. Mapping of Flash Memory Versions
FLASH Memory Space
64 Kbytes + 16K RWW + regs
0x4010 DFBF
FLASH Memory Space
128 Kbytes + 16K RWW + regs
0x4010 DFBF
FLASH Registers
20b
0x4010 0000
20b
8K
0x400C 2000
0x400C 4000
8K
B1F1
0x400C 2000
B1F0
8K
0x400C 0000
8K
B1F0
reserved
0x4003 0000
reserved
64K
reserved
64K
0x4002 0000
64K
B0F4
32K
0x4001 0000
64K
reserved
B0F3
B0F2
B0F1
B0F0
8K
8K
8K
8K
0x4000
0x4000
0x4000
0x4000
0x4000
STR715FR0xx
STR711FR0xx
STR712FR0xx
8000
6000
4000
2000
0000
64K
B0F6
64K
B0F5
64K
B0F4
32K
B0F3
B0F2
B0F1
B0F0
8K
8K
8K
8K
0x4002 0000
B0F5
64K
B0F4
32K
0x4001 0000
8000
6000
4000
2000
0000
B0F7
0x4003 0000
0x4002 0000
reserved
8K
0x4004 0000
0x4003 0000
reserved
B1F0
reserved
64K
8K
0x400C 0000
0x4004 0000
reserved
B1F1
0x400C 2000
0x400C 0000
0x4004 0000
20b
reserved
0x400C 4000
B1F1
FLASH Registers
0x4010 0000
reserved
0x400C 4000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4010 DFBF
FLASH Registers
0x4010 0000
reserved
FLASH Memory Space
256 Kbytes + 16K RWW + regs
0x4001 0000
8K
8K
8K
8K
B0F3
B0F2
B0F1
B0F0
STR710FZ1xx
STR711FR1xx
STR712FR1xx
0x4000
0x4000
0x4000
0x4000
0x4000
8000
6000
4000
2000
0000
STR710F72xx
STR711FR2xx
STR712FR2xx
Table 8. RAM Memory Mapping
Part Number
STR715FR0xx
RAM Size
Start Address
End Address
STR711FR0xx
16 Kbytes
0x2000 0000
0x2000 3FFF
32 Kbytes
0x2000 0000
0x2000 7FFF
64 Kbytes
0x2000 0000
0x2000 FFFF
STR712FR0xx
STR710FZ1xx
STR711FR1xx
STR712FR1xx
STR710F72xx
STR711FR2xx
STR712FR2xx
28/49
STR71xF - INTRODUCTION
Figure 8. External Memory Map
Addressable Memory Space
4 Gbytes
0xFFFF FFFF
EIC
0xFFFF F800
7
0xE000 0000
APB2
6
0xC000 0000
APB1
External Memory Space
64 MBytes
5
0xA000 0000
0x6C00
0x6C00
0x6C00
0x6C00
PRCCU
000C
0008
0004
0000
BCON3
BCON2
BCON1
BCON0
register
register
register
register
4
0x66FF FFFF
0x8000 0000
Reserved
Bank3
16M
Bank2
16M
Bank1
16M
Bank0
16M
CSn.3
0x6600 0000
3
0x64FF FFFF
0x6000 0000
EXTMEM
CSn.2
0x6400 0000
2
0x4000 0000
0x62FF FFFF
CSn.1
FLASH
0x6200 0000
0x60FF FFFF
1
CSn.0
0x2000 0000
RAM
0x6000 0000
0
0x0000 0000
FLASH/RAM/EMI
Reserved
Drawing not in scale
29/49
STR71xF - ELECTRICAL CHARACTERISTICS
2 ELECTRICAL CHARACTERISTICS
2.1 Absolute Maximum Ratings
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take normal precautions to avoid application of any
voltage higher than the specified maximum rated voltages.
For proper operation, it is recommended that VIN and VO be higher than VSS and lower than
V33. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage
level (V33 or VSS).
Table 9. Absolute Maximum Ratings.
Symbol
V33
V33IO-PLL
V18
Parameter
Value
Unit
Min
Max
Voltage on V33 with respect to ground (VSS)
-0.3
+4.0
V
Voltage on V33IO-PLL with respect to ground (VSS)
-0.3
+4.0
V
Voltage on V18 with respect to ground (VSS)
-0.3
+2.0
V
Voltage on V18BKP with respect to ground (VSS)
-0.3
+2.0
V
AVDD
Voltage on AVDD pin with respect to ground (VSS)
-0.3
+4.0
V
AVSS
Voltage on AVSS with respect to ground (VSS)
-0.1
V33 + 0.1
V
V18BKP
Voltage on true open drain pin (P0.10) with respect to ground (VSS)
-0.3
+5.5
Voltage on any other pin with respect to ground (VSS)
-0.3
+4.0
IOV
Input current on any pin during overload condition
-10
+10
mA
ITDV
Absolute sum of all input currents during overload condition
|200|
mA
TST
Storage Temperature
+150
°C
ESD
ESD Susceptibility (Human Body Model)
VIN
Note
30/49
–55
2000
V
V
Stresses exceeding above listed recommended “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. During
overload conditions (VIN>V33 or VIN<VSS) the voltage on pins with respect to ground
(VSS) must not exceed the recommended values.
STR71xF - ELECTRICAL CHARACTERISTICS
2.2 Operating Conditions
Symbol
Value
Parameter
Unit
Min
Max
Digital Supply Voltage for I/O circuitry
3.0
3.6
V
Digital Supply Voltage for I/O circuitry and for PLL reference
3.0
3.6
V
External Supply Voltage for Backup block (Voltage Regulator off)
1.4
1.8
V
Analog Supply Voltage for the A/D converter
V33
V33
V
TA
Ambient temperature under bias
–40
+85
°C
TJ
Junction temperature under bias
–40
+105
°C
V33
V33IO-PLL
V18BKP
AVDD
Note
RAM data retention is guaranteed with V33 not below 2.7 Volt, with the device in low
power mode (Stop or Wait for Interrupt).
2.3 LVD Electrical Characteristics
V33 = 3.3 ± 10%, TA = -40 / 85 °C unless otherwise specified.
Table 10. LVD Electrical Characteristics
Symbol
VIT
Parameter
LVD Threshold
Test Conditions
Main and LP LVDs
Value
Min
Typ
Max
1.3
1.45
Unit
V
31/49
STR71xF - ELECTRICAL CHARACTERISTICS
2.4 DC Electrical Characteristics
V33 = 3.3V ± 10%, TA = -40 / 85 °C unless otherwise specified.
Table 11. DC Electrical Characteristics
Symbol
VIH
VIL
VHYS
VOH
VOL
Parameter
Comment
Value
Min
Typ
Max
Unit
Input High Level CMOS
With or w/o hysteresis
0.7V33
V
Input High Level
P0.15 (WAKEUP) only
1.8
V
Input Low Level CMOS
With or w/o hysteresis
0.3V33
V
Input Low Level
P0.15 (WAKEUP) only
0.7
V
1.2
V
Input Hysteresis CMOS
Schmitt Trigger
0.4
0.8
0.3
0.5
Input Hysteresis
Schmitt Trigger
P0.15 (WAKEUP) only
Output High Level
High Current Pins
Push Pull, IOH= 8mA
V33 – 0.8
V
Output High Level
Standard Current Pins
Push Pull, IOH= 4mA
V33 – 0.8
V
Output Low Level
High Current Pins
Push Pull, IOL= 8mA
0.4
V
Output Low Level
Standard Current Pins
Push Pull, IOL= 4mA
0.4
V
V
RWPU
Weak Pull-Up Resistor
Measured at 0.5V33
100
kΩ
RWPD
Weak Pull-Down Resistor
Measured at 0.5V33
100
kΩ
32/49
STR71xF - ELECTRICAL CHARACTERISTICS
2.5 AC Electrical Characteristics
V33 = 3.3V ± 10%, TA = 27 °C unless otherwise specified.
Table 12. Power Consumption
Symbol
Parameter
IDDRUN
RUN Mode current
MCLK=50 MHz
IDDWFI
WFI Mode current
IDDLP
Value
Conditions
Min
Unit
Typ
Max
See
Table 13
100
mA
1 MHz System Clock
3
6
mA
LPWFI Mode current
32 kHz System Clock
200
IDDSTP
STOP Mode current
Main VReg off, Flash in Power-Down
100
IDDSB1
STANDBY Mode current
LP VReg and 32kHz Osc on
15
30
µA
IDDSB0
STANDBY Mode current
LP VReg, LVD, 32kHz Osc bypassed
3
10
µA
µA
µA
Note
IDDRUN is the power consumption in applications exploiting the full performances of
the core (running at the maximum frequency).
Note
IDDWFI is the power consumption with PLLs off, VReg and Flash on. This guarantees
the minimum interrupt response time.
Note
IDDLP is the power consumption with PLLs, Main VReg and Flash off.
Table 13. IDDRUN Typical Data measurements, TA=25°C
All Peripheral clocks enabled1)
Frequency
(Reset Configuration)
All Peripheral clocks disabled1)
RAM Execution
Flash Execution
RAM Execution
Flash Execution
MCLK=1 MHz
PCLK=1 MHz
15
15
11
11
MCLK=8 MHz
PCLK=8 MHz
19
20
15
17
MCLK=16 MHz
PCLK=8 MHz
23
27
19
23
MCLK=48 MHz
PCLK=6 MHz
43
53
40
50
MCLK=64 MHz
PCLK=8 MHz
53
N/A
48
N/A
Unit
mA
1)
Refer to APBn_CKDIS register description.
33/49
STR71xF - ELECTRICAL CHARACTERISTICS
V33 = 3.3V ± 10%, TA = -40 / 85 °C unless otherwise specified.
Table 14. AC Electrical Characteristics
Symbol
Parameter
Conditions
Value
Min
Typ
Executing from RAM or
external memory
fMCLK
fPCLK
fCK
CPU Frequency
Max
Unit
66
Executing from Flash
50
Executing from Flash with RWW
45
Burst Mode disabled (FLASHLP bit =1)
33
Peripheral Clock for APB
33
Clock input pin
16
MHz
2.6 nRSTIN Input Filter Characteristics
V33 = 3.3V ± 10%, TA = -40 / 85 °C unless otherwise specified.
Table 15. nRSTIN input Filter Characteristics
Symbol
Parameter
tFR
nRSTIN Input Filtered Pulse
tNFR
nRSTIN Input Not Filtered Pulse
34/49
Conditions
Value
Min
Typ
Max
500
1.2
Unit
ns
µs
STR71xF - ELECTRICAL CHARACTERISTICS
2.7 Oscillator Electrical Characteristics
V33 = 3.3 ± 10%, TA = -40 / 85 °C unless otherwise specified.
DEVICE
RTCXTO
RTCXTI
RTCXTI
DEVICE
RTCXTO
Figure 9. Crystal Oscillator and Resonator
RS
CL
CL
Table 16. Oscillator Electrical Characteristics
Symbol
Parameter
gm
Oscillator Transconductance
tSTUP
Oscillator Start-up Time
Test Conditions
Value
Min
Typ
Max
µA/V
8
Stable V33
Unit
2.5
s
2.8 PLL Electrical Characteristics
V33 = 3.3 ± 10%, V33IOPLL = 3.3 ± 10%, TA = -40 / 85 °C unless otherwise specified.
Table 17. PLL1 Electrical Characteristics
Symbol
fPLLCLK1
Parameter
PLL output clock
Test Conditions
fPLL1x 24
FREF_RANGE = 0
FREF_RANGE = 1
fPLL1
PLL input clock
MX[1:0]=’00’ or ‘01’
FREF_RANGE = 1
MX[1:0]=’10’ or ‘11’
PLL input clock duty cycle
Value
Min
Typ
Max
Unit
165
MHz
1.5
3.0
MHz
3.0
8.25
MHz
3.0
6
MHz
25
75
%
35/49
STR71xF - ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
Min
FREF_RANGE = 0
MX[1:0]=’01’ or ‘11’
FREF_RANGE = 0
fFREE1
PLL free running frequency
MX[1:0]=’00’ or ‘10’
FREF_RANGE = 1
MX[1:0]=’01’ or ‘11’
FREF_RANGE = 1
MX[1:0]=’00’ or ‘10’
Typ
Max
Unit
1
MHz
2
MHz
2
MHz
4
MHz
FREF_RANGE = 0
Stable Input Clock
tLOCK1
PLL lock time
300
µs
600
µs
2
ns
Stable V33IOPLL, V18
FREF_RANGE = 1
Stable Input Clock
Stable V33IOPLL, V18
∆tJITTER1 PLL jitter (peak to peak)
tPLL = 4 MHz, MX[1:0]=’11’
Global Output division = 32
(Output Clock = 2 MHz)
0.7
Table 18. PLL2 Electrical Characteristics
Symbol
fPLLCLK2
fPLL2
Parameter
PLL output clock
PLL input clock
Test Conditions
Value
Min
Typ
fPLL x 28
Max
Unit
140
MHz
FREF_RANGE = 0
1.5
3.0
MHz
FREF_RANGE = 1
3.0
5
MHz
300
µs
600
µs
2
ns
FREF_RANGE = 0
Stable Input Clock
tLOCK2
PLL lock time
Stable V33IOPLL, V18
FREF_RANGE = 1
Stable Input Clock
Stable V33IOPLL, V18
∆tJITTER2 PLL jitter (peak to peak)
36/49
tPLL = 4 MHz, MX[1:0]=’11’
Global Output division = 32
(Output Clock = 2 MHz)
0.7
STR71xF - ELECTRICAL CHARACTERISTICS
2.9 Flash Electrical characteristics
V33 = 3.3 ± 10%, TA = -40 / 85 °C unless otherwise specified.
Table 19. Flash Program/Erase Characteristics 1
Symbol
Parameter
Test Conditions
Value
Typ
Max(C0) Max(Cmax)
Unit
tPW
Word Program
40
µs
tPDW
Double Word Program
60
µs
tPB0
Bank 0 Program (256K)
Double Word Program
1.6
2.1
4.3
s
tPB1
Bank 1 Program (16K)
Double Word Program
130
170
300
ms
tES
Sector Erase (64K)
Not preprogrammed
Preprogrammed
2.3
1.9
4.0
3.3
4.9
4.1
s
tES
Sector Erase (8K)
Not preprogrammed
Preprogrammed
0.7
0.6
1.1
1.0
1.36
1.26
s
tES
Bank 0 Erase (256K)
Not preprogrammed
Preprogrammed
8.0
6.6
13.7
11.2
17.2
14.0
s
tES
Bank 1 Erase (16K)
Not preprogrammed
Preprogrammed
0.9
0.8
1.5
1.3
1.87
1.66
s
20
µs
tRPD
Recovery from Power-Down
tPSL
Program Suspend Latency
10
µs
tESL
Erase Suspend Latency
300
µs
Note
C0: TA = 85 °C after 0 cycles
Cmax: TA = 85 °C after max number of cycles
Table 20. Flash Program/Erase Characteristics 2
Symbol
tESR
Parameter
Conditions
Value
Min
Typ
Max
Unit
Endurance
10
kcycles
Endurance (Bank1 sectors)
100
kcycles
Data Retention
20
Years
20
ms
Erase Suspend Rate
Min time from Erase
Resume to next Erase
Suspend
37/49
STR71xF - ELECTRICAL CHARACTERISTICS
2.10 External Memory Bus Timing
V33 = 3.3 ± 10%, TA = -40 / 85 °C unless otherwise specified.
The tables below use a variable which is derived from the EMI_BCONn registers (described in
the STR71x Reference Manual) and represents the special characteristics of the programmed
memory cycle.
Symbol
tMCLK
tC
Parameter
Value
CPU clock period
1 / fMCLK
Memory cycle time wait states
tMCLK x (1 + [C_LENGTH])
Table 21. EMI Read Operation
Symbol
tRCR
Parameter
Test Conditions
Value
Min
Read to CSn Removal Time
tRP
Read Pulse Time
Typ
Max
Unit
tMCLK
ns
tC
ns
tRDS
Read Data Setup Time
3
ns
tRDH
Read Data Hold Time
3
ns
tRAS
Read Address Setup Time
1.3*tMCLK
ns
tRAH
Read Address Hold Time
3
ns
tRAT
Read Address Turnaround Time
3
ns
tRRT
RDn Turnaround Time
tMCLK
ns
See Figure 10, Figure 11, Figure 12and Figure 13 for related timing diagrams.
Table 22. EMI Write Operation
Symbol
Parameter
Value
Min
Typ
Max
Unit
tMCLK
ns
tWP
Write Pulse Time
tC
ns
tWCR
WEn to CSn Removal Time
Test Conditions
tWDS
Write Data Setup Time
3
ns
tWDH
Write Data Hold Time
3
ns
tWAS
Write Address Setup Time
1.3*tMCLK
ns
tWAH
Write Address Hold Time
3
ns
tWAT
Write Address Turnaround Time
3
ns
tWWT
WEn Turnaround Time
tMCLK
ns
See Figure 14, Figure 15, Figure 16 and Figure 17 for related timing diagrams.
38/49
STR71xF - ELECTRICAL CHARACTERISTICS
Figure 10. Read Cycle Timing: 16-bit READ on 16-bit Memory
tRAH
A[23:0]
Address
tRP
RDn
tRCR
CSn.x
WEn.x
tRDS
tRDH
tRAS
Data Input
D[15:0]
(Input)
Figure 11. Read Cycle Timing: 32-bit READ on 16-bit Memory
tRAT
tRAH
A[23:0]
tRAH
Address
Address
tRP
tRRT
tRP
RDn
tRCR
CSn.x
WEn.x
tRAS
D[15:0]
tRDS
Data Input
tRDH
tRDS
tRDH
Data Input
(Input)
See Table 21 for read timing data.
39/49
STR71xF - ELECTRICAL CHARACTERISTICS
Figure 12. Read Cycle Timing: 16-bit READ on 8-bit Memory
tRAT
tRAH
A[23:0]
tRAH
Address
Address
tRP
tRRT
tRP
RDn
tRCR
CSn.x
WEn.x
tRAS
tRDS
tRDH
tRDS
Data Input
Data Input
D[7:0]
tRDH
(Input)
Figure 13. Read Cycle Timing: 32-bit READ on 8-bit Memory
tRAT
A[23:0]
tRAH
tRAH
Address
Address
tRP
tRAT
tRAT
tRAH
tRRT
tRAH
Address
Address
tRP
tRRT
tRRT
tRP
tRP
RDn
tRCR
CSn.x
WEn.x
tRAS
D[7:0]
tRDS
tRDH
Data Input
(Input)
See Table 21 for read timing data.
40/49
tRDS
Data Input
tRDH
tRDS
Data Input
tRDH
tRDS
Data Input
tRDH
STR71xF - ELECTRICAL CHARACTERISTICS
Figure 14. Write Cycle Timing: 16-bit WRITE on 16-bit Memory
tWAH
A[23:0]
Address
RDn
tWCR
CSn.x
tWAS
tWP
WEn.x
tWDH
tWDS
Data Output
D[15:0]
(Output)
Figure 15. Write Cycle Timing: 32-bit WRITE on 16-bit Memory
tWAT
tWAH
A[23:0]
tWAH
address
address
RDn
tWCR
CSn.x
tWP
tWWT
tWP
WEn.x
tWAS
D[15:0]
tWDS
Data Output
tWDH
tWDS
tWDH
Data Output
(Output)
See Table 22 for write timing data.
41/49
STR71xF - ELECTRICAL CHARACTERISTICS
Figure 16. Write Cycle Timing: 16-bit WRITE on 8-bit Memory
tWAT
tWAH
A[23:0]
tWAH
address
address
RDn
tWCR
CSn.x
tWP
tWWT
tWP
WEn.x
tWAS
tWDS
tWDH
tWDS
Data Output
D[7:0]
tWDH
Data Output
(Output)
Figure 17. Write Cycle Timing: 32-bit WRITE on 8-bit Memory
tWAT
tWAT
tWAH
A[23:0]
tWAT
tWAH
address
address
tWAH
tWAH
address
address
RDn
tWCR
CSn.x
tWP
tWWT
tWP
tWWT
tWP
tWWT
tWP
WEn.x
tWAS
D[7:0]
tWDS
tWDH
Data Output
(Output)
See Table 22 for write timing data.
42/49
tWDS
Data Output
tWDH
tWDS
Data Output
tWDH
tWDS
Data Output
tWDH
STR71xF - ELECTRICAL CHARACTERISTICS
2.11 ADC Electrical Characteristics
V33 = 3.3 ± 10%, AVDD = 3.3 ± 10%, TA = -40 / 85 °C unless otherwise specified.
Table 23. ADC Electrical Characteristics
Symbol
Parameter
RES
Resolution
∆VIN
Input Voltage Range
fMOD
Modulator Oversampling Frequency
IBW
Input Bandwidth
Nch
Number of Input Channels
PBR
Passband Ripple
SINAD
S/N and Distortion
THD
Test Conditions
Sinewave with ∆VIN amplitude
Input Impedance
Typ
fMOD = 2 MHz
CIN
Input Capacitance
IADC
Power Consumption
TA = 27 °C
ISTBY
Standby Power Consumption
TA = 27 °C
Max
12
0
Total Harmonic Distortion
ZIN
Value
Min
56
63
60
74
Unit
bits
2.5
V
2.1
MHz
fMOD/
4096
kHz
4
n
0.1
dB
dB
dB
1
MΩ
2.5
5
pF
3.0
mA
1
µA
43/49
STR71xF - PACKAGE CHARACTERISTICS
3 PACKAGE CHARACTERISTICS
3.1 Package Mechanical Data
Figure 18. 64-Pin Thin Quad Flat Package (10x10)
Dim.
D
A
D1
A2
b
E
e
c
L1
h
L
Typ
A
A1
E1
mm
Min
inches
Max
Min
Typ
Max
1.60
0.063
0.15 0.002
0.006
A1
0.05
A2
1.35
1.40
1.45 0.053 0.055 0.057
b
0.17
0.22
0.27 0.007 0.009 0.011
c
0.09
0.20 0.004
0.008
D
12.00
0.472
D1
10.00
0.394
E
12.00
0.472
E1
10.00
0.394
e
0.50
0.020
θ
0°
3.5°
L
0.45
0.60
L1
7°
0°
3.5°
7°
0.75 0.018 0.024 0.030
1.00
0.039
Number of Pins
N
64
Figure 19. 144-Pin Thin Quad Flat Package
Dim.
D
D3
A1
73
72
0.10mm
.004 in. b
Seating Plane
b
E3
E
E1
A
A2
37
36
c
L1
L
h
Min
Typ
0.05
0.15 0.002
0.006
A2
1.35
1.40
1.45 0.053
0.057
b
0.17
0.22
0.27 0.007
0.011
c
0.09
0.20 0.004
0.008
D
21.80 22.00 22.20 0.858 0.867 0.874
D1
19.80 20.00 20.20 0.780 0.787 0.795
17.50
0.699
E
21.80 22.00 22.20 0.858 0.867 0.874
E1
19.80 20.00 20.20 0.780 0.787 0.795
E3
17.50
0.699
0.50
K
0°
3.5°
L
0.45
0.60
L1
0.020
7°
0°
3.5°
N
7°
0.75 0.018 0.024 0.030
1.00
0.039
Number of Pins
44/49
Max
0.063
A1
e
e
inches
Max
1.60
D3
144
1
Typ
A
D1
108
109
mm
Min
144
STR71xF - PACKAGE CHARACTERISTICS
Figure 20. 64-Low Profile Fine Pitch Ball Grid Array Package
mm
Dim.
Min
A
1.210
A1
0.270
A2
Typ
inches
Max
Min
Typ
1.700 0.048
Max
0.067
0.011
1.120
0.044
b
0.450 0.500 0.550 0.018 0.020 0.022
D
7.750 8.000 8.150 0.305 0.315 0.321
D1
E
5.600
0.220
7.750 8.000 8.150 0.305 0.315 0.321
E1
5.600
0.220
e
0.720 0.800 0.880 0.028 0.031 0.035
f
1.050 1.200 1.350 0.041 0.047 0.053
ddd
0.120
0.005
Number of Pins
N
64
Figure 21. 144-Low Profile Fine Pitch Ball Grid Array Package
Dim.
mm
Min
A
1.21
A1
0.21
A2
Typ
inches
Max
Min
Typ
1.70 0.048
Max
0.067
0.008
1.12
0.35
D
9.85 10.00 10.15 0.388 0.394 0.400
D1
E
0.40
0.044
b
0.45 0.014 0.016 0.018
8.80
0.346
9.85 10.00 10.15 0.388 0.394 0.400
E1
8.80
0.346
e
0.80
0.031
F
0.60
0.024
ddd
0.10
0.004
eee
0.15
0.006
0.08
0.003
fff
Number of Pins
N
144
45/49
STR71xF - PACKAGE CHARACTERISTICS
3.2 Thermal Characteristics
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the
following equation:
TJ = TA + (PD x ΘJA)
(1)
Where:
– TA is the Ambient Temperature in °C,
– ΘJA is the Package Junction-to-Ambient Thermal Resistance, in °C/W,
– PD is the sum of PINT and PI/O (PD = PINT + PI/O),
– PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power.
– PI/O represents the Power Dissipation on Input and Output Pins;
Most of the time for the applications PI/O < PINT and may be neglected. On the other hand,
PI/O may be significant if the device is configured to drive continuously external modules and/
or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273°C)
(2)
Therefore (solving equations 1 and 2):
K = PD x (TA + 273°C) + ΘJA x PD2
(3)
where:
– K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may
be obtained by solving equations (1) and (2) iteratively for any value of TA.
Table 24. Thermal characteristics
Symbol
Parameter
Value
Unit
ΘJA
Thermal Resistance Junction-Ambient
TQFP 144 - 20 x 20 mm / 0.5 mm pitch
42
°C/W
ΘJA
Thermal Resistance Junction-Ambient
TQFP 64 - 10 x 10 mm / 0.5 mm pitch
45
°C/W
ΘJA
Thermal Resistance Junction-Ambient
LFBGA 64 - 8 x 8 x 1.7mm
TBD
ΘJA
Thermal Resistance Junction-Ambient
LFBGA 144 - 10 x 10 x 1.7mm
TBD
46/49
°C/W
°C/W
STR71xF - ORDER CODES
4 ORDER CODES
Table 25. Order Codes
Partnumber
STR710FZ1T6
STR710FZ2T6
STR710FZ1H6
STR710FZ2H6
FLASH RAM
Kbytes Kbytes
128+16
32
256+16
64
128+16
32
256+16
64
STR711FR0H6
64+16
16
STR711FR0T6
64+16
16
STR711FR1T6
128+16
32
STR711FR2T6
256+16
64
STR712FR0H6
64+16
16
STR712FR0T6
64+16
16
STR712FR1T6
128+16
32
STR712FR2T6
256+16
64
STR715FR0H6
64+16
16
STR715FR0T6
64+16
16
EMI
USB
CAN
I/O
Ports
Package
Yes
Yes
Yes
48
TQFP144 20 x 20
Yes
Yes
Yes
48
LFBGA 10 x 10 1.7
Temp.
Range
LFBGA64 8 x 8 1.7
Yes
No
30
TQFP64 10x10
-40 to
+85°C
LFBGA64 8 x 8 1.7
No
Yes
No
32
No
TQFP64 10 x10
LFBGA64 8 x 8 1.7
TQFP64 10 x 10
47/49
STR71xF - REVISION HISTORY
5 REVISION HISTORY
Table 26. Revision history
Date
Revision
Description of Changes
17-Mar-2004
1
First Release
05-Apr-2004
2
Updated “ELECTRICAL CHARACTERISTICS” on page 30
08-Apr-2004
2.1
Corrected STR712F Pinout. Pins 43/42 swapped.
15-Apr-2004
2.2
PDF hyperlinks corrected.
Corrected description of STDBY, V18, VSS18 V18BKP VSSBKP pins
7-Jul-2004
3
Added IDDrun typical data
Updated BSPI max. baudrate.
Updated “External Memory Bus Timing” on page 38
Corrected Flash sector B1F0/F1 address in Figure 6 on page 27
29-Oct-2004
4
Corrected Table 6 on page 21 TQFP64 TEST pin is 16 instead of 17.
Added to TQPFP64 column: pin 7 BOOTEN, pin 17 V33IO-PLL
Changed description of JTCK from ‘External pull-down required’ to ‘External pull-up or pull down required’.
Changed “Product Preview” to “Preliminary Data” on page 1 and 3
25-Jan-2005
5
Renamed ‘PU/PD’ column to ‘Reset state’ in Table 6 on page 21
Added reference to STR7 Flash Programming Reference Manual
Added STR715F devices and modified RAM size of STR71xF1 devices
19-Apr-2005
6
Added BGA package in Section 3
Updated ordering information in Section 4 .
Added PLL duty cycle min and max. in Section 2.8
48/49
STR71xF - REVISION HISTORY
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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49/49