STA8090FG
Fully Integrated GPS/Galileo/Glonass/BeiDou/QZSS Receiver
with embedded RF and in-package Flash
Data brief
• Power Management Unit (PMU) embedding
switching regulator
• Operating condition:
– Main voltage regulator (VINL): 1.6V to 4.3V
– Backup voltage (VINB): 1.6V to 4.3V
– Digital voltage (VDD): 1.2 V ± 10%
– RF core voltage (VCC): 1.2 V ± 10%
– IO Ring Voltage (VddIO): 1.8 V ± 5% or
3.3 V ± 10%
5'#("YYNN
("1($'5
Features
• Package:
– TFBGA99 (5 x 6 x 1.2 mm) 0.5 mm pitch
• Ambient temperature range: -40/+85°C
• STMicroelectronics® positioning receiver with
48 tracking channels and 2 fast acquisition
channels supporting GPS, Galileo, Glonass,
BeiDou and QZSS systems
• Single die standalone receiver embedding RF
Front-End and low noise amplifier
• -162 dBm indoor sensitivity (tracking mode)
• Fast TTFF < 1 s in Hot start and 30 s in Cold
Start
• High performance ARM946 MCU (up to
196 MHz)
• 256 Kbyte embedded SRAM
• In-Package SQI Flash Memory (16 Mbits)
Description
STA8090FG is a single die standalone positioning
receiver IC working on multiple constellations
(GPS/Galileo/Glonass/BeiDou/QZSS).
The minimal BOM makes STA8090FG the ideal
solution for cost competitive and small footprint
products such as trackers, telematics, portable,
tablets, marine and sports accessories.
The device is offered with a complete GNSS
firmware which performs all GNSS operations
including tracking, acquisition, navigation and
data output with no need of external memories.
• Real Time Clock (RTC) circuit
• 32-bit Watch-dog timer
• 3 UARTs
• 1 I2C master interface
• 1 Synchronous Serial Port (SSP, Motorola-SPI
supported)
• USB2.0 full speed (12 MHz) with integrated
physical layer transceiver
• 2 Controller Area Network (CAN)
• 2 channels ADC (10 bits)
December 2014
DocID025726 Rev 4
For further information contact your local STMicroelectronics sales office.
1/22
www.st.com
Contents
STA8090FG
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
2.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
TFBGA99 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
Communication interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Multimedia card pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8
General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9
RF Front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
TFBGA99 5 x 6 x 1.2 mm package information . . . . . . . . . . . . . . . . . . . . 17
4
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/22
DocID025726 Rev 4
STA8090FG
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
TFBGA99 connection diagram (with CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA99 connection diagram (no CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Communication interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Multimedia card pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RF Front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TFBGA99 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DocID025726 Rev 4
3/22
3
List of figures
STA8090FG
List of figures
Figure 1.
Figure 2.
Figure 3.
4/22
STA8090FG system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA99 5 x 6 x 1.2 mm package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DocID025726 Rev 4
STA8090FG
1
Overview
Overview
STA8090FG is a highly integrated single-chip standalone GNSS receiver designed for
positioning system applications.
STA8090FG embeds the new ST GNSS positioning engine capable of receiving signals
from multiple satellite navigation systems, including the US GPS, European Galileo,
Russia's Glonass, Chinese BeiDou and Japan's QZSS.
The STA8090FG ability of tracking simultaneously the signals from multiple satellites
regardless of their constellation, make this chip capable of delivering exceptional accuracy
in urban canyons and in the environments where buildings and other obstructions make
satellite visibility challenging.
STA8090FG embeds innovative power management with switching regulator for power
consumption optimization.
The extended voltage supply range from 1.6 V to 4.3 V, the 1.8 V and 3.3 V I/O compliance
support make the STA8090FG the suitable solution for different user applications.
The STA8090FG combines a high performance ARM946 microprocessor with I/O
capabilities and enhanced peripherals. It supports USB2.0 standard at full speed (12 Mbps)
with on-chip PHY.
The chip embeds backup logic with real time clock.
The device is offered with a complete firmware performing all positioning operations
including acquisition, tracking, navigation and data output with no need of external
memories.
The STA8090FG, using STMicroelectronics CMOSRF Technology, is housed in a
TFBGA99 (5 x 6 x 1.2 mm) package with stacked 16 Mbit Flash memory.
DocID025726 Rev 4
5/22
21
Pin description
STA8090FG
2
Pin description
2.1
Block diagram
Figure 1. STA8090FG system block diagram
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6/22
DocID025726 Rev 4
STA8090FG
2.2
Pin description
TFBGA99 pin configuration
Table 1. TFBGA99 connection diagram (with CAN)
1
2
3
4
5
6
7
8
9
A
VINM
VINM
SPI_CLK
SPI_CSN
VINL1
VOL1
GND
VINB
VOB
B
VLX
VLX
SPI_DI
UART0_
TX
UART0_
CTS
UART2_
RX
GPIO1
GPIO0
GND
C
GND
GND
SPI_DO
VDDIO_
R1
UART2_
TX
UART0_
RTS
VDD_SQI
VDD_
ADC
Reserved
D
VOM
GND
TMS
UART0_
DSR
UART0_
DTR
GND
ADC_IN2
GND
RTC_XT
O
E
VDD_ANA
TDO
TRSTn
UART0_
DCD
VDDD
UART0_
RX
ADC_IN1
F
GND
TDI
VDDD
VDDD
GND
GND
WAKEUP1
STDBYn
RSTn
G
USB_DP
TCK
VDDD
GND
GND
GND
STDBY_
OUT
PMU_
CFG
XTAL_
OUT
H
USB_DM
GPIO10
MMC_D3
MMC_
CLK
TP_IF_N
GND
GND
VCC_PLL
XTAL_IN
J
CAN0_TX
GPIO11
MMC_D2
MMC_
CMD
TP_IF_P
GND
GND
ANT_
SENSE2
VCC_
CHAIN
K
CAN0_RX
VDDIO_
R2
GPIO2
MMC_D1 GND_LNA GND_LNA GND_LNA
GND
ANT_
SENSE1
L
GND
I2C_SD
I2C_CLK
MMC_D0
VINL2
GND
VCC_RF
DocID025726 Rev 4
LNA_IN
VOL2
WAKEUP0 RTC_XTI
7/22
21
Pin description
STA8090FG
Table 2. TFBGA99 connection diagram (no CAN)
1
2
3
4
5
6
7
8
9
A
VINM
VINM
SPI_CLK
SPI_CSN
VINL1
VOL1
GND
VINB
VOB
B
VLX
VLX
SPI_DI
UART0_
TX
UART0_
CTS
UART2_
RX
GPIO1
GPIO0
GND
C
GND
GND
SPI_DO
VDDIO_
R1
UART2_
TX
UART0_
RTS
VDD_SQI
VDD_
ADC
Reserved
D
VOM
GND
TMS
UART0_
DSR
UART0_
DTR
GND
ADC_IN2
GND
RTC_XTO
E
VDD_ANA
TDO
TRSTn
UART0_
DCD
VDDD
UART0_
RX
ADC_IN1
F
GND
TDI
VDDD
VDDD
GND
GND
WAKEUP1
STDBYn
RSTn
G
USB_DP
TCK
VDDD
GND
GND
GND
STDBY_
OUT
PMU_
CFG
XTAL_
OUT
H
USB_DM
GPIO10
MMC_D3
MMC_
CLK
TP_IF_N
GND
GND
VCC_PLL
XTAL_IN
J
UART0_
TX
GPIO11
MMC_D2
MMC_
CMD
TP_IF_P
GND
GND
ANT_
SENSE2
VCC_
CHAIN
K
UART0_
RX
VDDIO_
R2
GPIO2
MMC_D1 GND_LNA GND_LNA GND_LNA
GND
ANT_
SENSE1
L
GND
I2C_SD
I2C_CLK
MMC_D0
VINL2
GND
2.3
VCC_RF
LNA_IN
VOL2
WAKEUP0 RTC_XTI
Power supply pins
Table 3. Power supply pins
Symbol
I/O voltage
I/O
VCC_CHAIN
1.2 V
PWR
Analog supply voltage for RF chain (1.2V)
J9
VCC_PLL
1.2 V
PWR
Analog supply voltage for PLL RF (1.2V)
H8
VCC_RF
1.2 V
PWR
Analog supply voltage for RF (1.2V)
L5
VDD_ADC
1.8 V
PWR
Digital supply voltage for ADC (1.8V)
C8
VDD_SQI
1.8 V
PWR
Digital supply voltage for SQI
C7
VDDD
1.1 V
PWR
Digital supply voltage. This value can be configured to
1.0 V, 1.1 V (default) or 1.2 V
VDDIO_R1
1.8 V or 3.3 V
PWR
Digital supply voltage for I/O ring 1 (1.8 V or 3.3 V)
C4
VDDIO_R2
3.3V
PWR
Digital supply voltage for I/O ring 2 (3.3 V)
K2
VINB
1.6 V - 4.3 V
PWR
Backup LDO input supply voltage (1.6 V to 4.3 V)
A8
VINL1
1.6 V - 4.3 V
PWR
LDO1 input supply voltage (1.6 V to 4.3 V)
A5
8/22
Description
DocID025726 Rev 4
STA8090FG
E5, F3, F4, G3
STA8090FG
Pin description
Table 3. Power supply pins (continued)
Symbol
I/O voltage
I/O
VINL2
1.6 V - 4.3 V
PWR
LDO2 input supply voltage (1.6 V to 4.3 V)
VINM
1.6 V - 4.3 V
PWR
SMPS coil input supply (1.6 V to 4.3 V)
VDD_ANA
1.6 V - 4.3 V
PWR
SMPS input supply (1.6 V to 4.3 V)
VLX
0 V - 4.3 V
PWR
SMPS coil output
VOB
1.0V
PWR
LDO backup output voltage (1.0 V)
A9
A6
Description
STA8090FG
L8
A1, A2
E1
B1, B2
VOL1
1.1 V or 1.8 V
PWR
LDO1 output voltage:
PMU_CFG = high -> 1.1 V (it can be also configured to
1.0 V or 1.2 V)
PMU_CFG = low -> 1.8 V
VOL2
1.2 V
PWR
LDO2 output voltage (1.2 V)
L7
PWR
SMPS output voltage
PMU_CFG = high -> 1.8 V
PMU_CFG = low -> 1.1 V (it can be also configured to
1.0 V or 1.2 V)
D1
VOM
1.1 V or 1.8 V
GND
GND
GND
Ground
A7, B9, C1,
C2, D2, D6,
D8, F1, F5, F6,
G4, G5, G6,
H6, H7, J6, J7,
K8, L1, L9
GND_LNA
GND
GND
Ground
K5, K6, K7
2.4
Main function pins
Table 4. Main function pins
Symbol
I/O voltage
I/O
ADC_IN1
1.4 V – 0 V typ
range
I
ADC Analog input [1]
E7
ADC_IN2
1.4 V – 0 V typ
range
I
ADC Analog input [2]
D7
PMU_CFG
1.0 V
I
Power management unit config pin
High -> VOL1 = 1.1 V, VOM = 1.8 V
Low -> VOL1 = 1.8 V, VOM = 1.1 V
G8
RSTn
1.0 V
I
Reset Input with Schmitt-Trigger characteristics and noise
filter.
F9
RTC_XTI
1.0 V (max)
I
Input of the 32 KHz oscillator amplifier circuit and input of
the internal real time clock circuit.
E9
RTC_XTO
1.0 V (max)
O
Output of the oscillator amplifier circuit.
D9
STDBY_OUT
1.0 V
O
When low, indicates the chip is in Standby mode
G7
Description
DocID025726 Rev 4
STA8090FG
9/22
21
Pin description
STA8090FG
Table 4. Main function pins (continued)
Symbol
I/O voltage
I/O
Description
STA8090FG
STDBYn
1.0 V
I
When low, the chip is forced in Standby Mode - All pins in
high impedance except the ones powered by Backup
supply
F8
WAKEUP0
1.0 V
I
WAKEUP from STANDBY mode
E8
WAKEUP1
1.0 V
I
WAKEUP from STANDBY mode
F7
2.5
Test/emulated dedicated pins
Table 5. Test/emulated dedicated pins
Symbol
I/O voltage
I/O
TCK
VDDIO_R2
I
JTAG Test Clock
G2
TDI
VDDIO_R2
I
JTAG Test Data In
F2
TDO
VDDIO_R2
O
JTAG Test Data Out
E2
TMS
VDDIO_R2
I
JTAG Test Mode Select
D3
TRSTn(1)
VDDIO_R2
I
JTAG Test Circuit Reset
E3
TP_IF_N
1.2 V
O
Diff.Test Point for IF – Neg.
H5
TP_IF_P
1.2 V
O
Diff.Test Point for IF . Pos.
J5
Description
STA8090FG
1. If JTAG interface is not used, pin TRSTn must be asserted low.
2.6
Communication interface pins
Table 6. Communication interface pins
Symbol
CAN0_RX(1)
CAN0_TX(1)
10/22
I/O
voltage
I/O
Alternative
function
Function
I
AF0
(default)
CAN0_RX(1)
CAN0 receive data input
I
AF1
UART0_RX
UART0 Rx data
I/O
AF2
Tsense
External temperature capture
port
I/O
AF3
I2C_SD
I2C serial data
O
AF0
(default)
CAN0_TX(1)
CAN0 transmit data output
O
AF1
UART0_TX
UART0 Tx data
I/O
AF2
GPIO7
O
AF3
I2C_CLK
Description
K1
VDDIO_R2
VDDIO_R2
STA8090FG
General purpose I/O #7
I2C clock
DocID025726 Rev 4
J1
STA8090FG
Pin description
Table 6. Communication interface pins (continued)
Symbol
I2C_CLK
I2C_SD
SPI_CLK
SPI_CSN
SPI_DI
SPI_DO
I/O
voltage
VDDIO_R2
VDDIO_R2
VDDIO_R1
VDDIO_R1
VDDIO_R1
VDDIO_R1
UART0_CTS VDDIO_R1
I/O
Alternative
function
Function
O
AF0
(default)
I2C_CLK
I/O
AF1
GPIO8
Description
I2C clock
General purpose I/O #8
(1)
O
AF2
CAN1_TX
O
AF3
SPI_CLK
I/O
AF0
(default)
I2C_SD
I/O
AF1
GPIO9
STA8090FG
L3
CAN1 transmit data output
SPI clock
I2C serial data
General purpose I/O #9
(1)
CAN1_RX
L2
CAN1 receive data input
I
AF2
I/O
AF3
SPI_CSN
SPI chip select active low
O
AF0
(default)
SPI_CLK
SPI clock
I/O
AF1
GPIO25
General purpose I/O #25
O
AF2
SQI_CLK
O
AF3
MMC_CLK
O
AF0
(default)
SPI_CSN
I/O
AF1
GPIO24
I/O
AF2
SQI_CEN
I/O
AF3
MMC_CMD
I
AF0
(default)
SPI_DI
SPI serial data input/ BOOT2
I/O
AF1
TSENSE
External temperature capture
port
I/O
AF2
I/O
AF3
MMC_D0
Multimedia card data 0
O
AF0
(default)
SPI_DO
SPI serial data output
I/O
AF1
GPIO27
General purpose I/O #27
I/O
AF2
SQI_SIO0/SI
I/O
AF3
MMC_D1
I
AF0
(default)
UART0_CTS
I/O
AF1
GPIO15
General purpose I/O #15
O
AF2
i2s_out_sclk
MSP serial clock output
O
AF3
Clock GNSS
GNSS clock out
A3
SQI Flash clock
Multimedia Clock line
SPI chip select active low /
IO_Power Sel Ring 1
General purpose I/O #24
A4
SQI Flash chip enable
Multimedia card command line
B3
SQI_SIO1/SO SQI Flash data IO 1 / ser. Output
C3
SQI Flash data IO 0 / ser. Input
Multimedia card data 1
UART0 clear to send
DocID025726 Rev 4
B5
11/22
21
Pin description
STA8090FG
Table 6. Communication interface pins (continued)
Symbol
I/O
voltage
UART0_DCD VDDIO_R1
I/O
Alternative
function
Function
I
AF0
(default)
UART0_DCD
UART0 data carrier detect
I/O
AF1
GPIO17
General purpose I/O #17
O
AF2
i2s_out_sdata
MSP serial data output
O
AF3
Clock GNSS
GNSS clock out
I
AF0
(default)
UART0_DSR
UART0 data set ready
I/O
AF1
GPIO16
O
AF2
i2s_out_lrclk
MSP left/right clock output
O
AF3
Sign GC
Glonass and BeiDou 3-bit
coding output (Sign)
O
AF0
(default)
UART0_DTR
UART0 data terminal read
I/O
AF1
GPIO18
General purpose I/O #18
I
AF2
Timer_ICAPA
O
AF3
Mag_1 GG
O
AF0
(default)
UART0_RTS
UART0 request to send
I/O
AF1
GPIO14
General purpose I/O #14
O
AF2
TCXO_OUT
O
AF3
Sign GG
I
AF0
(default)
UART0_RX
O
AF1
SPI_DO
I/O
AF2
SQI_SIO2
I
AF3
Timer_ICAPA
O
AF0
(default)
UART0_TX
I
AF1
SPI_DI
SPI serial data input
I/O
AF2
SQI_SIO3
SQI Flash data IO 3
O
AF3
Timer_OCMPA
Description
D4
UART0_DTR VDDIO_R1
Extended function timer - input
capture A
12/22
D5
GPS and Galileo 3-bit coding
Output (MAG1)
UART0_RTS VDDIO_R1
UART0_TX
E4
General purpose I/O #16
UART0_DSR VDDIO_R1
UART0_RX
STA8090FG
C6
TCXO out clock
GPS and Galileo 3-bit coding
output (Sign)
UART0 Rx data
SPI serial data output
E6
VDDIO_R1
SQI Flash data IO 2
Extended Function Timer - Input
Capture A
UART0 Tx data / BOOT1
B4
VDDIO_R1
Extended Function Timer –
Output Compare A
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STA8090FG
Pin description
Table 6. Communication interface pins (continued)
Symbol
UART2_RX
UART2_TX
USB_DM
USB_DP
I/O
voltage
VDDIO_R1
VDDIO_R1
I/O
Alternative
function
Function
I
AF0
(default)
UART2_RX
I/O
AF1
GPIO28
General purpose I/O #28
I/O
AF2
I2C_SD
I2C serial data
I/O
AF3
MMC_D2
O
AF0
(default)
UART2_TX
UART 2 Tx data / BOOT0
I/O
AF1
GPIO29
General purpose I/O #29
O
AF2
I2C_CLK
I2C clock
I/O
AF3
MMC_D3
Multimedia card data 2
USB
AF0
USB_DM
USB D- signal
I
AF1
(default)
UART1_RX
VDDIO_R2
Description
UART 2 Rx data
B6
Multimedia card data 2
C5
UART 1 Rx data
H1
(1)
CAN1 receive data input
I
AF2
CAN1_RX
I/O
AF3
I2C_SD
I2C serial data
USB
AF0
USB_DP
USB D+ signal
O
AF1
(default)
UART1_TX
VDDIO_R2
STA8090FG
UART 1 Tx data
G1
(1)
O
AF2
CAN1_TX
O
AF3
I2C_CLK
CAN1 transmit data output
I2C clock
1. Only for STA8090FGB.
2.7
Multimedia card pins
Table 7. Multimedia card pins
Symbol
MMC_CLK
I/O voltage
I/O
Alternative
function
Function
O
AF0
(default)
MMC_CLK
O
AF1
i2s_out_lrclk
MSP left/right clock output
Extended Function Timer Input Capture A
Description
STA8090FG
Multimedia Clock line
VDDIO_R2
H4
I
AF2
Timer_ICAPA
I/O
AF3
GPIO4
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Pin description
STA8090FG
Table 7. Multimedia card pins (continued)
Symbol
MMC_CMD(1)
MMC_D0
MMC_D1
MMC_D2
MMC_D3
I/O voltage
VDDIO_R2
VDDIO_R2
I/O
Alternative
function
Function
Description
I/O
AF0
(default)
MMC_CMD
Multimedia card command line
O
AF1
i2s_out_sdata
(2)
MSP serial data output
O
AF2
CAN0_TX
I/O
AF3
GPIO5
General purpose I/O #5
I/O
AF0
(default)
MMC_D0
Multimedia card data 0
O
AF1
i2s_out_sclk
MSP serial clock output
I/O
AF2
I2C_SD
I2C serial data
I/O
AF3
GPIO20
General purpose I/O #20
I/O
AF0
(default)
MMC_D1
I
AF1
i2s_in_sdata
O
AF2
Sign GC
Glonass and BeiDou 3-bit
coding output (Sign)
I/O
AF3
GPIO21
General purpose I/O #21
I/O
AF0
(default)
MMC_D2
Multimedia card data 2
I/O
AF1
Reserved
Reserved
L4
Multimedia card data 1
MSP serial data input
K4
VDDIO_R2
(2)
J3
CAN0 receive data input
I
AF2
CAN0_RX
I/O
AF3
Tsense
I/O
AF0
(default)
MMC_D3
Multimedia card data 2
I/O
AF1
Reserved
Reserved
O
AF2
Sign GG
GPS 3-bit coding output (Sign)
I/O
AF3
GPIO23
General purpose I/O #23
External temperature capture
port
1. A pull down must be present to enable ARM Real Time Debugging via JTAG.
2. Only for STA8090FGB.
14/22
J4
CAN0 transmit data output
VDDIO_R2
VDDIO_R2
STA8090FG
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H3
STA8090FG
2.8
Pin description
General purpose pins
Table 8. General purpose pins
Symbol
GPIO0
GPIO1
GPIO2
GPIO10
GPIO11
I/O
voltage
VDDIO_R1
I/O
Alternative
function
Function
I/O
AF0 (default)
GPIO0
General purpose I/O #0
I
AF1
PPS_IN
pulse per second input
O
AF2
Timer_OCMPB
O
AF3
Mag_0 GC
Glonass and BeiDou 3-bit coding
Output (MAG0)
I/O
AF0 (default)
GPIO1
General purpose I/O #1/ BOOT3
I
AF1
i2s_in_sdata
O
AF2
PPS_OUT
I/O
AF3
TSENSE
External temperature capture port
I/O
AF0 (default)
GPIO2
General purpose I/O #2
I/O
AF1
Reserved
I
AF2
Timer_ICAPB
Extended Function Timer - Input
Capture B
O
AF3
Mag_1 GC
Glonass and Beidou 3bit coding
Output (MAG1)
I/O
AF0
(default),
AF1
GPIO10
I
AF2
Timer_ICAPA
O
AF3
Timer_OCMPB
I/O
AF0
(default),
AF1
GPIO11
O
AF2
Timer_OCMPA
Extended Function Timer – Output
Compare A
I
AF3
Timer_ICAPB
Extended Function Timer – Input
Capture B
Description
Extended Function Timer – Output
Compare B
VDDIO_R2
VDDIO_R2
B8
MSP serial data input
VDDIO_R1
VDDIO_R2
STA8090FG
B7
pulse per second output
Reserved
K3
General purpose I/O #10
Extended Function Timer – Input
Capture A
H2
Extended Function Timer – Output
Compare B
General purpose I/O #11
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Pin description
2.9
STA8090FG
RF Front-end pins
Table 9. RF Front-end pins
Symbol
I/O voltage
I/O
ANT_SENSE1
3.3 V
I
Antenna sensing input 1
K9
ANT_SENSE2
3.3 V
I
Antenna sensing input 2
J8
LNA_IN
1.2 V
I
Low Noise Amplifier Input
L6
XTAL_IN
1.2 V
I
Input Side of Crystal Oscillator or TCXO Input
H9
XTAL_OUT
1.2 V
O
Output Side of Crystal Oscillator
G9
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Description
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STA8090FG
STA8090FG
Package and packing information
3
Package and packing information
3.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
3.2
TFBGA99 5 x 6 x 1.2 mm package information
Table 10. TFBGA99 package dimensions
Symbol
Min.
Typ.
A
A1
Max
1.20
0.15
A2
0.28
A4
0.60
b
0.25
0.30
0.35
D
5.85
6.00
6.15
D1
E
5.00
4.85
5.00
E1
4.00
e
0.50
F
0.50
5.15
ddd
0.08
eee
0.15
fff
0.05
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Package and packing information
STA8090FG
Figure 2. TFBGA99 5 x 6 x 1.2 mm package dimension
("1($'5
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STA8090FG
4
Ordering information
Ordering information
Figure 3. Ordering information scheme
Example code:
STA8090FG
Family identifier
B
Qualified Grade/CAN Bus
TR
Packing
TR = Tape and Reel
<blank> = Tray
B = Industrial Grade (with CAN)
<blank> = Industrial Grade (no CAN)
SAL with Stacked Flash
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Revision history
5
STA8090FG
Revision history
Table 11. Document revision history
Date
Revision
18-Dec-2013
1
Initial release.
2
Updated Features list
Added following chapters:
– Chapter 1: Overview
– Chapter 2: Pin description
– Chapter 3: Package and packing information
– Chapter 4: Ordering information
3
Table 5: Test/emulated dedicated pins:
– TRSTn: added note
Table 7: Multimedia card pins:
– MMC_CMD: added note
4
Updated Features list
Table 1: TFBGA99 connection diagram (with CAN):
– K5, K6, K7, K8: updated pin name
Table 2: TFBGA99 connection diagram (no CAN):
– K5, K6, K7, K8: updated pin name
Table 3: Power supply pins:
– GND, GND_LNA: updated pin number
Table 4: Main function pins:
– ADC_IN2: updated description
– RTC_XTI, RTC_XTO: updated I/O voltage
Table 5: Test/emulated dedicated pins:
– TDI, TMS: updated description
Table 6: Communication interface pins:
– CAN0_RX: added note on CAN0_RX function; updated I/O type
for TSENSE function
– CAN0_TX: added note on CAN0_TX function
– I2C_CLK, I2C_SD: changed AF3 function
– SPI_CSN: updated I/O type for SQI_CEN function
– SPI_DI: updated AF0 description; changed AF1 function
– SPI_DO: updated description
– UART0_CTS, UART0_DCD, UART0_DSR: changed AF2
function
– UART0_TX, UART0_RX: changed AF1 I/O type and function
09-Apr-2014
10-Apr-2014
04-Dec-2014
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STA8090FG
Revision history
Table 11. Document revision history
Date
04-Dec-2014
Revision
Changes
4
(continued)
Table 7: Multimedia card pins:
– MMC_CLK, MMC_CMD, MMC_D0, MMC_D1: updated AF1
function
– MMC_D2: changed AF1 I/O type and function; updated TSENSE
I/O type;
– MMC_D3: changed AF1 I/O type and function
Table 8: General purpose pins:
– GPIO1: updated AF0 description; updated AF1 function;
updated TSENSE I/O type
– GPIO2: updated AF1 function
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STA8090FG
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