TECHNICAL DATA EIB-TP-UART-IC Features • Signaling for standard UART (LSB-First, Idle is 1) VB - 11 10 VB + Tx0 12 9 VSP Rx IN 13 8 CSA MODE 0 14 7 VCC MODE 1 15 6 DIV TEST MODE 16 5 • Direct coupling to host controller (TxD, RxD), or via optical couplers (optional) SAVE X1 17 4 TSTIN • 2 - wire protocol with software handshake X2 18 3 VIF TSTOUT 19 2 RESn RxD 20 1 TxD • Baud rate 9600 or 19200 baud for the communication: TP - UART <--> Host - Controller • Buffering of send frames • No critical timing during transmission • 64 Byte telegram buffer • Operating temperature range: -25°C to 85°C • Supervision of EIB bus voltage GENERAL DESCRIPTION The TP - UART - IC (Twisted Pair - Universal Asynchronous Receive Transmit - IC) is a transceiver which supports the connection of microcontrollers of sensors, actuators, or other applications to the EIB (European - Installation - Bus). This module supports every transmit- and receive - function and also the high ohmic decoupling of energy from bus line. It generates further a stabilized 3.3V or 5V supply to use by a host controller. Up to 256 subscribers can be connected to one bus line. An UART interface is realized for communication with a host controller. The coupling can be realized directly or via optical couplers. The TP - UART - IC consists of two main parts: the digital part (UART - Interface) and the analog part ( analog circuit part). The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 1 TP-UART-IC GENERAL DRAWING A - Bus + Power Supply 230V / 50Hz 30V B - Bus - TP-UARTIC Optional Electrical Isolation RxD TP-UARTIC TxD RxD TP-UARTIC TxD RxD TxD (Optocoupler) Application Application ... Application Optional Power Supply Bus Device 1 Bus Device 2 Bus Device n STRUCTURE of TP - UART - IC (Block Diagram:) Host-Controller RxD TxD UART-Receiver UART-Transmitter Digital - Part 64 Byte TelegramSendbuffer State-Byte Controll-Logic 1 Bytebuffer (receive) ACK-Flags Filter EIB-Transmit RxD3 TSTIN_BDS (Baud rate) TSTout Mode 0 Mode 1 EIB-Receiver EIB-Transmitter RESn 4,9152 MHz 0,05 % EIB-ReceiveTxD3 Analog - Part Transmit Receive Power Supply 5 V Regulator EIB The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 2 TP-UART-IC 1 The ANALOG - PART 1.1 General Device Specification 1.1.1 Absolute Maximum Ratings All voltages are referring to VB-. Currents are declared positive in case of flowing into pin. Symbol VB+ VCC VIF VVSP VTxO VRxIN VLV1 VLV2 ϑj ϑS VESD Parameter positive line voltage positive voltage supply (internal or external supply) positive external voltage supply interstate voltage (generated by on-chip regulator) voltage on pin Tx0 voltage on pin RxIN voltage on low voltage pins MODE0, MODE1, TSTIN, TESTMODE voltage on low voltage pins TxD, RESn, TSTOUT, X1, X2, RxD junction temperature Min -0.5 -0.5 -0.5 -0.5 -0.5 -15 -0.5 Max Unit Note 45 V 1) 7 V 2) 7 V 2) 13 V 2) 45 V 1) 45 V 1) 4) VCC +0.5 V -0.5 VIF +0.5 storage temperature -65 V 170 ο 170 ο C C V 3) mA 71.5 K/W 1 W -20 V for 2 µsec and 65 V for 150 µsec 2) Allowed voltage relations: (a) VCC and VVSP normal / VB+ and VIF can be 0 V (b) VVSP normal / VCC , VB+ and VIF can be 0 V (c) VIF normal / VCC , VB+ and VVSP can be 0 V The combination: VCC normal and VVSP = 0 V is not allowed! 3) Human body model: 100 pF, 1.5 kΩ 4) Dynamic via CREC= 47 nF in case of switching-on the bus voltage max. ESD stress voltage ILATCHUP static current for latchup initialization ± 50 Rth thermal resistance of the SOIC-20 package 58.5 PV maximum power dissipation 1) During surge impulse is allowed and guaranteed by ext. elements: ± 1000 1.1.2 Recommended Operating Conditions Symbol VB+ VCC Parameter positive line voltage positive voltage supply for external supply (digital test modes with SHB = 0) positive external supply voltage ambient temperature Min 20 4.75 Max 33 5.25 VIF 3.0 5.25 -25 85 ϑamb fclk clock frequency (external quartz) 4.9152 1) DC voltage of bus, with signal and compensation pulse 11 V ... 45 V Unit Note V 1) V V C MHz ο 1.1.3 Humidity Level The valid susceptibility against humidity is described by JEDEC JESD22-A112, table 1, level 5. The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 3 TP-UART-IC 1.2 DC and AC Characteristics The following parameters are valid in the ambient temperature range ϑamb = -25 οC to 85 οC and for bus voltage VB+ = 20 to 33 V if it is not otherwise declared. When the bus voltage is lower than 20 V and no RESET is active then the normal functionality must be fulfilled, but the parameters may be outside the limits. 1.2.1 Bus Pins VB+ and VB- (Pins 10, 11) Via these pins the ASIC is connected to the bus line. VB- represents the reference potential. Symbol Parameter Min Max Unit Note VVB+ positive line voltage -0.5 45 V 1) Inormal current consumption in analog mode (without clock) 1 mA Inormal current consumption in normal mode (with clock) 1.6 mA 4,9152 MHz 1) during surge impulse is allowed and guaranteed by ext. Elements: -20 V for 2 µs and 65 V for 150 µs 1.2.2 Buffer Voltage VSP (Pin 9) The ASIC delivers a supply voltage of 5 volts to external loads. In order to prevent a rapid change of bus current as a result of a rapid change of the load an external capacitor at the pin VSP is used for energy storage. The static voltage is adjusted to app. 8,8 V (8,2 ...9,2) by an internal regulator. Symbol Parameter Min Max Unit VVSP Energy buffer voltage 5.76 13 V CVSP External storage capacitor 80 µF 1) due to the limited current changing rate an overshoot of VVSP after load change may occur 2) recommended 100 µF; must be larger than the capacitor at VCC Note 1) 2) 1.2.3 Current Controlling Pin CSA (Pin 8) An external capacitor at this pin prevents a quick change of ASIC current in case of quick changing bus voltage VB+ or load current IVCC. The ASIC current changes with a rate of max. 0,5 mA/ms (CCSA = 47 nF). Symbol Parameter CCR max. current changing rate (ext. Start, CCSA = 47 nF) 1)tolerance of capacitor CCSA = 47nF/50V +/- 5% Min 0.2 Max 0.5 Unit mA/ms Note 1) The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 4 TP-UART-IC 1.2.4 Supply Pin VCC (Pin 7) The pin VCC delivers the internal generated voltage supply to external loads. An external short-circuit from the VCC pin to GND will not cause a destruction of the ASIC. Symbol VVCC Parameter Min Max Unit Note Voltage supply (generated by the ASIC or external 4.75 5.25 V 1) source in case of digital test modes) CVCC External storage capacitor 6,8 10 µF +/-20 % IVCC External load at VCC 10 mA 2) 1) VB+ ≥ 11 V 2) If there is a current leap ILeap with a slope greater than 1 mA/ms the following formulas have to be applied: IStat is the static current, i.e. slope not greater than 1 mA/ms IStat ≤ 3 mA; ILeap ≤ (3 mA – IStat) + 5 mA 3mA < IStat ≤ 5 mA; ILeap ≤ 8 mA - IStat IStat > 5 mA; ILeap ≤ 3 mA 1.2.5 Receive Pin RxIN (Pin 13) The Receive Pin RxIN is coupled to the EIB bus by an external capacitor. Symbol Parameter CREC external coupling capacitor 1) external capacitor 47 nF/50V ± 5% Min 44.5 Max 49.5 Unit Note 1) nF typ.47 nF 1.2.6 Transmit Pin TxO (Pin 12) The transmit pin is connected to EIB via external resistor of typ. 68Ω /1W (see Typical Application Circuits). Symbol Parameter VTRANS transmit voltage 1) related to VB+ Min -6 Max -9 Unit Note V 1) 1.2.7 Supply Pin VIF (Pin 3) The Pin VIF is used as supply voltage for the pins TxD, RxD, RESn, TSTOUT, X1, X2 and determines their high input or output level. Symbol VIF CVIF Parameter external supply voltage for interface external storage capacitor Min 3 10 Max 5.5 Unit V nF Note 1) 2) 1) Typical supply voltages: 3.3 V or 5 V 2) Recommended The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 5 TP-UART-IC 1.2.8 Oscillator Pins X1 and X2 (Pins 17, 18) The oscillator pins X1 and X2 are used to connect directly a quartz of 4.9152 MHz without additional external capacitors. These pins are ESD protected to VB - and VIF. Symbol Parameter Min Max Unit Note VX1/2 Oscillator voltage at X1 and X2 -0.5 VIF + 0.5 V VIL Voltage range for input low level 0 0.25 * VIF VIH Voltage range for input high level 0.75 * VIF 1.0 * VIF fclk Clock frequency 2,4576 4,9152 MHz 1) 1) 4,9152 MHz (DIV = VCC) or 2.4576 MHz (DIV = VB -); Tolerance: ±0,05 %; no other clock frequencies Operation Mode Normal Mode with external Clock Analog Mode X1 X2 Clock open VB- open 1.2.9 Internal Clock Divider Pin DIV (Pin 6) This input pin activates an internal 2:1 clock divider. If a 4.9152 MHz clock is used (quartz or external clock) then pin DIV must be connected to VCC. If an 2.4576 MHz clock is used (only external clock) then this pin must be connected to VB -. Symbol VIL VIH Parameter voltage range for input low level voltage range for input high level Min 0 0.8 * VCC Max 0.2 * VCC 1.0 * VCC Unit Note 1.2.10 Interface Pin RxD (Pin 20) The UART interface input pin RxD receives the information from host controller to control the transmitter of the ASIC. This pin is an input pin with pull-down resistor. The switching levels are derived from external voltage supply VIF. This pin is ESD protected to VB- and VIF. In normal mode: RxD = LOW à RxD3 = HIGH à transmitter switches on In analog mode: RxD = HIGH à RxD3 = HIGH à transmitter switches on Symbol Parameter VIL voltage range for input low level VICH voltage range for input high level Vhyst hysteresis for switching level RPullDown value of internal pull-down resistor 1) switching level appr. VIF/2, i.e. VIF/2 ± Vhyst/2 Min 0 0.8 * VIF 0.1 * VIF 150 Max 0.2 * VIF 1.0 * VIF 0.4 * VIF 450 Unit kΩ Note 1) typ.220 kΩ The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 6 TP-UART-IC 1.2.11 Interface Pin TxD (Pin 1) The UART interface output pin TxD transmits the information to host controller. The high output level is derived from external voltage supply VIF. This pin is ESD protected to VBand VIF. In normal mode: LOW pulse at EIB bus à TxD3 = HIGH à TxD = LOW In analog mode: LOW pulse at EIB bus à TxD3 = HIGH à TxD = HIGH Symbol VOH VOL tr, tf Parameter output voltage high output voltage low rise time, fall time (10 % ↔ 90 %) Min VIF - 0.8 Max 0.5 100 Unit V V ns Note IOH = -5 mA IOL = 5 mA CL = 150 pF 1.2.12 Reset Pin RESn (Pin 2) This pin is an I / O pin with internal pull - up resistor to VIF. In case of a reset the reset pin RESn delivers an active LOW signal to external host controller. The output driver is realized as open drain (NMOS - transistor). The reset state RESn = LOW can be caused by an internal RESET or by an external RESET due to forcing an active LOW to the pin RESn. The switching levels are derived from external voltage supply VIF. This pin is ESD protected to VB - and VIF. Symbol RPullUp VRESmax VIL VIH Vhyst VOL VOL Parameter value of internal pull-up resistor to VIF maximum voltage at RES pin voltage range for input low level voltage range for input high level hysteresis for switching level output low voltage at 1V <= VCC < 4 V, IOL = 1 mA output low voltage at VCC <= 1V, VIF > 3 V, IOL = 1 mA VOL output low voltage at VCC >= 4 V, IOL = 3 mA 1) Switching level appr. VIF/2, i.e. VIF/2 ±Vhyst/2 Min 10 0 0.8 * VIF 0.1 * VIF Max 25 VIF + 0.5 0.2 * VIF 1.0 * VIF 0.4 * VIF 0.2 0.2 Unit kΩ V 0.4 V Note 1) V V 1.2.13 Save PIN SAVE (Pin 5) This pin is an NMOS open drain output with internal pullup resistor to VIF. In case of break-down of the bus voltage for more than typ. 1.5 ms (save condition) this pin delivers an active LOW signal to external host electronic. This pin is ESD protected to VBand VIF. Symbol Parameter Min Max Unit Note RPullUp Value of internal pull-up resistor to VIF 10 25 kΩ Vmax maximum voltage at SAVE pin VIF + 0.5 V VOL Output LOW voltage at VCC >= 4V 0.4 V IOL = 3 mA tFRG2 Delay from VB+ break-down to SAVE= LOW 0.7 3 ms Typ. 1.5 ms In order to reach a Buffertime of at least 60 ms for VCC (IVCC ≤ 10 mA) the capacitor at VSP has to be 470 µF ±20 % The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 7 TP-UART-IC 2 Modes of Operation 2.1 Interface to the HOST Controller TP - UART - IC Analog Digital Part Part EIB TxD HOST Controller RxD TxD3 RxD3 Normal Mode: IDLE = HIGH Bus Coupler IDLE = HIGH Mode: IDLE = LOW IDLE = LOW 2.2 Selection of Different Modes of Operation It is possible to choose two different modes of operation: the normal mode and the analog mode. To work in one of those modes you have to adjust the mode control pins as it is shown in following table, in which is also demonstrated the usage of other pins: Operating Modes Mode Mode0 (Pin 14) 1 Control Pins Other Pins Mode1 (Pin 15) 1 Testmode TSTin_BDS (Pin 16) (Pin 4) 0 = 1: 9.600 Baud = 0: 19.200 Baud TSTout_TW (Pin 19) 1) = 1: Temp. Warning Normal Mode --> TxO disabled = 0: Temp. is OK 1)2) 1 0 0 do not care! = 1: Temp. warning Analog Mode (à 19.200 Baud) --> TxO disabled = 0: Temp. is OK 1) After a Temperature Warning was recognized, a second must at least be maintained until the next telegram is sent. 2) Transmission is stopped immediately by the TP_UART_IC. 2.2.1 Normal Mode In the ‘normal’operation mode both parts, digital and analog part, are working. The Idle-level on the UART-interface is 1. (As it is shown in the above standing figure, in chapter 2.1) The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 8 TP-UART-IC 2.2.2 Analog / Bus Coupler Mode In the ‘analog’operation mode the analog part just works. The Idle-level on the UARTinterface is 0. (As it is shown in the above standing figure, in chapter 2.1) The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 9 TP-UART-IC 3 3.1 The DIGITAL - PART Relationship to ISO-Reference-Model ISO - Layer EIB - UART - Layer Applikation - Layer Transport - Layer Host Contoller Network - Layer Link - Logical Link Control Layer UART - Digital - Part Media - Access Control TPUARTIC Physical - Layer UART - Analog - Part Tasks of the Logical Link - Control in: TP - UART - IC : Checksum, Parity, Immediate Acknowledge, Repetition, Timing Host - Controller : Checksum, Parity, Addressing, Length 3.2 UART - Interface 3.2.1 Configuration and Timing The TP-UART-IC has an UART-interface to transmit received EIB-telegrams. The baud rate is as it was mentioned before 19.2 or 9.6 kbaud. The UART-interface has the following firm telegram structure: 1 start bit (= 0) / 8 data bits (LSB first) / 1 parity bit / 1 stop bit (= 1). The signals can be transmit without a break and the Idle-level is 1. The parity bit of every signal is checked while down loading and faults, which can appear, are transmitted to the host controller. The check mechanism runs also while receiving of telegrams from the EIB, but here isn’t any possibility to transmit a fault to the host controller. In those cases the host controller has to recognize the parity faults in the transmitted telegrams by its own. The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 10 TP-UART-IC The UART-interface works with a clock frequency of 307,2 kHz, if it is chosen 9.6 kbaud (32 sample spots per bit), or 614,4 kHz, if it is chosen 19.2 kbaud (32 sample spots per bit). 3.2.2 Resetbehavior After connecting the operating voltage the TP-UART-IC generates an active reset (level 0 V) at pin RESn. This is valid for all modes. If Normal Mode is activated the following will happen at the UART-interface. TxD will be 0 as long as there was no bus signal on the EIB for 40 Tbit (1 Tbit = 1/9600 s; Attention: The bittime of RxD/TxD depends on the adjusted baudrate at the UART-interface, for example 1 Tbit or 0,5 Tbit). This results in a complete time of 40 Tbit + 12 Tbit = 5,42 ms. Then TxD changes for 1 Tbit to 1 and following the service TPUART-Reset.Indication is transmitted. This signal behavior on TxD appears after each reset. 3.2.3 UART-Protocol Definition The protocol between TP-UART-IC and the application controller is a two wire protocol with software handshake. Each data byte transmitted to the TP-UART-IC is started with a control byte. Each data byte received on the EIB is transparently transmitted through the TP-UARTIC and is therefore started with the EIB control field. Additional Information from the TPUART-IC is transmitted with an ESC code on the EIB control field. The host controller which is connected to the TP-UART-IC needs to detect a receive time-out of 2 to 2,5 ms to detect an end of Packet. 3.2.3.1 Services to UART The following Services are supported from the TP-UART-IC. • U_Reset.request • U_State.request • U_Activate Busmonitor • U_AckInformation (Nack, Busy, Addressed) • U_L_DataStart + CTRL-Byte • U_L_DataContinue (index) + Data-Byte • U_L_DataEnd + Checksum • U_PollingState (Slotnumber) + PollAddrHigh + PollAddrLow + State Hexadecimal UART-Control Field Servicename 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 U_Reset.request 0 0 0 0 0 0 1 0 U_State.request 0 0 0 0 0 1 0 1 U_ActivateBusmon 0 0 0 1 0 X X X U_AckInformation 01 02 05 10 - 17 xxx: Nack,Busy,Addressed 1 0 0 0 0 0 0 0 U_L_DataStart 1 0 i i i i i i U_L_DataContinue 80 81 - BE i = Index 0 1 l l l l l l U_L_DataEnd 47 - 7F 1 1 1 0 s s s s U_PollingState E0 - EF l = last index + 1 s = Slotnumber 1 .. 62 7 .. 63 0 .. 14 The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 11 TP-UART-IC 3.2.3.1.1 U_Reset.request-Service Resets the TP-UART-IC to the initial state. At start-up the TP-UART-IC waits for a bus free time-out before sending a U_Reset.indication-Service to the host controller. To be sure that TP-UART-IC is in reset state the host controller has to wait for 50 ms and after that the U_Reset.request-Service can be send. 7 0 6 0 UART-Control Field (01hex) 5 4 3 2 1 0 0 0 0 0 0 1 3.2.3.1.2 U_State.request-Service Requests the internal communication state from TP-UART-IC. The TP-UART-IC answers with the communication state. 7 0 6 0 UART-Control Field (02hex) 5 4 3 2 1 0 0 0 0 1 0 0 3.2.3.1.3 U_ActiveBusmon-Service Activates the busmonitor mode. That means each byte which is received on the EIB is sent through the TP-UART-IC as well as illegal control bytes and not used immediate ACK. The TP-UART-IC is absolute quiet (not sending) on the EIB. The busmonitor mode can only left by using the U_Reset.request-Service. 7 0 6 0 UART-Control Field (05hex) 5 4 3 2 1 0 0 0 1 0 0 1 3.2.3.1.4 U_AckInformation-Service The U_AckInformation-Service is to indicate if the device is addressed. This service must be send latest 1,7 ms (9600 Baud) after receiving the address type octet of an addressed frame. The nack- / busy- / addressed-bits set internal flags in the TP-UART-IC. The internal NACK flag is also be set by the TP-UART-IC itself if it is detecting any frame error. If the TP-UART-IC receive this service and the addressed bit is set it will generate an ACK-, NACK- or BUSY-frame on the EIB depending on the settings of the NACK- / BUSY-flags. 7 0 6 0 UART-Control Field 5 4 3 2 1 0 1 0 x x 1: Nack 1: Busy AckInformation 0 X 1: Addr 0: NotAddr The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 12 TP-UART-IC Receive frame Ack / Nack / Busy Generation of the TP- UART: Addr. No Yes Nack Yes Send NACK No Busy Yes Send BUSY No Send ACK Timing for sending U_AckInformation (9600 Baud): Interchargap (2Bit) Receive from Bus 67ps Send to Host-Con. ps Parity Addresstype s 01234567ps s 01234567ps 1 Startbit 1 Stopbit TPCI s 01234567ps Addresstype s01234567ps 8 Datenbits 15 Bit Pause Checksum s 01234567ps TPCI s 01234567ps Ack s 01234567ps Checksum s 01234567ps Ack-Information s 01234567ps Rec. fr. Host-Con. Send to Bus s 01234567ps Time for Addresssearch (17 Bit) 1 Bit Buffertime 1 Bit Buffertime The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 13 TP-UART-IC 3.2.3.1.5 U_L_Data-Service The U_L_Data-Services are used to transfer the complete EIB-Link-Layer-Frame to the TPUART-IC. TP-UART-IC sending telegram: HOSTController EIB U_L_DATA_Start U_L_DATA_Cont(1) U_L_DATA_Cont(2) U_L_DATA_End TPUART Ctrl-Byte 1. Databyte Ctrl-Byte 1. Databyte 2. Databyte 2. Databyte Chksum Chksum immediate Ack L_DATA_Confirm The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 14 TP-UART-IC TP-UART-IC receiving telegram: HOSTController EIB Ctrl-Byte Ctrl-Byte 1. Databyte 1. Databyte 2. Databyte TPUART 2. Databyte immediate Ack-Info Chksum Chksum immediate Ack 3.2.3.1.5.1 U_L_DataStart-Service The U_L_DataStart-Service initialize the TP-UART-IC to receive a complete EIB-Link-LayerFrame from Host Controller. As additional data the EIB control byte is transmitted which is the control field of the L_Data-frame or L_Polldata-frame. If the repetition flag in the control byte is just cleared the TP-UART-IC transmits the frame only once with repetition flag set. 7 1 UART-Control Field (80hex) 6 5 4 3 2 1 0 0 0 0 0 0 0 0 L-Data Data-Index 00 = Start 7 F 6 F Additional Information 5 4 3 2 R 1 c c EIB control field 1 0 0 0 The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 15 TP-UART-IC FF = Frame Format 10 Standard Length L_DATA-EIB-Frame 00 Long L_DATA-Frames 11 Polling Frame R = Repeat-flag (on the EIB 1 = not repeated, 0 = repeated) 1 = repeat the telegram on the EIB 3 times send first time with repeat flag = 1 and repeat with repeat flag = 0 0 = don’t repeat the telegram on the EIB; send only once with repeat flag = 1 CC = Class: control field FFR1 cc00 FFR1 0000 FFR1 1000 FFR1 0100 FFR1 1100 1111 0000 data link frame type class L_DATA request L_DATA request L_DATA request L_DATA request L_POLLDATA request system alarm high normal system priority repeat flag (0 = repeated) set by TP-UART-IC set by TP-UART-IC set by TP-UART-IC set by TP-UART-IC =1 3.2.3.1.5.2 U_L_DataContinue-Service The U_L_DataContinue-Service transmits one byte containing an EIB-L_Data-Frame to the TP-UART-IC. The index starts with 1 and the maximum value is 62 depending on the length of the frame. But the EIB confirms just the length of 22 Bytes. 7 1 6 0 L-Data 5 i UART-Control Field 4 3 2 i i i Index 1 i 0 i 7 d Additional Information 5 4 3 2 1 d d d d d EIB-Data Byte for L-Data-Frame 6 d 0 d 3.2.3.1.5.3 U_L_DataEnd-Service The U_L_DataEnd-Service marks the end of the transmission of the EIB frame. After receiving this service the TP - UART controls the checksum and in case of correctness it starts the transmission on the EIB, else the UART returns a state indication with receiveerror flag is set. 7 0 6 1 L-Data UART-Control Field(40 hex) 5 4 3 2 1 l l l l l last index + 1 0 l 7 c 6 c 5 c Additional Information 4 3 2 c c c Checksum 1 c 0 c The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 16 TP-UART-IC 3.2.3.1.6 U_Polling-State This service must be send to the TP-UART-IC if a polling-frame-control-byte is received. If the TP-UART-IC detects a collision during sending the slave slot to the EIB TP - UART generates a state indication with the slave collision flag set. 7 1 6 1 5 1 7 c 6 c 5 c UART-Control Field 4 3 2 1 0 0 s s s s Slotnumber Polling Address Low 4 3 2 c c c 1 c 0 c 7 c 6 c 5 c 7 c 6 c 5 c Polling Address High 4 3 2 c c c Polling State 4 3 2 c c c 1 c 0 c 1 c 0 c Timing for U_PollingState-Service (9600 Baud): Receive from Bus Ctrl-Byte s 01234567ps Src-Addr s 01234567ps Src-Addr s 01234567ps PollAddr s 01234567ps PollAddr s 012345 Ctrl-Byte s 01234567ps Send to Controller X1 PollCtrl+Slotnr s 01234567ps Rec from Controller PollAddr s 01234567ps PollAddr s 01234567 Send to Bus continuos ... PollAddr 567ps Receive from Bus Slotcount s 01234567ps Checksum s 01234567ps Slot 0 s 01234567ps Slot 1 s 01234567 Send to Controller X1 Rec From Controller PollAddr Pollingstate 7ps s 01234567ps Slot 0 s 01234567ps Send to Bus The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 17 TP-UART-IC Timing for U_PollingState-Service for a Master (9600 Baud): Send to Bus Ctrl-Byte s 01234567ps Src-Addr s 01234567ps Src-Addr s 01234567ps PollAddr s 01234567ps PollAddr s 01234 Receive from Bus Ctrl-Byte s 01234567ps Src-Addr s 01234567ps Src-Addr s 01234567ps PollAddr s 01234567ps PollAddr s 01234 X2 Ctrl-Byte s 01234567ps Send to Host-Con. Src-Addr s 01234567ps PollCtrl+Slotnr s 01234567ps Rec. f. Host-Con. Send to Bus PollAddr 567ps Slotcount s 01234567ps Checksum s 01234567ps Receive from Bus PollAddr 567ps Slotcount s 01234567ps Checksum s 01234567ps Src-Addr s 01234567ps PollAddr s 01234567ps Poll Addr s 012345 PollAddr s 0123456 Fillbyte for Slot0 s 01234567ps Slot 0 s 01234567ps s 01234567ps Slot 1 s 01234567ps X2 Send to Host-Con. PollAddr PollAddr 7ps s 01234567ps Rec. f. Host-Con. PollAddr Pollingstate 7ps s 01234567ps Slotcount s 01234567ps Checksum s 01234567ps Slot 0 s 01234567ps The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 18 TP-UART-IC 3.2.3.2 Services from UART The first character of each service which is sent to the host controller is the control field. The control field contains the information about the TP - UART-Service. There are 3 types of services which can be send to the host controller: the EIB-Layer-2-Services, the ImmediateAcknowledge-Services and the special TP – UART - Services. The EIB-Layer-2-Services contain information about their class and also a flag which contains the information whether the LPDU is a repeated one, or not. The Immediate-Acknowledge-Services include information about a successful sending. The TP – UART - Services are to inform the host controller about the communication state or to reset the communication. Control Field 7 6 5 4 3 2 1 0 repeat flag = 0: repeated L_DATA frame class class repeat flag Layer-2 Services repeat flag = 1: not repeated 1 0 r 1 c1 c0 0 0 L_DATA.ind 0 0 r 1 c1 c0 0 0 L_LONG_DATA.ind c1 c0 0 0 system priority 1 1 1 1 0 0 0 0 L_Poll_Data.ind 1 0 alarm priority Immediate Acknowledge Services 0 1 high priority 1 1 0 0 1 1 0 0 Acknowledge frame 0 0 0 0 1 1 0 0 NotAcknowledge frame 1 1 low priority 1 1 0 0 0 0 0 0 Busy frame EIBUART-Control-Services 0 0 0 0 0 0 1 1 Reset-Indication x x x x x 1 1 1 State-Response/Indication x 0 0 0 1 0 1 1 L_DATA.confirm x = 1 Positive Confirm x = 0 Negative Confirm 3.2.3.2.1 Layer-2-Services The Layer-2-Services include all standard EIB Link-Layer-Services. The control fields are followed by the data of the EIB frame. All bytes received on the EIB are immediately sent to the host controller. The host controller has to detect a end of packet time out by supervising the EOP gap of 2 to 2.5 bittimes. control field Hexadecimal FFR1 cc00 long/normal FF11 0000 30/B0Hex FF01 0000 10/90Hex FF11 1000 38/B8Hex FF01 1000 18/98Hex FF11 0100 34/B4Hex FF01 0100 14/94Hex FF11 1100 3C/BCHex FF01 1100 1C/9CHex 1111 0000 F0Hex data link frame type class L_DATA request L_DATA request L_DATA request L_DATA request L_DATA request L_DATA request L_DATA request L_DATA request L_POLLDATA request system system alarm alarm high high normal normal system Repeat flag (0 = repeated) Not repeated Repeated Not repeated Repeated Not repeated Repeated Not repeated Repeated The frame format 01 is not supported. For a complete description of the Link-Layer service see the EIB - Handbook. The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 19 TP-UART-IC Each L_Data-request is transmitted completely to the host controller. If TP - UART is polling master the complete polling frame is transmitted to the host controller and regardless of whether a collision is detected while sending the polling frame, or not. In case TP - UART is polling slave just the control byte out of L_PollData-request is transmitted to the host controller. 3.2.3.2.2 Acknowledge-Services Acknowledge-Services are just transmitted to the host controller in busmonitor mode. The short acknowledgment frame format consists of 15 Tbit (1 Tbit = 1/9600 s) idle time followed by a single character which is used to acknowledge a L_Data.req frame. The following figure shows the corresponding codes of the short acknowledgment. 8 1 0 1 7 1 0 1 6 0 0 0 Octet 0 Short ACK 5 4 0 1 0 1 0 0 3 1 1 0 2 0 0 0 1 0 0 0 ACK NACK BUSY 3.2.3.2.3 TP-UART-Control-Services The TP-UART-Control-Services are services which exist only on this interface. They have to reset the communication or to inform the host controller about the actual state. 3.2.3.2.3.1 TP-UART-Reset.indication-Service The Reset.indication-Service is sent after each reset (e.g. TP_UART_Reset.requ). 7 0 TP-UART-Control Field 5 4 3 2 0 0 0 0 6 0 1 1 0 1 3.2.3.2.3.2 TP-UART-State.indication/response-Service The TP-UART-State.response-Service is sent if an U_State.request-Service was received from the host controller. In case of a slave collision, receive error, checksum error or protocol error the TP-UART-IC sends a State.indication-Service. 7 SC SC RE TE PE TW 1) 6 RE = = = = = TP-UART-Control Field 5 4 3 2 TE PE TW 1 1 1 0 1 Slave Collision Receive Error (checksum, parity or bit error) Transmitter Error (send 0 receive 1) Protocol Error (e.g. illegal control byte) 1) Temperature Warning After a temperature warning was received, a second must at least be maintained until the next telegram is sent. The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 20 TP-UART-IC Attention: A received L_Data frame can follow the State-Indication without any delay. 3.2.3.2.3.3 TP-UART-L_Data.confirm Service The L_DATA.confirm service is transmitted to the host controller if an acknowledge was received or the last repetition is transmitted and no acknowledge was received. 7 x 6 0 TP-UART-Control Field 5 4 3 2 1 0 0 1 0 1 0 1 X = 1 à The transmission of the L_DATA frame was successful X = 0 à The transmission of the L_DATA frame was not successful The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 21 TP-UART-IC 4 INTERFACE BLOCK DIAGRAM PIN Description (The drawing of the pins is shown on first page) Pin # 1 2 3 4 Name TxD RESn VIF TSTIN_BDS Type OUT IO_HYST SUPPLY IO 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SAVE DIV VCC CSA VSP VB+ VBTXO RxIN MODE0 MODE1 TESTMODE X1 X2 TSTOUT_TW RxD OUT IN POWER ANALOG POWER POWER POWER ANALOG ANALOG IN IN IN IN IN OUT IN_HYST Description data transmit to host controller reset pin external supply (5V or 3.3V) input for digital test / baud rate select; output for analog test save pin internal clock divider 2:1 active external power supply 5 V current changing rate control interstate voltage blocking capacitor positive bus pin negative bus pin transmit output current (bus signal) capacitive coupling of bus signal mode control pin 1 mode control pin 2 mode control pin 3 crystal oscillator pin 1, external clock crystal oscillator pin 2 digital test / temperature signal data receive from host controller The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 22 TP-UART-IC 5 MECHANICAL SPECIFICATION A A1 A2 B C D E e H h L α SOIC 20 (300 MIL) Dimensions (mm) min. nom. 2.46 2.56 0.127 0.22 2.29 2.34 0.35 0.41 0.23 0.25 12.70 12.83 7.42 7.52 1.27 BSC 10.16 10.31 0.25 0.33 0.61 0.81 o o 0 5 Max. 2.64 0.29 2.39 0.48 0.32 12.95 7.59 10.41 0.41 1.02 o 8 h x 45o α C L E H 1 e B D A1 A2 A The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 23 TP-UART-IC 6 APPENDIX 6.1 Typical Application Circuits 6.1.1 Normal Mode RESn D1 A BYG21M VCC SAVE TxD U1 1 2 3 U2 4 SMAJ43CA 5 6 7 C2 8 9 47n/50V 10 TxD RESn RxD TSTOUT VIF X2 TSTIN X1 SAVE TEST MODE DIV MODE1 VCC MODE0 CSA RxIN VSP TxO VB+ VB- 20 19 RxD VCC 18 Y1 17 C1 16 R1 68/1W 4,915MHz 15 47n/50V 14 13 12 11 TP-UART-01 2) C5 10n C3 6,8u + + 3) C4 100u/16V 2) C6 10n GND B TSTIN = Low => 19200 Baud 2) recommended (close to Pins VSP and VCC) 3) Buffertime of VCC after SAVE active, see 1.2.13 The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 24 TP-UART-IC 6.1.2 Analogmode RESn D1 A BYG21M VCC SAVE TxD U1 1 2 3 U2 4 SMAJ43CA 5 6 7 C2 8 47n/50V 9 10 TxD RESn RxD TSTOUT VIF X2 TSTIN X1 SAVE TEST MODE DIV MODE1 VCC MODE0 CSA RxIN VSP TxO VB+ VB- 20 19 RxD VCC 18 17 C1 16 R1 1) 68/1W 15 14 13 12 11 47n/50V TP-UART-01 2) C5 10n + C3 6,8u 3) 2) C4 100u/16V C6 10n + GND B 1) The maximum average powerdissipation of the transmitting resistance of 1 W is valid for an active telegramrate of 50 % 2) recommended (close to Pins VSP and VCC) 3) Buffertime of VCC after SAVE active, see 1.2.13 The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 25 TP-UART-IC 6.1.3 PART LIST *) No. Component Type/Value U1 IC TP-UART-IC Remarks U2 Suppressor Diode SMAJ43CA Manufacturer: General Semiconductor D1 Rectifier Diode BYG21M Fast rectifier, Manufaturer: Vishay, Temic C1, C2 Capacitor 47nF/50V/ ±5% Ceramic C3 Capacitor 6,8uF/6.3V/ ±20% Electrolytic, useful life at 105°C : 2000h C4 Capacitor 100uF/16V/ ±20% Electrolytic, useful life at 105°C : 2000h C5, C6 Capacitor 10nF/50V/ ±10% Ceramic R1 Resistor 68/±5% 1W Y1 Quarz 4.9152MHz/50ppm/30pF *)additional components may be required because of EMC 6.2 Galvanic Isolation The interface pins TxD, RxD and TSTOUT_TW are prepared for galvanic isolation with optocouplers. The interface output pins TxD and TSTOUT_TW provide a driver current of 5 mA, thus the transmitting diode of an optocoupler can be connected directly. The interface input pin RxD is implemented as a Schmitt Trigger. There are no additional level shifters after the output of the optocoupler necessary. In Normal Mode it is possible to recognize a reset via TxD without an additional optocoupler. Please refer to 3.2.2. A busvoltage breakdown can also be monitored if in quiescent state the transmitting diode belonging to TxD is active. The data contained herein are subject to change without notice. Siemens does not warrant for correctness or completeness of the documentation or that the products described are qualified for certification. The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes reserved. 25.15.10.41.33a 25.10.01 page 26