Ordering number : EN5521 CMOS LSI LC7874E CD Graphics Decorder Overview The LC7874E is a CMOS LSI that provides the signal processing needed for compact disc graphics (CD-G) on a single chip. The LC7874E accepts subcode R to W signals output from a CD player DSP LC786X Series, LC7862XE Series, or LC7863XE Series device, and performs de-interleaving, error detection and correction, graphic instruction processing, and image processing. • Has microcomputer interface functions, allowing set upgrading. • Provides superimposition support. • Has a color bar signal output function. • DRAM interface and RGB output and sync signal output are 3-state outputs. Package Dimensions unit: mm Features 3159-QFP64E • A CD-G decoder can be configured using a three-chip combination of this LSI—the LC7874E—with external RAM (64K × 4 bits) and an LC78010E digital RGB encoder. • Performs insertion and protection of CD subcode R to W sync signals and detection of R to W signal deinterleave error signals. • Has two crystal oscillators, for NTSC and PAL, with simple switchover by means of a control pin. Connecting a crystal resonator of 14.31818 MHz for NTSC and 17.734476 MHz for PAL enables the standard clock and other necessary timings to be generated internally. • Performs CD graphics instruction processing and drawing functions, and controls image display. [LC7874E] SANYO: QIP64E • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Specifications Electrical Characteristics at Ta = –30°C to +85°C Parameter Power supply voltage Symbol VDD Conditions VDD Ratings Unit VSS – 0.3 to VSS + 7.0 V VSS – 0.3 to VDD + 0.3 V VSS – 0.3 to VDD +0 .3 V S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to 3, Input voltage VIN CB, CE1, CE2, CE3, LINE, HRESET, VRESET, INIT, RESET, N/P, SON, XIN1, XIN2 SBCK, DO, CDGM, WE, RAS, A0 to 7, DB0 to 3, CAS, OE, Output voltage VOUT ROUT0 to 3, GOUT0 to 3, BOUT0 to 3, HSYNC, CSYNC, BLANK, YS, 4FSCO, EFLG, FSCO, XOUT1, XOUT2 Allowable power dissipation Pd max Ta = 25°C 500 mW Operating temperature Topr –30 to +85 °C Storage temperature Tstg –40 to +125 °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 13097HA(OT) No. 5521-1/22 LC7874E Allowable Operating Ranges at Ta = –30°C to +85°C Parameter Power supply voltage Input high-level voltage Input low-level voltage Symbol Input amplitude Ratings min typ Unit max VDD VDD 5.5 V VIH1 S1, S2, CB LINE, N/P, SON 0.7 VDD VDD + 0.3 V VIH2 INIT, RESET 0.8 VDD VDD + 0.3 V VIH3 CL 0.8 VDD 5.8 V VIH4 DB0 to DB3, HRESET, VRESET 2.2 VDD + 0.3 V VIH5 SFSY, PW, SBSY, CE, DI, MUTE, CE1 to CE3 2.2 5.8 V VIL1 S1, S2, CB, LINE, N/P, SON VSS – 0.3 0.3VDD V VIL2 CL, INIT, RESET VSS – 0.3 0.2VDD V VSS – 0.3 0.8 V VIL3 Input frequency Conditions 3.0 SFSY, PW, SBSY, CE, DI, MUTE, DB0 to DB3, CE1 to CE3, HRESET, VRESET 5.0 FSCIN1 XIN1 14.31818 FSCIN2 XIN2 17.734476 VIN XIN1, XIN2 0.5 MHz MHz VDD Vp-p Electrical Characteristics at Ta = –30 to +85°C, VDD = 5 V unless otherwise specified Parameter Symbol Conditions Ratings min typ Unit max S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, Input high-level current IIH1 DB0 to DB3, LINE, HRESET, VRESET, CE1 to 3, 5 µA 200 µA INIT, RESET, N/P, SON : VIN = VDD IIH2 CB : VIN = VDD 30 100 S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, Input low-level current IIL1 DB0 to DB3, CB, LINE, HRESET, VRESET, –5 µA CE1 to 3, INIT, RESET, N/P, SON : VIN = VSS SBCK, WE, RAS, A0 to 7, CAS, OE, DB0 to 3, CDGM, ROUT0 to 3, GOUT0 to 3, BOUT0 to 3, Output high-level voltage VOH FSCO, 4FSCO, HSYNC, YS, CSYNC, VDD – 1 VDD V VSS 0.4 V –5 +5 µA BLANK, EFLG : IOH = –0.5 mA SBCK, WE, RAS, A0 to 7, CAS, OE, DB0 to 3, CDGM, ROUT0 to 3, GOUT0 to 3, BOUT0 to 3, Output low-level voltage VOL FSCO, 4FSCO, HSYNC, YS, CSYNC, BLANK, EFLG : IOL = 2.0 mA A0 to A7, RAS, CAS, OE, WE, DB0 to DB3, Output off leakage current IOFF HSYNC, ROUT0 to 3, GOUT0 to 3, BOUT0 to 3, CSYNC, BLANK, FSCO, 4FSCO Built-in feedback resistance RX XIN1, XIN2 Clock frequency fO SBCK Operating current drain IDD VDD 1 MΩ 220 kHz 26 40 mA No. 5521-2/22 LC7874E Timing Characteristics (Microcontroller Interface Timing) at Ta = 25°C, VDD = 5 V Parameter Symbol Conditions Ratings min typ max Unit tWH CL, high pulse width 400 ns tWL CL, low pulse width 400 ns Data setup time tDS DI, CL 200 ns Data hold time tDH DI, CL 200 Data hold time tDOH DO, CL 130 tCP CE, CL 400 ns CE setup time tCS CE, CL 400 ns CE hold time tCH CE, CL 400 ns Input minimum pulse width CE wait time ns 300 ns No. 5521-3/22 LC7874E Timing Characteristics (DRAM Access Timing) at Ta = 25°C, VDD = 5 V Parameter Symbol Conditions Ratings min typ max Unit Random read/write cycle time tRC 250 ns Page mode cycle time tPC 130 ns RAS precharge time tRP 100 ns RAS pulse width tRAS 120 RAS pulse width (page mode) tRASP RAS hold time tRSH 60 CAS hold time tCSH 120 ns CAS pulse width tCAS 60 ns CAS precharge time tCPN 50 ns CAS precharge time tCP 50 ns Row address setup time tASR 100 ns Row address hold time tRAH 50 ns ns 18000 (In page mode) ns ns Column address setup time tASC 0 ns Column address hold time tCAH 50 ns Read command setup time tRCS 150 ns Read command hold time tRCH (Referenced to CAS ) 120 ns Read command hold time tRRH (Referenced toRAS) 120 ns Write command setup time tWCS 100 ns Write command hold time tWCH 50 ns Write command pulse width tWP 150 ns Write data setup time tDS 100 ns Write data hold time tDH 100 ns CAS setup time tCSR (CAS before RAS) 50 ns CAS hold time tCHR (CAS before RAS) 50 ns tRPC 50 ns Read data setup time tRDS 20 ns Read data hold time tRDH 10 Refresh time tREF RAS precharge CAS active time ns 3.5 ms No. 5521-4/22 LC7874E DRAM Read Cycle No. 5521-5/22 LC7874E DRAM Early Write Cycle No. 5521-6/22 LC7874E DRAM Page Mode Read Cycle No. 5521-7/22 LC7874E DRAM Page Mode Write Cycle DRAM CAS-Before-RAS Refresh Cycle No. 5521-8/22 LC7874E Pin Assignment No. 5521-9/22 LC7874E Pin Functions Pin Pin Symbol 1 S1 Pin Name CD DSP selection pins 2 S2 I/O In Polarity Function S1 S2 0 0 LC7861N/67 1 0 LC7860K/63 0 1 Setting prohibited 1 1 LC7868/62X/63X Positive Selected CD DSP 3 SBCK Clock output pin Out — 4 SFSY Sync signal input pin In Positive Subcode frame sync signal input (MORE+ input) 5 PW Data input pin In Positive Subcode R to W data input (MORE+ input) 6 SBSY Sync signal input pin In Positive 7 VDD Power supply pin (+5 v) — — 8 CE Enable input pin In Positive Serial input/output data control input (MORE+ input) 9 DO Data output pin Out Positive Serial data output (Nch open-drain) 10 DI Data input pin In Positive Serial data input (MORE+ input) 11 CL Clock input pin In Positive Serial data input/output clock input (MORE+ input) 12 MUTE Data input pin In Positive 13 VSS Ground pin (GND) — — 14 CB Color bar selection pin In Positive L: Normal mode, H: Color bar output (built-in pull-down resistor) Out Positive Goes high when graphics data is input (can be reset low by command control). DRAM control input pin In Positive Signal input setting DRAM connection pin to high impedance (MORE+ input) Graphic data discrimination output pin Subcode R to W read clock output Subcode block sync signal input (MORE+ input) Digital power supply Control signal input invalidating subcode data (MORE+ input) GND 15 CDGM 16 CE1 17 A0 DRAM output pin I/O Positive DRAM address (A0) output 18 A1 DRAM output pin I/O Positive DRAM address (A1) output 19 A2 DRAM output pin I/O Positive DRAM address (A2) output 20 A3 DRAM output pin I/O Positive DRAM address (A3) output 21 A4 DRAM output pin I/O Positive DRAM address (A4) output 22 A5 DRAM output pin I/O Positive DRAM address (A5) output 23 A6 DRAM output pin I/O Positive DRAM address (A6) output 24 A7 DRAM output pin I/O Positive DRAM address (A7) output 25 CAS DRAM output pin 3ST Negative DRAM column address strobe signal output 26 WE DRAM output pin 3ST Negative DRAM data write enable signal output 27 OE DRAM output pin 3ST Negative DRAM data read enable signal output 28 RAS DRAM output pin 3ST Negative DRAM row address strobe signal output 29 DB0 DRAM input/output pin I/O Positive DRAM data (D0) input/output 30 DB1 DRAM input/output pin I/O Positive DRAM data (D1) input/output 31 DB2 DRAM input/output pin I/O Positive DRAM data (D2) input/output 32 DB3 DRAM input/output pin I/O Positive DRAM data (D3) input/output 33 BLANK Blank signal output pin 3ST Positive Video signal blanking period output 34 CSYNC Composite sync output pin 3ST Negative Composite sync signal output Continued on next page. No. 5521-10/22 LC7874E Continued from preceding page. Pin Pin Symbol Pin Name I/O 35 HSYNC Horizontal synchronization output pin 3ST Negative Horizontal sync signal output Polarity Function 36 ROUT3 R data output pin I/O Positive Video signal R3 data output 37 ROUT2 R data output pin I/O Positive Video signal R2 data output 38 ROUT1 R data output pin I/O Positive Video signal R1 data output 39 ROUT0 R data output pin I/O Positive Video signal R0 data output 4 × FSC clock output NTSC: 14.31818 MHz PAL: 17.734476 MHz Subcarrier clock output NTSC: 3.579545 MHz PAL: 4.433619 MHz 40 4FSC0 Clock output pin 3ST Positive 41 FSC0 Clock output pin 3ST Positive 42 GOUT3 G data output pin I/O Positive Video signal G3 data output 43 GOUT2 G data output pin I/O Positive Video signal G2 data output 44 GOUT1 G data output pin I/O Positive Video signal G1 data output 45 GOUT0 G data output pin I/O Positive Video signal G0 data output 46 BOUT3 B data output pin I/O Positive Video signal B3 data output 47 BOUT2 B data output pin I/O Positive Video signal B2 data output 48 BOUT1 B data output pin I/O Positive Video signal B1 data output 49 BOUT0 B data output pin I/O Positive Video signal B0 data output 50 CE2 Video output control input pin In Positive Signal input setting video output pin to high impedance (MORE+ input) 51 CE3 Sync signal control input pin In Positive Signal input setting sync signal output pin to high impedance (MORE+ input) Superimposition output pin Out Positive Superimposition control output Error status monitor output pin Out Positive Error status monitor signal output 52 YS 53 EFLG 54 HRESET 55 LINE 56 VRESET 57 INIT 58 RESET 59 60 External horizontal synchronization input pin In Line number selection pin In External vertical synchronization input pin In Negative External vertical synchronization timing control pin Initial input pin In Negative System initial signal input Reset input pin In Negative System reset signal input N/P NTSC/PAL selection input pin In Positive NTSC/PAL selection input L: NTSC, H: PAL SON Superimposition control pin In Positive Superimposition ON/OFF control input H: Superimposition ON 61 XIN2 62 XOUT2 63 XIN1 64 XOUT1 Crystal oscillator connection pins Crystal oscillator connection pins Negative External horizontal synchronization timing control pin — In — Out — In — Out — Line number selection input NTSC : L = 263H, H = 262H PAL : H = 312H, L = 314H PAL crystal oscillator connection pin (4Fsc = 17.734476 MHz) NTSC crystal oscillator connection pin (4Fsc = 14.31818 MHz) No. 5521-11/22 LC7874E Block Diagram No. 5521-12/22 LC7874E CD-G Instructions The contents of instructions in the CD Red Book which are supported by the LC7874E are as follows. ZERO mode (MODE = 0, ITEM = 0) LINE GRAPHICS mode (MODE = 1, ITEM = 0) ① INSTRUCTION (4): Write FONT ② INSTRUCTION (12): Write Scroll SCREEN TV GRAPHICS mode (MODE = 1, ITEM = 1) ① INSTRUCTION (1): Preset MEMORY ② INSTRUCTION (2): Preset BORDER ③ INSTRUCTION (6): Write FONT FOREGROUND/BACKGROUND ④ INSTRUCTION (20): scroll SCREEN with preset ⑤ INSTRUCTION (24): scroll SCREEN with copy ⑥ INSTRUCTION (30): Load CLUT color-0 color-7 ⑦ INSTRUCTION (31): Load CLUT color-8 color-15 ⑧ INSTRUCTION (38): EXCLUSIVE-OR FONT Outline of Functions 1. Crystal clock oscillation: XIN1, XOUT1, XIN2, XOUT2, N/P, 4FSCO, FSCO XIN1 and XOUT1 are 14.31818 MHz (NTSC) crystal oscillator connection pins, and XIN2 and XOUT2 are 17.734476 MHz (PAL) crystal oscillator connection pins. Both modes can be supported by switching the N/P pin. The 4FSCO pin outputs the Xtal OSC clock, and the FSCO pin outputs this clock divided by 4. The pin functions in each mode are shown below. XIN1, XOUT1 XIN2, XOUT2 N/P TV system 4FSCO FSCO 14.31818 MHz * L NTSC/M 14.31818 MHz 3.579545 MHz * 17.734476 MHz H PAL/GBIDH 17.734476 MHz 4.433619 MHz 2. Subcode interface: S1, S2, SBCK, SFSY, PW, SBSY Control of the S1 and S2 pins provides interfacing with the following three modes. Driving the mute pin high disables SBSY and PW input and SBCK output. S1 S2 L L LC7861N/67 interface Mode H L LC7860K/63 interface H H LC78681/62X/63X interface No. 5521-13/22 LC7874E With the LC7860K/63 interface, SBCK is transmitted when SFSY is confirmed to be low approximately 2.2 µs after a falling edge of SFSY is detected. With other interfaces, SBCK is transmitted when SFSY is confirmed to be high and SBSY to be low approximately 2.2 µs after a rising edge of SFSY is detected. (1) LC7860 interface [DSP pin names shown in parentheses] (2) LC7861N/67 interface [DSP pin names shown in parentheses] (3) LC78681/62X/63X Series interface Same as (2), except that the SBCK polarity is shifted inversely (shifted on rise of SBCK). 3. DRAM interface Interface pins: A0 to A7, DB0 to DB3, RAS, CAS, WE, OE 64K × 4-bit DRAM is connected externally. The interface pins are set to high impedance by driving the CE1 pin high. MPEG DRAM sharing is possible. 4. CD graphic monitor pin: CDGM CDGM goes high once the LC7874E accepts any CD-G instruction. In the power-on state, once CDGM goes high it remains high. It can be driven low by driving the INIT pin low or transferring an INIT command from the microcontroller. No. 5521-14/22 LC7874E 5. Display format 6. Video output: ROUT0 to ROUT3, GOUT0 to GOUT3, BOUT0 to BOUT3 7. Error flag output: EFLG Error detection results can be monitored with the EFLG pin. No. 5521-15/22 LC7874E 8. Color bar output: CB When the CB pin is driven high, color bars are output from the video output pins. Details of the color bars are shown below. R G ➀ White F F B F ➁ Gray B B B ➂ Yellow F F O ➃ Cyan O F F ➄ Green O F O ➅ Magenta F O F ➆ Red F O O ➇ Blue O O F BORDER (BLACK) O O O Drawing Functions (Graphic Functions) 1. Operating modes (scan operation, display operation) NTSC mode • Non-interlace • Dot clock • System clock 60 Hz (262 or 263 lines) 2fsc: 7.15909 MHz (T = 139.67 ns) 4fsc: 14.31818 MHz PAL mode • Non-interlace • Dot clock • System clock 50 Hz (312 or 314 lines) 4fsc × 2/5: 7.09379 MHz (T = 140.97 ns) 4fsc: 17.734476 MHz PAL60 mode • Non-interlace • Dot clock • System clock 60 Hz (262 or 263 lines) 4fsc × 2/5: 7.09379 MHz (T = 140.97 ns) 4fsc: 17.734476 MHz 2. Display functions • Display resolution • Image data area • 16-color display 288 dots × 192H 300 dots × 216H Selection of 16 colors from 4096 Microcontroller Interface (CCB) 1. Transfer format (for command transfer) Transfer format (example) No. 5521-16/22 LC7874E Display Control Command Table First byte Command Second byte MSB Command identification code LSB 7 6 5 4 3 2 1 0 MSB 7 Data 6 5 4 LSB 3 2 1 0 TV/ LINE VRAM /BG Register 00HEX (Various mode settings) 0 0 0 0 0 0 0 0 INIT SCP2 SCP1 SCP0 CB DISK /GPH Register 10HEX (Fine adjustment of screen position) 0 0 0 1 0 0 0 0 VP3 VP2 VP1 VP0 HP3 HP2 HP1 HP0 Register 20HEX (Channel 0 to 7 ON/OFF) 0 0 1 0 0 0 0 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Register 30HEX (Channel 8 to 15 ON/OFF) 0 0 1 1 0 0 0 0 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 Register 40HEX (BGC R, G settings) 0 1 0 0 0 0 0 0 BGG3 BGG2 BGG1 BGG0 BGR3 BGR2 BGR1 BGR0 Register 50HEX (BGC B setting) 0 1 0 1 0 0 0 0 0 0 0 0 BGB3 BGB2 BGB1 BGB0 Register 60HEX (Chroma key color R, G settings) 0 1 1 0 0 0 0 0 CKG3 CKG2 CKG1 CKG0 CKR3 CKR2 CKR1 CKR0 Register 70HEX (Chroma key color B setting) 0 1 1 1 0 0 0 0 0 0 0 0 CKB3 CKB2 CKB1 CKB0 Register 80HEX (YS output phase adjustment) 1 0 0 0 0 0 0 0 CSY SEL PAL 60 0 YT4 YT3 YT2 YT1 YT0 Register 90HEX (External synchronization mode, test mode) 1 0 0 1 0 0 0 0 CV SEL MVMD EXSN HVMK 0 TST2 TST1 TST0 Register A0HEX (Subtitle scroll: vertical) 1 0 1 0 0 0 0 0 0 0 0 SCV4 SCV3 SCV2 SCV1 SCV0 Register B0HEX (Subtitle scroll: horizontal) 1 0 1 1 0 0 0 0 0 0 SCH5 SCH4 SCH3 SCH2 SCH1 SCH0 Register 01HEX (19-byte command input) 0 0 0 0 0 0 0 1 R S T U V W 0 0 No. 5521-17/22 LC7874E Description of Commands Command transmission should be performed LSB-first. 1. Control item code 00HEX: Various mode settings Default: MSB [01100000] LSB Data 0: VRAM/BG Display screen switchover setting 0: VRAM contents displayed 1: Background color displayed Data 1: TV/LINE Graphic display mode setting 0: TV graphic mode 1: LINE graphic mode Data 2: DISK/GPH Disk command acceptance control 0: DISK command only accepted 1: DISK command acceptance ignored, MGC (Micro graphic command) only accepted Data 3: CB Color bar screen output setting 0: Graphic signal output 1: Color bar signal output Data 4: SCP0 YS output (pin 52) control Data 5: SCP1 Superimposition compare condition (valid only when SON = 1: pin 60) SCP1 SCP0 0 0 Comparison not performed Compare condition 1 0 When border color is black, YS is high (display) in the parts whose color does not match the border color, and low (transparent) otherwise 1 1 High in parts whose color does not match the chroma key color; low otherwise Data 6: SCP2 YS output (pin 52) control 0: When SCP0, SCP1 = 0, 0; 0, 1, and compare condition is not satisfied, setting is full-screen low (transparent) 1: L: When SCP0, SCP1 = 0, 0; 0, 1, and compare condition is not satisfied, setting is full-screen high (display) Data 7: INIT Software reset setting 0: Internal reset not executed (normal) 1: Internal reset executed (display screen becomes blue background screen) 2. Control item code 10HEX: Fine adjustment of screen position Default: MSB [00000000] LSB Data 0: Data 1: Data 2: Data 3: Data 4: Data 5: Data 6: Data 7: HP0 HP1 HP2 HP3 VP0 VP1 VP2 VP3 Horizontal fine adjustment of screen position Specified as two’s complement with left as positive direction (variable by –16 to +14 dots from center in 2-dot units) Vertical fine adjustment of screen position Specified as two’s complement with up as positive direction (variable by –16 to +14 dots from center in 2-dot units) No. 5521-18/22 LC7874E 3. Control item code 20HEX: Channel on/off setting Default: MSB [00000011] LSB Data 0: CH0 CH0 to CH7 on/off setting Data 1: CH1 Data 2: CH2 0: Channel off Data 3: CH3 1: Channel on Data 4: CH4 Data 5: CH5 Data 6: CH6 Data 7: CH7 4. Control item code 30HEX: Channel on/off setting Default: MSB [00000000] LSB Data 0: CH8 CH8 to CH15 on/off setting Data 1: CH9 Data 2: CH10 0: Channel off Data 3: CH11 1: Channel on Data 4: CH12 Data 5: CH13 Data 6: CH14 Data 7: CH15 5. Control item code 40HEX: BGC color (R, G) settings Default: MSB [00000000] LSB Data 0: BCR0 BGC color: R setting = 16 kinds Data 1: BCR1 Data 2: BCR2 Data 3: BCR3 Data 4: BCG0 BGC color: G setting = 16 kinds Data 5: BCG1 Data 6: BCG2 Data 7: BCG3 6. Control item code 50HEX: BGC color (B) setting Default: MSB [00001010] LSB Data 0: BCB0 BGC color: B setting = 16 kinds Data 1: BCB1 Data 2: BCB2 Data 3: BCB3 * R, G, B, 16 kinds each; selection of 1 color from 4096 Data 4 to data 8: Fixed at 0 7. Control item code 60HEX: Chroma key color (R, G) settings Default: MSB [00000000] LSB Data 0: CKR0 Chroma key color: R setting = 16 kinds Data 1: CKR1 Data 2: CKR2 Data 3: CKR3 Data 4: CKG0 Chroma key color: G setting = 16 kinds Data 5: CKG1 Data 6: CKG2 Data 7: CKG3 No. 5521-19/22 LC7874E 8. Control item code 70HEX: Chroma key color (B) setting Default: MSB [00000000] LSB Data 0: CKB0 Chroma key color: B setting = 16 kinds Data 1: CKB1 Data 3: CKB3 * R, G, B, 16 kinds each; selection of 1 color from 4096 Data 4 to data 8: Fixed at 0 9. Control item code 80HEX: YS signal output/video signal output phase adjustment data setting Default: MSB [00000000] LSB Data 0: YT0 YS signal output/video signal output phase adjustment data Data 1: YT1 Data 2: YT2 Data 3: YT3 Data 4: YT4 Data 5: Fixed at 0 Data 6: PAL60 PAL/PAL60 setting (valid only when N/P = 1) 0: PAL 1: PAL60 Data 7: CSYSEL CSYNC output addressing (autonomous mode only) 0: Equalization pulses used 1: No equalization pulses 10. Control item code 90HEX: External synchronization control, test mode setting Default: MSB [00000000] LSB Data 0: TST0 Test mode addressing (normally fixed low) Data 1: TST1 Data 2: TST2 Data 3: Fixed at 0 Data 4: HVMK HRESET, VRESET mask 0: Mask used 1: No mask Data 5: EXSN Sync signal rest control setting when using external clock (when SON = 1) 0: Reset executed with HRESET (pin 54) and VRESET (pin 56) signals 0: Reset executed with VRESET (pin 56) signal (HRESET signal unnecessary) Data 6: MVMD Moving display area setting 0: Movement of display area only 1: Border area included in movement (only horizontal movement possible) Data 7: CVSEL CSYNC output pin setting 0: CSYNC output 1: VSYNC output 11. Control item code A0HEX: Superimposed text scroll amount, vertical setting Default: MSB [00000000] LSB Data 0: SCV0 Upward scroll amount (font unit) setting (scroll amount: 0 to 17 font units) Data 1: SCV1 Screen display position scrolled vertically by 1 font unit Data 2: SCV2 (1 font unit: 12 vertical dots (12H)) Data 3: SCV3 Data 4: SCV4 Data 5 to data 7: Fixed at 0 No. 5521-20/22 LC7874E 12. Control item code C0HEX: Superimposed text scroll amount, horizontal setting Default: MSB [00000000] LSB Data 0: SCH0 Left scroll amount (font unit) setting (scroll amount: 0 to 49-font units) Data 1: SCH1 Screen display position scrolled horizontally in 1-font unit Data 2: SCH2 (1-font unit: 6 horizontal dots) Data 3: SCH3 Data 4: SCH4 Data 5: SCH5 Data 6, data 7: Fixed at 0 13. Control item code 01HEX: 19-byte command input (MGC write) Transfer format ① Address: F4HEX ② Control item: 01HEX ③ sym0 to sym19: R to W = subcode input ④ Executed on fall 14. Control item code 11HEX: 19-byte command input (pack data read) Transfer format ① Address: F5HEX ② Data (check flags) MSB [PF1, PF0, QF1, QF0, DKMD, VBLK, EXEC, OE] :LSB Data 0: OE 1 when the next 18 bytes are guaranteed and are the first data to be read. * Note: Reading must be completed within 1.1 ms after OE output setting. Data 1: EXEC Command status 0: Command executing 1: Command wait state Data 2: VBLK 1 output during vertical blanking (vertical retrace line) period Vertical retrace line period NTSC: 19H PAL: 25H Data 3: DKMD Disk identification flag 0: CD 1: CD-G No. 5521-21/22 LC7874E Data 4: Data 5: Data 6: Data 7: QF0 QF1 PF0 PF1 QF0 error correction Q flag data QF1 error correction Q flag data PF0 error correction P flag data PF1 error correction Q flag data ③ sym0, 1, 4 to 19: R to W = subcode input MSB [R, S, T, U, V, W, 0, 0] LSB Sample Application Circuit : NTSC ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1997. Specifications and information herein are subject to change without notice. No. 5521-22/22