STK14C88-5 256 Kbit (32 K x 8) AutoStore nvSRAM Features Functional Description ■ 35 ns and 45 ns access times ■ Hands off automatic STORE on power down with external 68 µF capacitor ■ STORE to QuantumTrap™ nonvolatile elements is initiated by software, hardware, or AutoStore™ on power down ■ RECALL to SRAM initiated by software or power up ■ Unlimited READ, WRITE, and RECALL cycles ■ 1,000,000 STORE cycles to QuantumTrap ■ 100 year data retention to QuantumTrap ■ Single 5 V + 10% operation ■ Military temperature ■ 32-pin (300 mil) CDIP and LCC (450 mil) packages The Cypress STK14C88-5 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin. For a complete list of related documentation, click here. Logic Block Diagram VCC Quantum Trap 512 X 512 A5 STATIC RAM ARRAY 512 X 512 DQ 4 DQ 5 DQ 6 STORE/ RECALL CONTROL HSB A13 - A 0 COLUMN I/O COLUMN DEC INPUT BUFFERS DQ 2 DQ 3 RECALL SOFTWARE DETECT DQ 0 DQ 1 POWER CONTROL STORE ROW DECODER A6 A7 A8 A9 A 11 A 12 A 13 A 14 VCAP A 0 A 1 A 2 A 3 A 4 A 10 DQ 7 OE CE WE Cypress Semiconductor Corporation Document Number: 001-51038 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 14, 2014 STK14C88-5 Pin Configurations Figure 1. Pin Diagram: 32-Pin DIP Figure 1. Pin Diagram: 32-Pin LCC Pin Definitions Pin Name Alt A0–A14 IO Type Input DQ0-DQ7 Description Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. WE W Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. CE E Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. G Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. OE VSS Ground Ground for the Device. The device is connected to ground of the system. VCC Power Supply Power Supply Inputs to the Device. HSB Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected (connection optional). VCAP Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Document Number: 001-51038 Rev. *C Page 2 of 18 STK14C88-5 Contents Device Operation .............................................................. 4 SRAM Read ....................................................................... 4 SRAM Write ....................................................................... 4 AutoStore Operation ........................................................ 4 AutoStore Inhibit Mode .................................................... 4 Hardware STORE (HSB) Operation ................................. 5 Hardware RECALL (Power Up) ........................................ 5 Software STORE ............................................................... 5 Software RECALL ............................................................. 5 Data Protection ................................................................. 6 Noise Considerations ....................................................... 6 Hardware Protect .............................................................. 6 Low Average Active Power .............................................. 6 Preventing Store ............................................................... 6 Best Practices ................................................................... 7 Maximum Ratings ............................................................. 8 Operating Range ............................................................... 8 DC Electrical Characteristics .......................................... 8 Data Retention and Endurance ....................................... 8 Document Number: 001-51038 Rev. *C Capacitance ...................................................................... 9 Thermal Resistance .......................................................... 9 AC Test Conditions .......................................................... 9 SRAM Read Cycle .................................................... 10 SRAM Write Cycle ..................................................... 11 AutoStore or Power Up RECALL .................................. 12 Software Controlled STORE/RECALL Cycle ................ 13 Switching Waveforms .................................................... 14 Part Numbering Nomenclature ...................................... 15 Ordering Information ...................................................... 15 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 Page 3 of 18 STK14C88-5 Device Operation The STK14C88-5 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The STK14C88-5 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. having a capacitor of between 68 F and 220 F (+ 20%) rated at 6 V should be provided. The voltage on the VCAP pin is driven to 5 V by a charge pump internal to the chip. A pull-up is placed on WE to hold it inactive during power up. Figure 3. AutoStore Mode SRAM Read The STK14C88-5 performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0–14 determines the 32,768 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM Write A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–7 are written into the memory if it has valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore Operation The STK14C88-5 stores data to nvSRAM using one of three storage operations: 1. Hardware store activated by HSB 2. Software store activated by an address sequence 3. AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK14C88-5. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. In system power mode, both VCC and VCAP are connected to the +5 V power supply without the 68 F capacitor. In this mode, the AutoStore function of the STK14C88-5 operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6 V during the 10 ms STORE cycle. To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored, unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. An optional pull-up resistor is shown connected to HSB. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. If the power supply drops faster than 20 s/volt before VCC reaches VSWITCH, then a 2.2 resistor should be connected between VCC and the system supply to avoid momentary excess of current between VCC and VCAP. AutoStore Inhibit Mode If an automatic STORE on power loss is not required, then VCC is tied to ground and + 5 V is applied to VCAP (Figure 4). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK14C88-5 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered through software control or the HSB pin. To enable or disable Autostore using an I/O port pin see “Preventing Store” on page 6. It is not permissible to change between these three options” on the fly”. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor Document Number: 001-51038 Rev. *C Page 4 of 18 STK14C88-5 Figure 4. AutoStore Inhibit Mode If the STK14C88-5 is in a WRITE state at the end of power-up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 k resistor is connected either between WE and system VCC or between CE and system VCC. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14C88-5 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. Hardware STORE (HSB) Operation The STK14C88-5 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the STK14C88-5 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. Pull up this pin with an external 10 k resistor to VCAP if HSB is used as a driver. SRAM READ and WRITE operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the STK14C88-5 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations take place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. During any STORE operation, regardless of how it is initiated, the STK14C88-5 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK14C88-5 remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected. Hardware RECALL (Power Up) During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. Document Number: 001-51038 Rev. *C To initiate the software STORE cycle, the following READ sequence is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0FC0, Initiate STORE cycle The software sequence is clocked with CE controlled READs. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0C63, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. Page 5 of 18 STK14C88-5 Data Protection Figure 5. Current Versus Cycle Time (READ) The STK14C88-5 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low-voltage condition is detected when VCC is less than VSWITCH. If the STK14C88-5 is in a WRITE mode (both CE and WE are low) at power up after a RECALL or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions. Noise Considerations The STK14C88-5 is a high-speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise. Figure 6. Current Versus Cycle Time (WRITE) Hardware Protect The STK14C88-5 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCAP<VSWITCH, all externally initiated STORE operations and SRAM WRITEs are inhibited. AutoStore can be completely disabled by tying VCC to ground and applying + 5 V to VCAP. This is the AutoStore Inhibit mode; in this mode, STOREs are only initiated by explicit request using either the software sequence or the HSB pin. Low Average Active Power CMOS technology provides the STK14C88-5 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 5 and Figure 6 shows the relationship between ICC and READ or WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5 V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14C88-5 depends on the following items: ■ The duty cycle of chip enable ■ The overall cycle rate for accesses ■ The ratio of READs to WRITEs ■ CMOS versus TTL input levels ■ The operating temperature ■ The VCC level ■ I/O loading Document Number: 001-51038 Rev. *C Preventing Store The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2 V, because it has to overpower the internal pull-down device. This device drives HSB LOW for 20 s at the onset of a STORE. When the STK14C88-5 is connected for AutoStore operation (system VCC connected to VCC and a 68 F capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK14C88-5 attempts to pull HSB LOW. If HSB does not actually get below VIL, the part stops trying to pull HSB LOW and abort the STORE attempt. Page 6 of 18 STK14C88-5 Best Practices manufacturing test to ensure these system routines work consistently. nvSRAM products have been used effectively for over 15 years. While ease of use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system ■ Power-up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). ■ The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the higher inrush currents may reduce the reliability of the internal pass transistor. Customers that want to use a larger VCAP value to make sure there is extra store charge should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period. Table 1. Hardware Mode Selection CE WE HSB A13–A0 Mode IO Power H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Active[1] L L H X Write SRAM Input Data Active X X L X Nonvolatile STORE Output High Z ICC2[2] L H H 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z Active ICC2[1, 3, 4, 5] L H H 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z Active[1, 3, 4, 5] Notes 1. I/O state assumes OE < VIL. Activation of nonvolatile cycles does not depend on state of OE. 2. HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part goes into standby mode, inhibiting all operations until HSB rises. 3. CE and OE LOW and WE HIGH for output behavior. 4. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle. 5. While there are 15 addresses on the STK14C88-5, only the lower 14 are used to control software modes. Document Number: 001-51038 Rev. *C Page 7 of 18 STK14C88-5 Maximum Ratings Voltage on DQ0-7 or HSB .................... –0.5 V to VCC + 0.5 V Power Dissipation......................................................... 1.0 W Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. DC output Current (1 output at a time, 1s duration) .... 15 mA Storage Temperature ............................... –65 C to +150 C Operating Range Temperature under Bias ........................... –55 C to +125 C Range Voltage on Input Relative to GND...................–0.5 V to 7.0 V Military Voltage on Input Relative to VSS ......... –0.6 V to VCC + 0.5 V Ambient Temperature VCC –55 C to +125 C 4.5 V to 5.5 V DC Electrical Characteristics Over the operating range (VCC = 4.5 V to 5.5 V) [6] Parameter Description Test Conditions Min Max Unit ICC1 Average VCC vurrent tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. IOUT = 0 mA. – 85 70 mA mA ICC2 Average VCC current during STORE All Inputs Do Not Care, VCC = Max Average current for duration tSTORE – 3 mA ICC3 Average VCC current at tRC= 200 ns, 5 V, 25 °C Typical WE > (VCC – 0.2 V). All other inputs cycling. Dependent on output loading and cycle rate. Values obtained without output loads. – 10 mA ICC4 Average VCAP current during AutoStore cycle All Inputs Do Not Care, VCC = Max Average current for duration tSTORE – 2 mA ISB1[7] VCC standby current (Standby, Cycling TTL Input Levels) tRC = 35 ns, CE > VIH tRC = 45 ns, CE > VIH – 26 23 mA mA ISB2 [7] VCC standby current CE > (VCC – 0.2 V). All others VIN < 0.2 V or > (VCC – 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. – 1.5 mA IIX Input leakage current VCC = Max, VSS < VIN < VCC –1 +1 A IOZ Off state output leakage current VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL –5 +5 A VIH Input HIGH voltage 2.2 VCC + 0.5 V VIL Input LOW voltage VSS – 0.5 0.8 V VOH Output HIGH voltage IOUT = –4 mA 2.4 – V VOL Output LOW voltage IOUT = 8 mA – 0.4 V VBL Logic ‘0’ voltage on HSB output IOUT = 3 mA – 0.4 V VCAP Storage capacitor Between VCAP pin and VSS, 6 V rated. 68 µF +20% nominal 54 260 uF Data Retention and Endurance Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 100 Years 1,000 K Notes 6. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. 7. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out. Document Number: 001-51038 Rev. *C Page 8 of 18 STK14C88-5 Capacitance In the following table, the capacitance parameters are listed.[8] Parameter Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 0 to 3.0 V Max Unit 5 pF 7 pF Thermal Resistance In the following table, the thermal resistance parameters are listed.[8] Parameter Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 32-CDIP 32-LCC Unit TBD TBD C/W TBD TBD C/W Figure 7. AC Test Loads R1 963 For Tristate Specs R1 963 5.0 V 5.0 V Output Output 30 pF R2 512 5 pF R2 512 AC Test Conditions Input Pulse Levels .................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)........................ <5 ns Input and Output Timing Reference Levels ................... 1.5 V Note 8. These parameters are guaranteed by design and are not tested. Document Number: 001-51038 Rev. *C Page 9 of 18 STK14C88-5 AC Switching Characteristics SRAM Read Cycle Parameter Cypress Parameter tACE 35 ns Description Alt 45 ns Min Max Min Max Unit tELQV Chip enable access time – 35 – 45 ns tAVAV, tELEH Read cycle time 35 – 45 – ns tAA [10] tAVQV Address access time – 35 – 45 ns tDOE tGLQV Output enable to data valid – 15 – 20 ns tRC [9] tAXQX Output hold after address change 5 – 5 – ns tLZCE [11] tELQX Chip enable to output active 5 – 5 – ns tHZCE [11] tEHQZ Chip disable to output inactive – 13 – 15 ns tLZOE [11] tGLQX Output enable to output active 0 – 0 – ns tHZOE [11] tOHA [10] tGHQZ Output disable to output inactive – 13 – 15 ns tPU [12] tELICCH Chip enable to power active 0 – 0 – ns tPD [12] tEHICCL Chip Disable to power standby – 35 – 45 ns Switching Waveforms Figure 8. SRAM Read Cycle 1: Address Controlled [9, 10] tRC ADDRESS t AA tOHA DQ (DATA OUT) DATA VALID Figure 9. SRAM Read Cycle 2: CE and OE Controlled [9] tRC ADDRESS tLZCE CE tACE tPD tHZCE OE tLZOE DQ (DATA OUT) t PU ICC tHZOE tDOE DATA VALID ACTIVE STANDBY Notes 9. WE and HSB must be HIGH during SRAM Read cycles. 10. Device is continuously selected with CE and OE both Low. 11. Measured ±200 mV from steady state output voltage. 12. These parameters are guaranteed by design and are not tested. Document Number: 001-51038 Rev. *C Page 10 of 18 STK14C88-5 SRAM Write Cycle Parameter Cypress Alt Parameter tAVAV tWC tPWE tWLWH, tWLEH tELWH, tELEH tSCE tDVWH, tDVEH tSD tHD tWHDX, tEHDX tAVWH, tAVEH tAW tAVWL, tAVEL tSA tHA tWHAX, tEHAX tWLQZ tHZWE [13,14] tWHQX tLZWE [13] 35 ns Description 45 ns Unit Min Max Min Max Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable 35 25 25 12 0 25 0 0 – – – – – – – – – 13 45 30 30 15 0 30 0 0 – – – – – – – – – 15 ns ns ns ns ns ns ns ns ns Output active after end of write 5 – 5 – ns Switching Waveforms Figure 10. SRAM Write Cycle 1: WE Controlled [15, 16] tWC ADDRESS tHA tSCE CE tAW tSA tPWE WE tSD tHD DATA VALID DATA IN tHZWE DATA OUT tLZWE HIGH IMPEDANCE PREVIOUS DATA Figure 11. SRAM Write Cycle 2: CE Controlled [15, 16] tWC ADDRESS CE WE tHA tSCE tSA tAW tPWE tSD DATA IN DATA OUT tHD DATA VALID HIGH IMPEDANCE Notes 13. Measured ±200 mV from steady state output voltage. 14. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 15. HSB must be high during SRAM WRITE cycles. 16. CE or WE must be greater than VIH during address transitions. Document Number: 001-51038 Rev. *C Page 11 of 18 STK14C88-5 AutoStore or Power Up RECALL Parameter Alt Description STK14C88-5 Min Max Unit tHRECALL [17] tRESTORE Power up RECALL duration – 550 s tSTORE [18] tHLHZ STORE cycle duration – 10 ms tDELAY [18] tHLQZ , tBLQZ Time allowed to complete SRAM cycle 1 – s 4.0 4.5 V VSWITCH Low voltage trigger level VRESET Low voltage reset level tVCCRISE VCC rise time tVSBL[19] Low voltage trigger (VSWITCH) to HSB low – 3.6 V 150 – s – 300 ns Switching Waveforms Figure 12. AutoStore/Power Up RECALL WE Notes 17. tHRECALL starts from the time VCC rises above VSWITCH. 18. CE and OE low and WE high for output behavior. 19. HSB is asserted low for 1 s when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB is released and no store takes place. Document Number: 001-51038 Rev. *C Page 12 of 18 STK14C88-5 Software Controlled STORE/RECALL Cycle The software controlled STORE/RECALL cycle follows. [22] Parameter Alt Description 35 ns 45 ns Min Max Min Max Unit tRC[20] tAVAV STORE/RECALL initiation cycle time 35 – 45 – ns tSA[21, 22] tCW[21, 22] tHACE[21, 22] tAVEL Address setup time 0 – 0 – ns tELEH Clock pulse width 25 – 30 – ns tELAX Address hold time 20 – 20 – ns RECALL duration – 20 – 20 s tRECALL Switching Waveforms Figure 13. CE Controlled Software STORE/RECALL Cycle [22] tRC ADDRESS # 1 ADDRESS tSA tRC ADDRESS # 6 tSCE CE tHACE OE t STORE / t RECALL DQ (DATA) DATA VALID DATA VALID HIGH IMPEDANCE Notes 20. CE and OE low and WE high for output behavior. 21. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence). 22. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles. Document Number: 001-51038 Rev. *C Page 13 of 18 STK14C88-5 Hardware STORE Cycle Parameter Alt Description STK14C88-5 Min Max Unit tDHSB [23, 24] tRECOVER, tHHQX Hardware STORE High to inhibit Off – 700 ns tPHSB tHLHX Hardware STORE pulse width 15 – ns Hardware STORE Low to STORE busy – 300 ns tHLBL Switching Waveforms Figure 14. Hardware STORE Cycle Note 23. CE and OE low and WE high for output behavior. 24. tDHSB is only applicable after tSTORE is complete. Document Number: 001-51038 Rev. *C Page 14 of 18 STK14C88-5 Part Numbering Nomenclature STK14C88 - 5 C 35 M Temperature Range: M - Military (–55 °C to 125 °C) Speed: 35 - 35 ns 45 - 45 ns Package: C = Ceramic 32-pin 300 mil DIP K = Ceramic 32-pin 300 mil DIP (Solder dip finish) L = Ceramic 32-pin LLC Retention / Endurance 5 = Military (10 years or 105 cycles) Ordering Information Speed (ns) 45 Ordering Code Package Diagram Package Type STK14C88-5L35M 51-80068 32-pin LCC (450 mil) STK14C88-5K45M 001-51694 32-pin CDIP (300 mil) STK14C88-5L45M 51-80068 32-pin LCC (450mil) Operating Range Military The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts Document Number: 001-51038 Rev. *C Page 15 of 18 STK14C88-5 Package Diagram Figure 15. 32-Pin (300-Mil) Side Braze DIL (001-51694) 001-51694 *B Document Number: 001-51038 Rev. *C Page 16 of 18 STK14C88-5 Package Diagram (continued) Figure 16. 32-Pad (450-Mil) LCC (51-80068) 51-80068 *C Acronyms Document Conventions Acronym Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C degrees Celsius I/O input/output k kilohm nvSRAM nonvolatile static random access memory A microampere OE output enable mA milliampere SRAM static random access memory F microfarad TTL transistor-transistor logic s microsecond WE write enable ms millisecond Document Number: 001-51038 Rev. *C Symbol Unit of Measure ns nanosecond pF picofarad V volt ohm W watt Page 17 of 18 STK14C88-5 Document History Page Document Title: STK14C88-5 256 Kbit (32 K x 8) AutoStore nvSRAM Document Number: 001-51038 Rev ECN No. Orig. of Change Submission Date ** 2666844 GVCH/PYRS 03/02/2009 New datasheet *A 3054310 GVCH/KEER 10/11/2010 Removed the inactive part, STK14C88-5C35M. Updated the Package diagrams. *B 3528678 GVCH 02/17/2012 Added Acronyms, Document Conventions, and Table of Contents. Updated Package Diagrams 51-80068 (from Rev *A to *B). Completing sunset review. *C 4568935 GVCH 11/14/2014 Added documentation related hyperlink in page 1 Removed 02 pruned parts - STK14C88-5K35M, STK14C88-5C45M Updated package diagram from 001-51694*A to 001-51694*B, 51-80068*A to 51-80068*B Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-51038 Rev. *C Revised November 14, 2014 Page 18 of 18 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.