CY14B108L CY14B108N 8-Mbit (1024 K × 8/512 K × 16) nvSRAM 8-Mbit (1024 K × 8/512 K × 16) nvSRAM Features ■ Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS) compliant ■ 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 1024 K × 8 (CY14B108L) or 512 K ×16 (CY14B108N) ■ ■ Hands off automatic STORE on power-down with only a small capacitor Functional Description ■ STORE to QuantumTrap nonvolatile elements initiated by software, device pin, or AutoStore on power-down ■ RECALL to SRAM initiated by software or power-up ■ Infinite Read, Write, and RECALL cycles ■ 1 million STORE cycles to QuantumTrap ■ 20 year data retention ■ Single 3 V +20, –10 operation ■ Industrial temperature The Cypress CY14B108L/CY14B108N is a fast static RAM (SRAM), with a nonvolatile element in each memory cell. The memory is organized as 1024 Kbytes of 8 bits each or 512 K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. For a complete list of related documentation, click here. Logic Block Diagram [1, 2, 3] Quatrum Trap 2048 X 2048 X 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A17 A18 A19 R O W STORE VCC VCAP POWER CONTROL RECALL D E C O D E R STATIC RAM ARRAY 2048 X 2048 X 2 STORE/RECALL CONTROL SOFTWARE DETECT HSB A14 - A2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 I N P U T B U F F E R S COLUMN I/O OE COLUMN DEC WE DQ12 DQ13 CE DQ14 BLE A9 A10 A11 A12 A13 A14 A15 A16 DQ15 BHE Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 24. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Notes 1. Address A0–A19 for × 8 configuration and Address A0–A18 for × 16 configuration. 2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 3. BHE and BLE are applicable for × 16 configuration only. Cypress Semiconductor Corporation Document Number: 001-45523 Rev. *O • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 8, 2015 CY14B108L CY14B108N Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 4 Device Operation .............................................................. 5 SRAM Read ................................................................ 5 SRAM Write ................................................................. 5 AutoStore Operation .................................................... 5 Hardware STORE Operation ....................................... 5 Hardware RECALL (Power-Up) .................................. 6 Software STORE ......................................................... 6 Software RECALL ....................................................... 6 Preventing AutoStore .................................................. 8 Data Protection ............................................................ 8 Maximum Ratings ............................................................. 9 Operating Range ............................................................... 9 DC Electrical Characteristics .......................................... 9 Data Retention and Endurance ..................................... 10 Capacitance .................................................................... 10 Thermal Resistance ........................................................ 10 AC Test Loads ................................................................ 11 AC Test Conditions ........................................................ 11 AC Switching Characteristics ....................................... 12 Switching Waveforms .................................................... 12 AutoStore/Power-Up RECALL ....................................... 15 Switching Waveforms .................................................... 15 Document Number: 001-45523 Rev. *O Software Controlled STORE/RECALL Cycle ................ 16 Switching Waveforms .................................................... 16 Hardware STORE Cycle ................................................. 17 Switching Waveforms .................................................... 17 Truth Table For SRAM Operations ................................ 18 Ordering Information ...................................................... 19 Ordering Code Definitions ......................................... 19 Package Diagrams .......................................................... 20 Acronyms ........................................................................ 23 Document Conventions ................................................. 23 Units of Measure ....................................................... 23 Errata ............................................................................... 24 Part Numbers Affected .............................................. 24 8Mb (1024 K × 8, 512 K × 16) nvSRAM Qualification Status ........................................................... 24 8Mb (1024 K × 8, 512 K × 16) nvSRAM Errata Summary ............................................................... 24 Document History Page ................................................. 25 Sales, Solutions, and Legal Information ...................... 27 Worldwide Sales and Design Support ....................... 27 Products .................................................................... 27 PSoC® Solutions ...................................................... 27 Cypress Developer Community ................................. 27 Technical Support ..................................................... 27 Page 2 of 27 CY14B108L CY14B108N Pinouts Figure 1. Pin Diagram – 48-ball FBGA (× 8) Top View (not to scale) (× 16) Top View (not to scale) 1 2 3 4 5 6 A BLE OE A0 A1 A2 NC A NC B DQ8 BHE A3 A4 CE DQ0 B NC DQ4 C DQ9 DQ10 A5 A6 DQ1 DQ2 C A7 DQ5 VCC D VSS A17 A7 DQ3 VCC D 2 3 4 5 6 NC OE A0 A1 A2 NC NC NC A3 A4 CE DQ0 NC A5 A6 VSS DQ1 A17 1 DQ11 VCC DQ2 VCAP A16 DQ6 VSS E VCC DQ12 VCAP A16 DQ4 VSS E DQ3 NC A14 A15 NC DQ7 F DQ14 DQ13 A14 A15 DQ5 DQ6 F NC HSB A12 A13 WE NC G DQ15 HSB A12 A13 WE DQ7 G A18 A8 A9 A10 A11 A19 H A9 A10 A11 NC H A18 A8 Figure 2. Pin Diagram – 44/54-pin TSOP II 44-pin TSOP II (× 8) NC [4] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Top View (not to scale) 54-pin TSOP II (× 16) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 HSB NC A19 A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 30 29 28 27 26 25 24 23 VCAP A14 A13 A12 A11 A10 NC NC NC [4] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 Top View (not to scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB A18 A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC Note 4. Address expansion for 16-Mbit. NC pin not connected to die. Document Number: 001-45523 Rev. *O Page 3 of 27 CY14B108L CY14B108N Pin Definitions Pin Name I/O Type A0–A19 Input A0–A18 Description Address inputs. Used to select one of the 1,048,576 bytes of the nvSRAM for × 8 configuration. Address inputs. Used to select one of the 524,288 words of the nvSRAM for × 16 configuration. DQ0–DQ7 Input/Output Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation. DQ0–DQ15 Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation. WE Input Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location. CE Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tristated on deasserting OE HIGH. BHE Input Byte High Enable, Active LOW. Controls DQ15–DQ8. BLE Input Byte Low Enable, Active LOW. Controls DQ7–DQ0. VSS Ground Ground for the device. Must be connected to the ground of the system. VCC Power supply Power supply inputs to the device. HSB Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional). VCAP Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. NC No connect No connect. This pin is not connected to the die. Document Number: 001-45523 Rev. *O Page 4 of 27 CY14B108L CY14B108N The CY14B108L/CY14B108N nvSRAM is made up of two functional components paired in the same physical cell. They are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14B108L/CY14B108N supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations. See Truth Table For SRAM Operations on page 18 for a complete description of read and write modes. SRAM Read The CY14B108L/CY14B108N performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0–19 or A0–18 determines which of the 1,048,576 data bytes or 524,288 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. AutoStore on page 8. In case AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This corrupts the data stored in nvSRAM. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 9 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull-up should be placed on WE to hold it inactive during power-up. This pull-up is effective only if the WE signal is tristate during power-up. Many MPUs tristate their controls on power-up. This should be verified when using the pull-up. When the nvSRAM comes out of power-on-RECALL, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 3. AutoStore Mode VCC 0.1 uF 10 kOhm Device Operation VCC SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–15 are written into the memory if the data is valid tSD before the end of a WE controlled write or before the end of an CE controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore Operation The CY14B108L/CY14B108N stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by the HSB; Software STORE activated by an address sequence; AutoStore on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B108L/CY14B108N. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing Document Number: 001-45523 Rev. *O WE VCAP VSS VCAP Hardware STORE Operation The CY14B108L/CY14B108N provides the HSB pin to control and acknowledge the STORE operations. Use the HSB pin to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14B108L/CY14B108N conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor. Page 5 of 27 CY14B108L CY14B108N SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B108L/CY14B108N. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14B108L/CY14B108N continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power-Up) During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on power-up, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B108L/CY14B108N Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. Document Number: 001-45523 Rev. *O To initiate the Software STORE cycle, the following read sequence must be performed. 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE or OE controlled read operations must be performed. 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements. Page 6 of 27 CY14B108L CY14B108N Table 1. Mode Selection CE WE OE BHE, BLE[5] A15–A0[6] Mode I/O Power H X X X X Not Selected Output High Z Standby L H L L X Read SRAM Output data Active L L X L X Write SRAM Input data Active L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output data Output data Output data Output data Output data Output data Active[7] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output data Output data Output data Output data Output data Output data Active[7] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output data Output data Output data Output data Output data Output High Z Active ICC2[7] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output data Output data Output data Output data Output data Output High Z Active[7] Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 24. Notes 5. BHE and BLE are applicable for × 16 configuration only. 6. While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A14–A2) are used to control software modes. Rest of the address lines are don’t care. 7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. Document Number: 001-45523 Rev. *O Page 7 of 27 CY14B108L CY14B108N Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable Note Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 24. The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the Software RECALL initiation. To initiate the Document Number: 001-45523 Rev. *O AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled and 0x00 written in all cells. Data Protection The CY14B108L/CY14B108N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B108L/CY14B108N is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions. Page 8 of 27 CY14B108L CY14B108N Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Maximum accumulated storage time Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount Pb soldering temperature (3 Seconds) ......................................... +260 C At 150 C ambient temperature ...................... 1000 h DC output current (1 output at a time, 1s duration) .... 15 mA At 85 C ambient temperature ..................... 20 Years Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Maximum junction temperature .................................. 150 C Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V Voltage applied to outputs in High Z state .................................... –0.5 V to VCC + 0.5 V Input voltage ........................................–0.5 V to Vcc + 0.5 V Latch up current .................................................... > 200 mA Operating Range Range Ambient Temperature VCC –40 C to +85 C 2.7 V to 3.6 V Industrial DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ [8] Max Unit 2.7 3.0 3.6 V VCC Power supply ICC1 Average VCC current tRC = 20 ns tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) – – 75 75 57 mA mA mA ICC2 Average VCC current during STORE All inputs don’t care, VCC = Max Average current for duration tSTORE – – 20 mA ICC3 Average VCC current at tRC= 200 ns, VCC(Typ), 25 °C All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA). – 40 – mA ICC4 Average VCAP current during AutoStore cycle All inputs don’t care. Average current for duration tSTORE – – 10 mA ISB VCC standby current CE > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. – – 10 mA IIX[9] Input leakage current (except HSB) VCC = Max, VSS < VIN < VCC –2 – +2 A Input leakage current (for HSB) VCC = Max, VSS < VIN < VCC –200 – +2 A IOZ Off-state output leakage current VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH or WE < VIL –2 – +2 A VIH Input HIGH voltage 2.0 – VCC + 0.5 V VIL Input LOW voltage Vss – 0.5 – 0.8 V VOH Output HIGH voltage IOUT = –2 mA 2.4 – – V VOL Output LOW voltage IOUT = 4 mA – – 0.4 V Notes 8. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested. 9. The HSB pin has IOUT = –2 µA for VOH of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. Document Number: 001-45523 Rev. *O Page 9 of 27 CY14B108L CY14B108N DC Electrical Characteristics (continued) Over the Operating Range Parameter Description VCAP[10] VVCAP[11, 12] Storage capacitor Test Conditions Min Typ [8] Between VCAP pin and VSS 122 – Maximum voltage driven on VCAP VCC = Max pin by the device Max Unit 150 360 F – VCC V Data Retention and Endurance Over the Operating Range Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 20 Years 1,000 K Max Unit Capacitance Parameter [12] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(Typ) 14 pF 14 pF Thermal Resistance Parameter [12] Description JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 48-ball FBGA 44-pin TSOP II 54-pin TSOP II Unit 42.2 45.3 44.22 C/W 6.3 5.2 8.26 C/W Notes 10. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options. 11. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating temperature range should be higher than the VVCAP voltage. 12. These parameters are guaranteed by design and are not tested. Document Number: 001-45523 Rev. *O Page 10 of 27 CY14B108L CY14B108N AC Test Loads Figure 4. AC Test Loads 577 3.0 V 577 3.0 V R1 for tristate specs R1 OUTPUT OUTPUT 30 pF R2 789 5 pF R2 789 AC Test Conditions Input pulse levels .................................................. 0 V to 3 V Input rise and fall times (10%–90%) ........................... < 3 ns Input and output timing reference levels ...................... 1.5 V Document Number: 001-45523 Rev. *O Page 11 of 27 CY14B108L CY14B108N AC Switching Characteristics Over the Operating Range Parameters [13] Cypress Alt Parameter Parameter SRAM Read Cycle tACE tACS tRC tRC[14] tAA[15] tAA tOE tDOE tOH tOHA[15] tLZCE[16, 17] tLZ tHZ tHZCE[16, 17] tOLZ tLZOE[16, 17] [16, 17] tHZOE tOHZ tPA tPU[16] tPS tPD[16] tDBE – – tLZBE[16] – tHZBE[16] SRAM Write Cycle tWC tWC tWP tPWE tSCE tCW tDW tSD tDH tHD tAW tAW tAS tSA tWR tHA tHZWE[16, 17, 18] tWZ tOW tLZWE[16, 17] – tBW 20 ns Description 25 ns 45 ns Unit Min Max Min Max Min Max Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Output disable to output inactive Chip enable to power active Chip disable to power standby Byte enable to data valid Byte enable to output active Byte disable to output inactive – 20 – – 3 3 – 0 – 0 – – 0 – 20 – 20 10 – – 8 – 8 – 20 10 – 8 – 25 – – 3 3 – 0 – 0 – – 0 – 25 – 25 12 – – 10 – 10 – 25 12 – 10 – 45 – – 3 3 – 0 – 0 – – 0 – 45 – 45 20 – – 15 – 15 – 45 20 – 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write Byte enable to end of write 20 15 15 8 0 15 0 0 – 3 15 – – – – – – – – 8 – – 25 20 20 10 0 20 0 0 – – – – – – – – 10 – – 45 30 30 15 0 30 0 0 – 3 30 – – – – – – – – 15 – – ns ns ns ns ns ns ns ns ns ns ns 3 20 Switching Waveforms Figure 5. SRAM Read Cycle #1 (Address Controlled) [14, 15, 19] tRC Address Address Valid tAA Data Output Previous Data Valid Output Data Valid tOHA Notes 13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 4 on page 11. 14. WE must be HIGH during SRAM read cycles. 15. Device is continuously selected with CE, OE and BHE / BLE LOW. 16. These parameters are guaranteed by design but not tested. 17. Measured ±200 mV from steady state output voltage. 18. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 19. HSB must remain HIGH during READ and WRITE cycles. Document Number: 001-45523 Rev. *O Page 12 of 27 CY14B108L CY14B108N Switching Waveforms (continued) Figure 6. SRAM Read Cycle #2 (CE and OE Controlled) [20, 21, 22] Address Address Valid tRC tHZCE tACE CE tAA tLZCE tHZOE tDOE OE tHZBE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance Output Data Valid tPU ICC tPD Active Standby Figure 7. SRAM Write Cycle #1 (WE Controlled) [20, 22, 23, 24] tWC Address Address Valid tSCE tHA CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input Input Data Valid tHZWE Data Output tHD Previous Data tLZWE High Impedance Notes 20. BHE and BLE are applicable for × 16 configuration only. 21. WE must be HIGH during SRAM read cycles. 22. HSB must remain HIGH during READ and WRITE cycles. 23. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 24. CE or WE must be >VIH during address transitions. Document Number: 001-45523 Rev. *O Page 13 of 27 CY14B108L CY14B108N Switching Waveforms (continued) Figure 8. SRAM Write Cycle #2 (CE Controlled) [25, 26, 27, 28] tWC Address Valid Address tSA tSCE tHA CE tBW BHE, BLE tPWE WE tHD tSD Input Data Valid Data Input High Impedance Data Output Figure 9. SRAM Write Cycle #3 (BHE and BLE Controlled) [25, 26, 27, 28] tWC Address Address Valid tSCE CE tSA tHA tBW BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output Notes 25. BHE and BLE are applicable for × 16 configuration only. 26. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 27. HSB must remain HIGH during READ and WRITE cycles. 28. CE or WE must be >VIH during address transitions. Document Number: 001-45523 Rev. *O Page 14 of 27 CY14B108L CY14B108N AutoStore/Power-Up RECALL Over the Operating Range Parameter 20 ns Description 25 ns 45 ns Min Max Min Max Min Max Unit tHRECALL[29] Power-Up RECALL duration – 20 – 20 – 20 ms tSTORE [30] STORE cycle duration – 8 – 8 – 8 ms Time allowed to complete SRAM write cycle – 20 – 25 – 25 ns tDELAY [31] VSWITCH Low voltage trigger level tVCCRISE[32] VCC rise time – 2.65 – 2.65 – 2.65 V 150 – 150 – 150 – s VHDIS[32] tLZHSB[32] HSB output disable voltage – 1.9 – 1.9 – 1.9 V HSB to output active time – 5 – 5 – 5 s tHHHD[32] HSB high active time – 500 – 500 – 500 ns Switching Waveforms Figure 10. AutoStore or Power-Up RECALL [33] VCC VSWITCH VHDIS t VCCRISE 30 tHHHD Note Note30 tSTORE tHHHD Note 34 tSTORE 34 Note HSB OUT tDELAY tLZHSB AutoStore tLZHSB tDELAY POWERUP RECALL tHRECALL tHRECALL Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write BROWN OUT AutoStore POWER-UP RECALL Read & Write POWER DOWN AutoStore Notes 29. tHRECALL starts from the time VCC rises above VSWITCH. 30. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 31. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 32. These parameters are guaranteed by design but not tested. 33. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 34. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document Number: 001-45523 Rev. *O Page 15 of 27 CY14B108L CY14B108N Software Controlled STORE/RECALL Cycle Over the Operating Range Parameter [35, 36] tRC tSA tCW tHA tRECALL Description Min 20 0 15 0 – STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration 20 ns Max – – – – 200 Min 25 0 20 0 – 25 ns Max – – – – 200 Min 45 0 30 0 – 45 ns Max – – – – 200 Unit ns ns ns ns s Switching Waveforms Figure 11. CE and OE Controlled Software STORE/RECALL Cycle [36] tRC Address tRC Address #1 tSA Address #6 tCW tCW CE tHA tSA tHA tHA tHA OE tHHHD HSB (STORE only) tHZCE tLZCE t DELAY 37 Note tLZHSB High Impedance tSTORE/tRECALL DQ (DATA) RWI Figure 12. Autostore Enable/Disable Cycle [36] Address tRC tRC Address #1 Address #6 tSA CE tCW tCW tHA tSA tHA tHA tHA OE tLZCE tHZCE tSS 37 Note t DELAY DQ (DATA) RWI Notes 35. The software sequence is clocked with CE controlled or OE controlled reads. 36. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles. 37. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time. Document Number: 001-45523 Rev. *O Page 16 of 27 CY14B108L CY14B108N Hardware STORE Cycle Over the Operating Range Parameter 20 ns Description 25 ns 45 ns Min Max Min Max Min Max Unit tDHSB HSB to output active time when write latch not set – 20 – 25 – 25 ns tPHSB Hardware STORE pulse width 15 – 15 – 15 – ns Soft sequence processing time – 100 – 100 – 100 s tSS [38, 39] Switching Waveforms Figure 13. Hardware STORE Cycle [40] Write latch set tPHSB HSB (IN) tSTORE tHHHD tDELAY HSB (OUT) tLZHSB DQ (Data Out) RWI Write latch not set tPHSB HSB pin is driven high to VCC only by Internal 100 kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. HSB (IN) HSB (OUT) tDELAY tDHSB tDHSB RWI Figure 14. Soft Sequence Processing [38, 39] Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 tSS Address #6 tCW CE VCC Notes 38. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 39. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 40. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. Document Number: 001-45523 Rev. *O Page 17 of 27 CY14B108L CY14B108N Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. Table 2. Truth Table for × 8 Configuration CE Inputs/Outputs[41] WE OE Mode Power H X X High Z Deselect/Power-down Standby L H L Data out (DQ0–DQ7); Read Active L H H High Z Output disabled Active L L X Data in (DQ0–DQ7); Write Active Table 3. Truth Table for × 16 Configuration BHE[42] BLE[42] Inputs/Outputs[41] CE WE OE Mode Power H X X X X High Z Deselect/Power-down Standby L X X H H High Z Output disabled Active L H L L L Data out (DQ0–DQ15) Read Active L H L H L Data out (DQ0–DQ7); DQ8–DQ15 in High Z Read Active L H L L H Data out (DQ8–DQ15); DQ0–DQ7 in High Z Read Active L H H L L High Z Output disabled Active L H H H L High Z Output disabled Active L H H L H High Z Output disabled Active L L X L L Data in (DQ0–DQ15) Write Active L L X H L Data in (DQ0–DQ7); DQ8–DQ15 in High Z Write Active L L X L H Data in (DQ8–DQ15); DQ0–DQ7 in High Z Write Active Notes 41. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 42. BHE and BLE are applicable for × 16 configuration only. Document Number: 001-45523 Rev. *O Page 18 of 27 CY14B108L CY14B108N Ordering Information Speed (ns) 20 25 45 Ordering Code Package Diagram Package Type CY14B108L-ZS20XIT 51-85087 44-pin TSOP II CY14B108L-ZS20XI 51-85087 44-pin TSOP II CY14B108L-ZS25XIT 51-85087 44-pin TSOP II CY14B108L-ZS25XI 51-85087 44-pin TSOP II CY14B108L-BA25XIT 51-85128 48-ball FBGA CY14B108L-BA25XI 51-85128 48-ball FBGA CY14B108N-BA25XIT 51-85128 48-ball FBGA CY14B108N-BA25XI 51-85128 48-ball FBGA CY14B108N-ZSP25XIT 51-85160 54-pin TSOP II CY14B108N-ZSP25XI 51-85160 54-pin TSOP II CY14B108L-ZS45XIT 51-85087 44-pin TSOP II CY14B108L-ZS45XI 51-85087 44-pin TSOP II CY14B108L-BA45XIT 51-85128 48-ball FBGA CY14B108L-BA45XI 51-85128 48-ball FBGA CY14B108N-BA45XIT 51-85128 48-ball FBGA CY14B108N-BA45XI 51-85128 48-ball FBGA CY14B108N-ZSP45XIT 51-85160 54-pin TSOP II CY14B108N-ZSP45XI 51-85160 54-pin TSOP II Operating Range Industrial All the above parts are Pb-free. Ordering Code Definitions CY 14 B 108 L - ZS 20 X I T Option: T - Tape & Reel Blank - Std. Pb-Free Package: ZS - 44-pin TSOP II BA - 48-ball FBGA ZSP - 54-pin TSOP II Voltage: B - 3.0 V Temperature: I - Industrial (–40 to 85 °C) Data Bus: L-×8 N - × 16 Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns Density: 108 - 8 Mb 14 - NVSRAM Cypress Document Number: 001-45523 Rev. *O Page 19 of 27 CY14B108L CY14B108N Package Diagrams Figure 15. 44-pin TSOP II Package Outline, 51-85087 51-85087 *E Document Number: 001-45523 Rev. *O Page 20 of 27 CY14B108L CY14B108N Package Diagrams (continued) Figure 16. 48-ball FBGA (6 × 10 × 1.2 mm) Package Outline, 51-85128 51-85128 *G Document Number: 001-45523 Rev. *O Page 21 of 27 CY14B108L CY14B108N Package Diagrams (continued) Figure 17. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Package Outline, 51-85160 51-85160 *E Document Number: 001-45523 Rev. *O Page 22 of 27 CY14B108L CY14B108N Acronyms Acronym Document Conventions Description Units of Measure CMOS complementary metal oxide semiconductor BHE byte high enable °C degree Celsius BLE byte low enable k kilohm CE EIA chip enable kHz kilohertz electronic industries alliance MHz megahertz FBGA fine-pitch ball grid array A microampere HSB I/O hardware store busy F microfarad input/output s microsecond nvSRAM non-volatile static random access memory mA milliampere OE RoHS output enable ms millisecond restriction of hazardous substances ns nanosecond RWI read and write inhibited ohm SRAM static random access memory % percent TSOP thin small outline package pF picofarad WE write enable s second V volt W watt Document Number: 001-45523 Rev. *O Symbol Unit of Measure Page 23 of 27 CY14B108L CY14B108N Errata This section describes the errata for the 8 Mb (2048 K × 8 and 1024 K × 16) nvSRAM product families. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. You can also send your related queries directly to [email protected]. Part Numbers Affected Part Number Device Characteristics CY14B108L 1024 K × 8, Asynchronous Interface nvSRAM in 44 TSOP-II and 48 FBGA package options CY14B108N 512 K × 16, Asynchronous Interface nvSRAM in 54 TSOP-II and 48 FBGA package options 8Mb (1024 K × 8, 512 K × 16) nvSRAM Qualification Status Production parts. 8Mb (1024 K × 8, 512 K × 16) nvSRAM Errata Summary The following table defines the errata applicability to available CY14B108L, CY14B108N devices. Items Part Number Silicon Revision Fix Status 1. AutoStore Disable feature does not work correctly CY14B108L CY14B108N Rev 0 None. This issue is applicable to all 8Mb nvSRAM parts in production 1. AutoStore Disable feature does not work correctly ■ Problem Definition The AutoStore Disable soft sequence disables the AutoStore feature in nvSRAMs. The AutoStore Disable feature is used in applications where data written in the SRAM is not required to be saved automatically on power loss. The 8Mb nvSRAM executes the nonvolatile Store automatically in half the memory (4Mb) even after the AutoStore feature is disabled. The reason is as follows: The 8Mb nvSRAM uses two dice stack of 4Mb with HSB pin of each die are tied together. Each nvSRAM die in the stacked-die monitors the VCC power independently. When the device VCC fails, the die which detects the VCC dropping below VSWITCH first, internally triggers the power down interrupt and drives its HSB output low. Since the HSB is a bidirectional pin, the low HSB output driven by one die is detected as HSB input by the other die. Therefore, low on the HSB input of other die internally triggers hardware Store and executes unintended nonvolatile Store even though AutoStore was disabled by AutoStore Disable soft sequence. ■ Parameters Affected None. ■ Trigger Condition(S) Device VCC power down with nvSRAM AutoStore disable. ■ Scope of Impact It can corrupt the data in half of the memory by overwriting the existing data in its nonvolatile memory with unintended data. ■ Workaround None. AutoStore disable feature should not be used in 8Mb nvSRAMs. ■ Fix Status This issue is applicable to all 8Mb nvSRAM parts in production and will continue serving with errata. There is no plan to fix this issue in the existing parts in production. Document Number: 001-45523 Rev. *O Page 24 of 27 CY14B108L CY14B108N Document History Page Document Title: CY14B108L/CY14B108N, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM Document Number: 001-45523 Revision ECN Orig. of Change Submission Date ** 2428826 GVCH See ECN New Data Sheet *A 2520023 GVCH / PYRS 06/23/08 Updated ICC1 for tRC=20ns, 25ns and 45ns access speed for both industrial and Commercial temperature Grade Updated Thermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP II packages Changed tCW value from 16ns to 15ns *B 2676670 GVCH / PYRS 03/20/2009 Added maximum accumulated storage time for 150C and 85C Temperature Added best practices Changed ICC2 from 12mA to 20mA Changed ICC3 from 38mA to 40mA Changed ICC4 from 12mA to 10mA Changed ISB from 6mA to 10mA Changed VCAP from 164uF to 360uF Changed Input Rise and Fall Times from 5ns to 3ns Updated ICC1, ICC3, ISBand IOZ Test conditions Changed tDELAY to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively Changed tSTORE from 15ms to 8ms Added VHDIS, tHHHD and tLZHSB parameters Software controlled STORE/RECALL cycle table: Changed tAS to tSA Changed tGHAX to tHA Added tDHSB parameter Changed tHLHX to tPHSB Updated tSS from 70us to 100us Added Truth table for SRAM operations Updated ordering information *C 2712462 GVCH / PYRS 05/29/2009 Moved data sheet status from Preliminary to Final Updated AutoStore operation Updated ISB test condition Updated footnote 7 Referenced footnote 9 to VCCRISE, tHHHD and tLZHSB parameters Updated VHDIS parameter description *D 2746310 GVCH 07/29/2009 Page 4: Updated Hardware STORE (HSB) operation description page 5: Updated Software STORE description Updated tDELAY parameter description Updated footnote 18 and added footnote 23 Referenced footnote 23 to Figure 11 and Figure 12 *E 2759948 GVCH 09/04/2009 Removed commercial temperature related specs *F 2828257 GVCH 12/15/2009 Changed STORE cycles to QuantumTrap from 200K to 1 Million Added Contents on page 2 *G 2894560 GVCH 03/18/2010 Removed part numbers CY14B108N-ZSP20XIT and CY14B108N-ZSP20XI from ordering information table. Updated Package diagrams 51-85160 and 51-85087. Updated Sales, Solution, and Legal Information Section. Updated copyright section. Updated table of contents. *H 2923475 GVCH / AESA 04/27/2010 Table 1: Added more clarity on HSB pin operation Hardware STORE Operation: Added more clarity on HSB pin operation Table 1: Added more clarity on BHE/BLE pin operation Updated HSB pin operation in Figure 10 Updated footnote 34 Document Number: 001-45523 Rev. *O Description of Change Page 25 of 27 CY14B108L CY14B108N Document History Page (continued) Document Title: CY14B108L/CY14B108N, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM Document Number: 001-45523 Revision ECN Orig. of Change Submission Date *I 3143765 GVCH 01/17/2011 48-ball FBGA package: 16 Mb address expansion is not supported Updated thermal resistance values for all packages Added Acronyms table and Document Conventions table *J 3311413 GVCH 07/13/2011 Updated DC Electrical Characteristics (Added Note 9 and referred the same note in VCAP parameter). Updated AC Switching Characteristics (Added Note 13 and referred the same note in Parameters). Updated Package Diagrams. Description of Change *K 3580269 GVCH 04/12/2012 Updated Package Diagrams. *L 3658005 GVCH 08/10/2012 Updated Maximum Ratings (Changed “Ambient temperature with power applied” to “Maximum junction temperature”). Updated DC Electrical Characteristics (Added VVCAP parameter and its details, added Note 11 and referred the same note in VVCAP parameter, also referred Note 12 in VVCAP parameter). Updated Package Diagrams (spec 51-85160 (Changed revision from *C to *D)). *M 4500772 ZSK 09/12/2014 Updated Package Diagrams: spec 51-85087 – Changed revision from *D to *E. spec 51-85160 – Changed revision from *D to *E. Added Errata. Updated to new template. *N 4563189 ZSK 11/12/2014 Added related documentation hyperlink in page 1 *O 4714292 GVCH 04/08/2015 No technical updates. Completing Sunset Review. Document Number: 001-45523 Rev. *O Page 26 of 27 CY14B108L CY14B108N Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/psoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2015. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-45523 Rev. *O Revised April 8, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 27 of 27