CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S 16-Mbit (2048 K × 8/1024 K × 16/512 K × 32) nvSRAM Features ■ 16-Mbit nonvolatile static random access memory (nvSRAM) ❐ 25-ns, 30-ns and 45-ns access times ❐ Internally organized as 2048 K × 8 (CY14X116L), 1024 K × 16 (CY14X116N), 512 K × 32 (CY14X116S) ❐ Hands-off automatic STORE on power-down with only a small capacitor ❐ STORE to QuantumTrap nonvolatile elements is initiated by software, device pin, or AutoStore on power-down ❐ RECALL to SRAM initiated by software or power-up ■ High reliability ❐ Infinite read, write, and RECALL cycles ❐ 1 million STORE cycles to QuantumTrap ❐ Data retention: 20 years ■ Sleep mode operation ■ Low power consumption ❐ Active current of 75 mA at 45 ns ❐ Standby mode current of 650 A ❐ Sleep mode current of 10 A ■ ■ Operating voltages: ❐ CY14B116X: VCC = 2.7 V to 3.6 V ❐ CY14E116X: VCC = 4.5 V to 5.5 V Functional Description The Cypress CY14X116L/CY14X116N/CY14X116S is a fast SRAM, with a nonvolatile element in each memory cell. The memory is organized as 2048 K bytes of 8 bits each or 1024 K words of 16 bits each or 512 K words of 32 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM can be read and written an infinite number of times. The nonvolatile data residing in the nonvolatile elements do not change when data is written to the SRAM. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. For a complete list of related documentation, click here. ■ Industrial temperature: –40 C to +85 C ■ Packages ❐ 44-pin thin small-outline package (TSOP II) ❐ 48-pin thin small-outline package (TSOP I) ❐ 54-pin thin small-outline package (TSOP II) ❐ 165-ball fine-pitch ball grid array (FBGA) package ■ Restriction of hazardous substances (RoHS) compliant Cypress Semiconductor Corporation Document #: 001-67793 Rev. *M Offered speeds ❐ 44-pin TSOP II: 25 ns and 45 ns ❐ 48-pin TSOP I: 30 ns and 45 ns ❐ 54-pin TSOP II: 25 ns and 45 ns ❐ 165-ball FBGA: 25 ns and 45 ns • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 7, 2015 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Logic Block Diagram[1, 2, 3] V CC V CAP POWER CONTROL SLEEP MODE CONTROL A 0-A11 ROW DECODER QUANTUMTRAP 4096 X 4096 STORE STORE / RECALL CONTROL ZZ HSB RECALL STATIC RAM ARRAY 4096 X 4096 SOFTWARE DETECT A 2-A14 OE [4] CE CONTROL LOGIC OUTPUT BUFFERS COLUMN IO SENSE AMPS DQ 0-DQ 31 INPUT BUFFERS WE BA /BLE BB /BHE BC BD ZZ COLUMN DECODER A 12-A20 Notes 1. Address A0 - A20 for ×8 configuration, address A0 - A19 for ×16 configuration and address A0 - A18 for ×32 configuration. 2. Data DQ0 - DQ7 for ×8 configuration, data DQ0 - DQ15 for ×16 configuration and data DQ0 - DQ31 for ×32 configuration. 3. BLE, BHE are applicable for ×16 configuration and BA, BB, BC, BD are applicable for ×32 configuration only. 4. TSOP II package is offered in single CE. TSOP I and BGA packages are offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Document #: 001-67793 Rev. *M Page 2 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Contents Pinouts .............................................................................. 4 Pin Definitions .................................................................. 7 Device Operation .............................................................. 8 SRAM Read ................................................................ 8 SRAM Write................................................................. 8 AutoStore Operation (Power-Down)............................ 8 Hardware STORE (HSB) Operation............................ 9 Hardware RECALL (Power-Up) .................................. 9 Software STORE......................................................... 9 Software RECALL ....................................................... 9 Sleep Mode ............................................................... 10 Preventing AutoStore ................................................ 12 Data Protection.......................................................... 12 Maximum Ratings........................................................... 13 Operating Range............................................................. 13 DC Electrical Characteristics ........................................ 13 Data Retention and Endurance ..................................... 14 Capacitance .................................................................... 14 Thermal Resistance........................................................ 14 AC Test Conditions ........................................................ 15 AC Switching Characteristics ....................................... 16 AutoStore/Power-Up RECALL Characteristics............ 20 Sleep Mode Characteristics........................................... 21 Document #: 001-67793 Rev. *M Software Controlled STORE and RECALL Characteristics................................................................ Hardware STORE Characteristics................................. Truth Table For SRAM Operations................................ For ×8 Configuration ................................................. For ×8 Configuration ................................................. For ×16 Configuration ............................................... For ×16 Configuration ............................................... For ×32 Configuration ............................................... Ordering Information...................................................... Ordering Code Definitions ......................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC® Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... 22 23 24 24 24 24 25 25 26 27 28 32 32 32 33 36 36 36 36 36 36 Page 3 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Pinouts Figure 1. Pin Diagram: 44-Pin TSOP II (×8) NC A20 A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 44 43 42 41 40 39 44 - TSOP II (x8) Top View (not to scale) 15 16 17 18 19 20 21 22 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Figure 2. Pin Diagram: 54-Pin TSOP II (×16) NC A19 A0 HSB NC[6] A19 A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC A12 A11 A10 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 - TSOP II (x16) Top View (not to scale) 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB A18 A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC Figure 3. Pin Diagram: 48-Pin TSOP I (×8) A15 A14 A13 A12 A11 A10 A9 A8 A19 [5] NC WE CE2 VCAP NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 - TSOP I (x8) Top View (not to scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 HSB VSS A20 DQ7 NC DQ6 NC DQ5 NC DQ4 VCC NC DQ3 NC DQ2 NC DQ1 NC DQ0 OE VSS CE1 A0 Note 5. Address expansion for 32-Mbit. NC pin not connected to die. Document #: 001-67793 Rev. *M Page 4 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Pinouts (continued) Figure 4. Pin Diagram: 48-Pin TSOP I (×16) A15 A14 A13 A12 A11 A10 A9 A8 A19 [6] NC WE CE2 VCAP BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48 - TSOP I (x16) Top View (not to scale) A16 HSB VSS DQ15 DQ7 DQ 14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE1 A0 Figure 5. Pin Diagram: 165-Ball FBGA (×16) 1 2 3 4 5 6 7 8 9 10 11 A NC A6 A8 WE BLE CE1 NC OE A5 A3 NC B NC DQ0 DQ1 A4 BHE CE2 NC A2 NC NC NC C ZZ NC NC VSS A0 A7 A1 VSS NC DQ15 DQ14 D NC DQ2 NC VSS VSS VSS VSS VSS NC NC NC E NC VCAP NC VCC VSS VSS VSS VCC NC DQ13 NC F NC DQ3 NC VCC VCC VSS VCC VCC NC NC DQ12 G HSB NC NC VCC VCC VSS VCC VCC NC NC NC H NC NC VCC VCC VCC VSS VCC VCC VCC NC NC J NC NC NC VCC VCC VSS VCC VCC NC DQ8 NC K NC NC DQ4 VCC VCC VSS VCC VCC NC NC NC L NC DQ5 NC VCC VSS VSS VSS VCC NC NC DQ9 M NC NC NC VSS VSS VSS VSS VSS NC DQ10 NC N NC DQ6 DQ7 VSS A11 A10 A9 VSS NC NC NC P NC NC NC A13 A19 NC A18 A12 NC DQ11 NC R NC NC A15 NC A17 NC A16 NC[6] A14 NC NC Note 6. Address expansion for 32-Mbit. NC pin not connected to die. Document #: 001-67793 Rev. *M Page 5 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Pinouts (continued) Figure 6. Pin Diagram: 165-Ball FBGA (×32) 1 2 3 4 5 6 7 8 9 10 11 A NC A6 A8 WE BA CE1 BC OE A5 A3 NC B NC DQ0 DQ1 A4 BB CE2 BD A2 NC NC DQ31 C ZZ NC DQ4 VSS A0 A7 A1 VSS NC DQ27 DQ26 D NC DQ2 DQ5 VSS VSS VSS VSS VSS NC NC DQ30 E NC VCAP DQ6 VCC VSS VSS VSS VCC NC DQ25 DQ29 F NC DQ3 DQ7 VCC VCC VSS VCC VCC NC NC DQ24 G HSB NC DQ12 VCC VCC VSS VCC VCC NC NC DQ28 H NC NC VCC VCC VCC VSS VCC VCC VCC NC NC J NC NC DQ13 VCC VCC VSS VCC VCC NC DQ20 DQ19 K NC NC DQ8 VCC VCC VSS VCC VCC NC NC DQ18 L NC DQ9 DQ14 VCC VSS VSS VSS VCC NC NC DQ21 M NC NC DQ15 VSS VSS VSS VSS VSS NC DQ22 DQ17 N NC DQ10 DQ11 VSS A11 A10 A9 VSS NC NC DQ16 P NC NC NC A13 NC NC A18 A12 NC DQ23 NC R NC NC A15 NC A17 NC A16 NC[7] A14 NC NC Note 7. Address expansion for 32-Mbit. NC pin not connected to die. Document #: 001-67793 Rev. *M Page 6 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Pin Definitions Pin Name I/O Type A0 – A20 A0 – A19 Description Address inputs. Used to select one of the 2,097,152 bytes of the nvSRAM for the ×8 configuration. Input A0 – A18 Address inputs. Used to select one of the 1,048,576 words of the nvSRAM for the ×16 configuration. Address inputs. Used to select one of the 524,288 words of the nvSRAM for the ×32 configuration. DQ0 – DQ7 Bidirectional data I/O lines for the ×8 configuration. Used as input or output lines depending on operation. DQ0 – DQ15 Input/Output Bidirectional data I/O lines for the ×16 configuration. Used as input or output lines depending on operation. DQ0 – DQ31 Bidirectional data I/O lines for ×32 configuration. Used as input or output lines depending on operation. WE Input CE Input CE1, CE2 Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location. Chip Enable input in TSOP II package, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Chip Enable input in FBGA package. The device is selected and a memory access begins on the falling edge of CE1 (while CE2 is HIGH) or the rising edge of CE2 (while CE1 is LOW). OE Input Output Enable, Active LOW. The Active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. BLE/BA[8] Input Byte Enable, Active LOW. When selected LOW, enables DQ7–DQ0. BHE/BB[8] Input Byte Enable, Active LOW. When selected LOW, enables DQ15–DQ8. BC[8] Input Byte Enable, Active LOW. When selected LOW, enables DQ23–DQ16. BD[8] Input Byte Enable, Active LOW. When selected LOW, enables DQ31–DQ24. ZZ[9] Input Sleep Mode Enable. When the ZZ pin is pulled LOW, the device enters a low-power Sleep mode and consumes the lowest power. Since this input is logically AND’ed with CE, ZZ must be HIGH for normal operation. VCC Power Supply Power supply inputs to the device. VSS Power Supply Ground for the device. Must be connected to ground of the system. HSB Hardware STORE Busy (HSB).When LOW, this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Input/Output Hardware and Software STORE operation, HSB is driven HIGH for a short time (t HHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional). VCAP Power Supply NC NC AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. No Connect. Die pads are not connected to the package pin. Notes 8. BLE, BHE are applicable for ×16 configuration and BA, BB, BC, BD are applicable for ×32 configuration only. 9. Sleep mode feature is offered in 165-ball FBGA package only. Document #: 001-67793 Rev. *M Page 7 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Device Operation AutoStore Operation (Power-Down) The CY14X116L/CY14X116N/CY14X116S nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) automatically at power-down, or from the nonvolatile cell to the SRAM (the RECALL operation) on power-up. Both the STORE and RECALL operations are also available under software control. Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14X116L/CY14X116N/ CY14X116S supports infinite reads and writes to the SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations. See the Truth Table For SRAM Operations on page 24 for a complete description of read and write modes. The CY14X116L/CY14X116N/CY14X116S stores data to the nonvolatile QuantumTrap cells using one of the three storage operations. These three operations are: Hardware STORE, activated by the HSB; Software STORE, activated by an address sequence; AutoStore, on device power-down. The AutoStore operation is a unique feature of nvSRAM and is enabled by default on the CY14X116L/CY14X116N/CY14X116S. The CY14X116L/CY14X116N/CY14X116S performs a read cycle whenever CE and OE are LOW, and WE, ZZ, and HSB are HIGH. The address specified on pins A0–A20 or A0–A19 or A0–A18 determines which of the 2,097,152 data bytes or 1,048,576 words of 16 bits or 524,288 words of 32 bits each are accessed. Byte enables (BLE, BHE) determine which bytes are enabled to the output, in the case of 16-bit words and byte enables (BA, BB, BC, BD) determine which bytes are enabled to the output, in the case of 32-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. Note If the capacitor is not connected to the VCAP pin, AutoStore must be disabled using the soft sequence specified in the section Preventing AutoStore on page 12. If AutoStore is enabled without a capacitor on the VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the STORE. This corrupts the data stored in the nvSRAM. Figure 7. AutoStore Mode VCC 0.1 uF VCC 10 k: SRAM Read During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a STORE operation during power-down. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC and a STORE operation is initiated with power provided by the VCAP capacitor. WE VCAP V SS VCAP SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–DQ31 is written into the memory if it is valid tSD before the end of a WE-controlled write or before the end of a CE-controlled write. The Byte Enable inputs (BLE, BHE determine which bytes are written, in the case of 16-bit words and Byte Enable inputs (BA, BB, BC, BD) determine which bytes are written, in the case of 32-bit words. Keep OE HIGH during the entire write cycle to avoid data bus contention on the common I/O lines. If OE is left LOW, the internal circuitry turns off the output buffers tHZWE after WE goes LOW. Document #: 001-67793 Rev. *M Figure 7 shows the proper connection of the storage capacitor (VCAP) for the automatic STORE operation. Refer to DC Electrical Characteristics on page 13 for the size of the VCAP. The voltage on the VCAP pin is driven to VVCAP by a regulator on the chip. A pull-up resistor should be placed on WE to hold it inactive during power-up. This pull-up resistor is only effective if the WE signal is in tristate during power-up. When the nvSRAM comes out of power-up-RECALL, the host microcontroller must be active or the WE held inactive until the host microcontroller comes out of reset. To reduce unnecessary nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place (which sets a write latch) since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. Page 8 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Hardware STORE (HSB) Operation The CY14X116L/CY14X116N/CY14X116S provides the HSB pin to control and acknowledge the STORE operations. The HSB pin is used to request a Hardware STORE cycle. When the HSB pin is driven LOW, the device conditionally initiates a STORE operation after tDELAY. A STORE cycle begins only if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (an internal 100-k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by an internal 100-k pull-up resistor. SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. If the write latch is not set, HSB is not driven LOW by the device. However, any of the SRAM read and write cycles are inhibited until HSB is returned HIGH by the host microcontroller or another external source. During any STORE operation, regardless of how it is initiated, the device continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after the HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power-Up) During power-up or after any low-power condition (VCC < VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on power-up, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. A Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the Document #: 001-67793 Rev. *M STORE cycle, the previous nonvolatile data is first erased, followed by a store into the nonvolatile elements. After a STORE cycle is initiated, further reads and writes are disabled until the cycle is completed. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence. Otherwise, the sequence is aborted and no STORE or RECALL takes place. To initiate the Software STORE cycle, the following read sequence must be performed: 1. Read address 0x4E38 Valid Read 2. Read address 0xB1C7 Valid Read 3. Read address 0x83E0 Valid Read 4. Read address 0x7C1F Valid Read 5. Read address 0x703F Valid Read 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE-controlled reads or OE-controlled reads, with WE kept HIGH for all the six read sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, perform the following sequence of CE or OE controlled read operations: 1. Read address 0x4E38 Valid Read 2. Read address 0xB1C7 Valid Read 3. Read address 0x83E0 Valid Read 4. Read address 0x7C1F Valid Read 5. Read address 0x703F Valid Read 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements. Page 9 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Sleep Mode In Sleep mode, the device consumes the lowest power supply current (IZZ). The device enters a low-power Sleep mode after asserting the ZZ pin LOW. After the Sleep mode is registered, the nvSRAM does a STORE operation to secure the data to the nonvolatile memory and then enters the low-power mode. The device starts consuming IZZ current after tSLEEP time from the instance when the sleep mode is initiated. When the ZZ pin is LOW, all input pins are ignored except the ZZ pin. The nvSRAM is not accessible for normal operations while it is in sleep mode. When the ZZ pin is de-asserted (HIGH), there is a delay tWAKE before the user can access the device. If sleep mode is not used, the ZZ pin should be tied to VCC. Note When nvSRAM enters sleep mode, it initiates a nonvolatile STORE cycle, which results in losing one endurance cycle for every Sleep mode entry unless data has not been written to the nvSRAM since the last nonvolatile STORE/RECALL operation. Note If the ZZ pin is LOW during power-up, the device will not be in Sleep mode. However, the I/Os are in tristate until the ZZ pin is de-asserted (HIGH). Figure 8. Sleep Mode (ZZ) Flow Diagram Power Applied After tHRECALL After tWAKE Device Ready CE = LOW ZZ = HIGH CE = HIGH ZZ = HIGH CE = LOW; ZZ = HIGH Active Mode (ICC) Standby Mode (ISB) CE = HIGH; ZZ = HIGH CE = Don’t Care ZZ = HIGH ZZ = LOW ZZ = LOW Sleep Routine After tSLEEP Sleep Mode (IZZ) Document #: 001-67793 Rev. *M Page 10 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Table 1. Mode Selection CE[10] H WE X OE X BLE, BHE / BA, BB, BC, BD[11] X A15 - A0[12] X Mode I/O Power Not selected Output High Z Standby L H L L X Read SRAM Output Data Active L L X L X Write SRAM Input Data Active L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output Data Output Data Output Data Output Data Output Data Output Data Active[13] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output Data Output Data Output Data Output Data Output Data Output Data Active[13] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Active ICC2[13] Output Data Output Data Output Data Output Data Output High Z L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z Active[13] Notes 10. The TSOP II package is offered in single CE. TSOP I, and BGA packages are offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted on any of the chip enable pins (CE for the single chip enable device; CE1 and CE2 for the dual chip enable device). 11. BLE, BHE are applicable for the ×16 configuration and BA, BB, BC, BD are applicable for the ×32 configuration only. 12. While there are 21 address lines on the CY14X116L (20 address lines on the CY14X116N and 19 address lines on the CY14X116S), only 13 address lines (A14–A2) are used to control software modes. The remaining address lines are don’t care. 13. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile operation. Document #: 001-67793 Rev. *M Page 11 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid Read 2. Read address 0xB1C7 Valid Read 3. Read address 0x83E0 Valid Read 4. Read address 0x7C1F Valid Read 5. Read address 0x703F Valid Read 6. Read address 0x8B45 AutoStore Disable AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: If the AutoStore function is disabled or re-enabled, a manual software STORE operation must be performed to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled and 0x00 written in all cells. Data Protection The CY14X116L/CY14X116N/CY14X116S protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and write operations. The low-voltage condition is detected when VCC is less than VSWITCH. If the CY14X116L/CY14X116N/CY14X116S is in a write mode at power-up (both CE and WE are LOW), after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brownout conditions. 1. Read address 0x4E38 Valid Read 2. Read address 0xB1C7 Valid Read 3. Read address 0x83E0 Valid Read 4. Read address 0x7C1F Valid Read 5. Read address 0x703F Valid Read 6. Read address 0x4B46 AutoStore Enable Document #: 001-67793 Rev. *M Page 12 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Package power dissipation capability (TA = 25 °C) ................................................. .1.0 W Storage temperature ................................ –65 C to +150 C Maximum accumulated storage time Surface mount lead soldering temperature (3 Seconds).......................................... +260 C At 150 C ambient temperature .................................. 1000 h DC output current (1 output at a time, 1s duration) ..... 20 mA At 85 C ambient temperature.................... ............. 20 Years Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Maximum junction temperature .................................. 150 C Latch-up current .................................................... > 140 mA Supply voltage on VCC relative to VSS CY14B116X: ................................................–0.5 V to +4.1 V CY14E116X: ................................................–0.5 V to +7.0 V Operating Range Product Range Voltage applied to outputs in high-Z state...................................... –0.5 V to VCC + 0.5 V CY14B116X Input voltage .........................................–0.5 V to Vcc + 0.5 V CY14E116X Ambient Temperature (TA) VCC Industrial –40 C to +85 C 2.7 V to 3.6 V 4.5 V to 5.5 V Transient voltage (<20 ns) on any pin to ground potential .................. –2.0 V to VCC + 2.0 V DC Electrical Characteristics Over the Operating Range Parameter VCC ICC1 Description Min Typ[14] Max Unit CY14B116X 2.7 3.0 3.6 V CY14E116X 4.5 5.0 5.5 V Values obtained without output loads tRC = 25/30 ns (IOUT = 0 mA) tRC = 45 ns – – 95 mA – – 75 mA All inputs don’t care, VCC = VCC (max). Average current for duration tSTORE – – 10 mA Test Conditions Power supply Average VCC current ICC2 Average VCC current during STORE ICC3 Average VCC current at All inputs cycling at CMOS Levels. Values obtained without output loads (IOUT = 0 mA). tRC = 200 ns, VCC (Typ), 25 °C – 50 – mA ICC4[15] Average VCAP current All inputs don’t care. Average current for duration tSTORE during AutoStore cycle – – 6 mA ISB VCC standby current tRC = 25/30 ns – – 650 A tRC = 45 ns – – 500 A CE > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). ‘Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. IZZ Sleep mode current All inputs are static at CMOS Level – – 10 A IIX[16] Input leakage current (except HSB) VCC = VCC (max), VSS < VIN < VCC –1 – +1 A Input leakage current (for HSB) VCC = VCC (max), VSS < VIN < VCC –100 – +1 A Notes 14. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested. 15. This parameter is only guaranteed by design and is not tested. 16. The HSB pin has IOUT = -2 uA for VOH of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. Document #: 001-67793 Rev. *M Page 13 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S DC Electrical Characteristics (continued) Over the Operating Range Parameter Test Conditions Min Typ[14] Max Unit VCC = VCC(Max), VSS < VOUT < VCC, CE or OE > VIH or BLE, BHE/BA, BB, BC, BD > VIH or WE < VIL –1 – +1 A Description IOZ Off state output leakage current VIH Input HIGH voltage 2.0 – VCC + 0.5 V VIL Input LOW voltage VSS – 0.5 – 0.8 V VOH Output HIGH voltage IOUT = –2 mA 2.4 – – V VOL Output LOW voltage IOUT = 4 mA – – 0.4 V VCAP[17] Storage capacitor Between VCAP pin and VSS 19.8 22.0 82.0 F – – 5.0 V VVCAP[18, 19] Maximum voltage driven on VCAP pin by the device VCC = VCC (max) Data Retention and Endurance Over the Operating Range Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 20 Years 1,000,000 Cycles Capacitance In the following table, the capacitance parameters are listed. [19] Parameter Description Test Conditions CIN Input capacitance CIO Input/Output capacitance COUT Output capacitance Max Max (All packages except 165-FBGA) (165-FBGA package) TA = 25 C, f = 1 MHz, VCC = VCC (Typ) Unit 8 10 pF 8 10 pF 8 10 pF Thermal Resistance In the following table, the thermal resistance parameters are listed.[19] Parameter Description Test Conditions JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 44-TSOP II 48-TSOP I 54-TSOP II 165-FBGA Unit 44.6 35.6 41.1 15.6 C/W 2.4 2.33 4.6 2.9 C/W Notes 17. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. 18. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating temperature range should be higher than the VVCAP voltage 19. These parameters are only guaranteed by design and are not tested. Document #: 001-67793 Rev. *M Page 14 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Figure 9. AC Test Loads and Waveforms For 3 V (CY14B116X): For Tristate specs 577 577 3.0 V 3.0 V R1 R1 OUTPUT OUTPUT R2 789 CL 30 pF R2 789 CL 5 pF For 5 V (CY14E116X): For Tristate specs 963 963 5.0 V 5.0 V R1 R1 OUTPUT OUTPUT CL 30 pF R2 512 CL 5 pF R2 512 AC Test Conditions CY14B116X CY14E116X 0 V to 3 V 0 V to 3 V Input rise and fall times (10%–90%) <3 ns <3 ns Input and output timing reference levels 1.5 V 1.5 V Input pulse levels Document #: 001-67793 Rev. *M Page 15 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S AC Switching Characteristics Over the Operating Range[20] Parameters Cypress Parameter Alt Parameter SRAM Read Cycle tACE tACS Description 25 ns Min Max 30 ns Min Max 45 ns Min Max Unit Chip enable access time – 25 – 30 – 45 ns [22] tRC Read cycle time 25 – 30 – 45 - ns tAA [23] tAA Address access time – 25 – 30 – 45 ns tDOE tOE Output enable to data valid – 12 – 14 – 20 ns tOH Output hold after address change 3 – 3 – 3 – ns tLZ Chip enable to output active 3 – 3 – 3 – ns tHZ Chip disable to output inactive – 10 – 12 – 15 ns tLZOE [24] tOLZ Output enable to output active 0 – 0 – 0 – ns tHZOE [21, 24] tOHZ Output disable to output inactive – 10 – 12 – 15 ns tPU [24] tPA Chip enable to power active 0 – 0 – 0 – ns tPD [24] tPS Chip disable to power standby – 25 – 30 – 45 ns tDBE Byte enable to data valid – 12 – 14 – 20 ns tLZBE[24] Byte enable to output active 0 – 0 – 0 – ns tHZBE[21, 24] Byte disable to output inactive – 10 – 12 – 15 ns tRC tOHA [23] tLZCE [24] tHZCE [21, 24] SRAM Write Cycle tWC tWC Write cycle time 25 – 30 – 45 – ns tPWE tWP Write pulse width 20 – 24 – 30 – ns tSCE tCW Chip enable to end of write 20 – 24 – 30 – ns tSD tDW Data setup to end of write 10 – 14 – 15 – ns tHD tDH Data hold after end of write 0 – 0 – 0 – ns tAW tAW Address setup to end of write 20 – 24 – 30 – ns tSA tAS Address setup to start of write 0 – 0 – 0 – ns tHA tWR Address hold after end of write 0 – 0 – 0 – ns tHZWE [21, 24, 25] tWZ Write enable to output disable – 10 – 12 - 15 ns tLZWE [24] tOW Output active after end of write 3 – 3 – 3 – ns Byte enable to end of write 20 – 24 – 30 – ns tBW Notes 20. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(Typ), and output loading of the specified IOL/IOH and 30 pF load capacitance as shown in Figure 9. 21. tHZCE, tHZOE, tHZBE and tHZWE are specified with a load capacitance of 5 pF. Transition is measured ±200 mV from the steady state output voltage. 22. WE must be HIGH during SRAM read cycles. 23. Device is continuously selected with CE, OE and BLE, BHE/BA, BB, BC, BD LOW. 24. These parameters are only guaranteed by design and are not tested. 25. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. Document #: 001-67793 Rev. *M Page 16 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Figure 10. SRAM Read Cycle 1: Address Controlled[26, 27, 28] tRC Address Address Valid tAA Output Data Valid Previous Data Valid Data Output tOHA Figure 11. SRAM Read Cycle 2: CE and OE Controlled[26, 28] Address Address Valid tRC [30] tHZCE tACE CE tAA tLZCE tHZOE tDOE OE tHZBE tLZOE [29] tDBE BLE, BHE /BA, BB, BC, BD tLZBE Data Output High Impedance Output Data Valid tPU ICC Standby tPD Active Notes 26. WE must be HIGH during SRAM read cycles. 27. Device is continuously selected with CE, OE and BLE, BHE/BA, BB, BC, BD LOW. 28. HSB must remain HIGH during Read and Write cycles. 29. BLE, BHE are applicable for the ×16 configuration and BA, BB, BC, BD are applicable for the ×32 configuration only. 30. TSOP II package is offered in single CE and BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted on any of the chip enable pins (CE for the single chip enable device; CE1 and CE2 for the dual chip enable device). Document #: 001-67793 Rev. *M Page 17 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Figure 12. SRAM Write Cycle 1: WE Controlled[32, 34, 36] tWC Address Address Valid tSCE tHA [35] CE tBW [31] BLE, BHE /BA, BB, BC, BD tAW tPWE WE tSA tHD tSD Data Input Input Data Valid tLZWE tHZWE Data Output High Impedance Previous Data Figure 13. SRAM Write Cycle 2: CE Controlled[32, 34, 36] tWC Address Valid Address tSA tSCE tHA [35] CE [31] tBW BLE, BHE /BA, BB, BC, BD tPWE WE tSD Data Input Data Output tHD Input Data Valid High Impedance Notes 31. BLE, BHE are applicable for the ×16 configuration and BA, BB, BC, BD are applicable for the ×32 configuration only. 32. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 33. WE must be HIGH during SRAM read cycles. 34. HSB must remain HIGH during Read and Write cycles. 35. TSOP II package is offered in single CE. TSOP I and BGA packages are offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted on any of the chip enable pins (CE for the single chip enable device; CE1 and CE2 for the dual chip enable device). 36. CE or WE must be >VIH during address transitions. Document #: 001-67793 Rev. *M Page 18 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Figure 14. SRAM Write Cycle 3: BHE, BLE/ BA, BB, BC, BDControlled[38, 39, 40] tWC Address Address Valid tSCE [41] CE tSA tHA tBW [37] BLE, BHE /BA, BB, BC, BD tAW tPWE WE tSD Data Input Data Output tHD Input Data Valid High Impedance Notes 37. BLE, BHE are applicable for the ×16 configuration and BA, BB, BC, BD are applicable for the ×32 configuration only. 38. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 39. HSB must remain HIGH during Read and Write cycles. 40. CE or WE must be >VIH during address transitions. 41. TSOP II package is offered in single CE. TSOP I and BGA packages are offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted on any of the chip enable pins (CE for the single chip enable device; CE1 and CE2 for the dual chip enable device). Document #: 001-67793 Rev. *M Page 19 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S AutoStore/Power-Up RECALL Characteristics Over the Operating Range Parameter Description Min Max Unit tHRECALL [42] Power-Up RECALL duration – 30 ms tSTORE [43] STORE cycle duration – 8 ms tDELAY [44, 45] Time allowed to complete SRAM write cycle – 25 ns VSWITCH Low-voltage trigger level CY14B116X – 2.65 V CY14E116X – 4.40 V 150 – s tVCCRISE[45] VCC rise time VHDIS[45] HSB output disable voltage – 1.9 V tLZHSB[45] HSB to output active time – 5 s tHHHD[45] HSB HIGH active time – 500 ns Figure 15. AutoStore or Power-Up RECALL[46] VCC VSWITCH VHDIS [43] t VCCRISE Note tHHHD [43] tSTORE Note tHHHD [47] Note tSTORE [47] Note HSB out tDELAY tLZHSB tLZHSB AutoStore tDELAY Power-Up RECALL tHRECALL tHRECALL Read & Write Inhibited (RWI) Power-Up RECALL Read & Write BROWN OUT AutoStore Power-Up RECALL Read & Write Power-down AutoStore Notes 42. tHRECALL starts from the time VCC rises above VSWITCH. 43. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 44. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 45. These parameters are only guaranteed by design and are not tested. 46. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 47. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document #: 001-67793 Rev. *M Page 20 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Sleep Mode Characteristics Over the Operating Range Parameter Description Min Max Unit tWAKE Sleep mode exit time (ZZ HIGH to first access after wakeup) – 30 ms tSLEEP Sleep mode enter time (ZZ LOW to CE don’t care) – 8 ms tZZL ZZ active LOW time 50 – ns tWEZZ Last write to sleep mode entry time 0 – s tZZH ZZ active to DQ Hi-Z time – 70 ns Figure 16. Sleep Mode[48] V CC V SWITCH V SWITCH t t SLEEP HRECALL t WAKE ZZ t WEZZ WE t DQ Read & Write Inhibited (RWI) ZZH Data Power-Up RECALL Read & Write Sleep Entry Sleep Sleep Exit Read & Write Power-down AutoStore Note 48. Device initiates sleep routine and enters into Sleep mode after tSLEEP duration. Document #: 001-67793 Rev. *M Page 21 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Software Controlled STORE and RECALL Characteristics Over the Operating Range[49, 50] Parameter 25 ns Description 30 ns 45 ns Min 25 Max – Min 30 Max – Min 45 Max – Unit tRC STORE/RECALL initiation cycle time tSA Address setup time 0 – 0 – 0 – ns tCW Clock pulse width 20 – 24 – 30 – ns tHA Address hold time 0 – 0 – 0 – ns tRECALL RECALL duration – 600 – 600 – 600 s tSS [51, 52] Soft sequence processing time – 500 – 500 – 500 s ns Figure 17. CE and OE Controlled Software STORE and RECALL Cycle[50] tRC Address tRC Address #1 tSA [53] Address #6 tCW tCW CE tHA tSA tHA tHA tHA OE tHHHD HSB (STORE only) tHZCE tLZCE t DELAY [54] Note tLZHSB High Impedance tSTORE/tRECALL DQ (DATA) RWI Figure 18. AutoStore Enable and Disable Cycle Address tSA [53] CE tRC tRC Address #1 Address #6 tCW tCW tHA tSA tHA tHA tHA OE tLZCE tSS tHZCE Note [54] t DELAY DQ (DATA) RWI Notes 49. The software sequence is clocked with CE controlled or OE controlled reads. 50. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles. 51. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. 52. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 53. TSOP II package is offered in single CE. TSOP I and BGA packages are offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted on any of the chip enable pins (CE for the single chip enable device; CE1 and CE2 for the dual chip enable device). 54. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time. Document #: 001-67793 Rev. *M Page 22 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Hardware STORE Characteristics Over the Operating Range Parameter Description Min Max Unit tDHSB HSB to output active time when write latch not set – 25 ns tPHSB Hardware STORE pulse width 15 – ns Figure 19. Hardware STORE Cycle[55] Write Latch set ~ ~ tPHSB HSB (IN) tSTORE tHHHD ~ ~ tDELAY HSB (OUT) tLZHSB RWI Write Latch not set ~ ~ tPHSB HSB (IN) tDELAY ~ ~ HSB (OUT) HSB pin is driven HIGH to VCC only by internal 100 K: resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. RWI Figure 20. Soft Sequence Processing[56, 57] Soft Sequence Command Address [58] Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 tSS Address #6 tCW CE V CC Notes 55. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 56. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. 57. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 58. TSOP II package is offered in single CE. TSOP I and BGA packages are offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted on any of the chip enable pins (CE for the single chip enable device; CE1 and CE2 for the dual chip enable device). Document #: 001-67793 Rev. *M Page 23 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For ×8 Configuration Single chip enable option (44-pin TSOP II package) CE WE OE Inputs and Outputs Mode Power H X X High-Z Deselect/Power-down Standby L H L Data out (DQ0–DQ7) Read Active L H H High-Z Output disabled Active L L X Data in (DQ0–DQ7) Write Active For ×8 Configuration Dual chip enable option (48-pin TSOP I package) CE1 CE2 WE OE H X X X Inputs and Outputs High-Z Mode Power Deselect/Power-down Standby X L X X High-Z Deselect/Power-down Standby L H H L Data out (DQ0–DQ7) Read Active L H H H High-Z Output disabled Active L H L X Data in (DQ0–DQ7) Write Active For ×16 Configuration Single chip enable option (54-pin TSOP II package) CE WE OE BLE BHE Inputs and Outputs Mode Power H X X X X High-Z Deselect/Power-down Standby L X X H H High-Z Output disabled Active Read Active L H L L L Data out (DQ0–DQ15) L H L L H Data out (DQ0–DQ7); DQ8–DQ15 in High-Z Read Active L H L H L Data out (DQ8–DQ15); DQ0–DQ7 in High-Z Read Active L H H X X High-Z Output disabled Active L L X L L Data in (DQ0–DQ15) Write Active L L X L H Data in (DQ0–DQ7); DQ8–DQ15 in High-Z Write Active L L X H L Data in (DQ8–DQ15); DQ0–DQ7 in High-Z Write Active Document #: 001-67793 Rev. *M Page 24 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S For ×16 Configuration Dual chip enable option (48-pin TSOP I package and 165-ball FBGA package) CE1 CE2 WE OE BLE BHE Inputs and Outputs Mode Power H X X X X X High-Z Deselect/Power-down Standby X L X X X X High-Z Deselect/Power-down Standby L H X X H H High-Z Output disabled Active L H H L L L Data out (DQ0–DQ15) Read Active L H H L L H Data out (DQ0–DQ7); DQ8–DQ15 in High-Z Read Active L H H L H L Data out (DQ8–DQ15); DQ0–DQ7 in High-Z Read Active L H H H X X High-Z Output disabled Active L H L X L L Data in (DQ0–DQ15) Write Active L H L X L H Data in (DQ0–DQ7); DQ8–DQ15 in High-Z Write Active L H L X H L Data in (DQ8–DQ15); DQ0–DQ7 in High-Z Write Active For ×32 Configuration Dual chip enable option (165-ball FBGA package) CE1 CE2 WE OE BA BB BC BD DQ0–DQ7 DQ8–DQ15 DQ16–DQ23 DQ24–DQ31 H X X X L L X X X X X High-Z High-Z High-Z High-Z deselect/ Standby Power down X X X X X X High-Z High-Z High-Z High-Z deselect/ Standby Power down H X X X X X X High-Z High-Z High-Z High-Z Selected Active L H H L L L L L Data out Data out Data out Data out Read all Active bits L H H L L H H H Data out High-Z High-Z High-Z Read Active L H H L H L H H High-Z Data out High-Z High-Z Read Active L H H L H H L H High-Z High-Z Data out High-Z Read Active L H H L H H H L High-Z High-Z High-Z Data out Read Active L H L X L L L L Data in Data in Data in Data in Write all bits Active L H L X L H H H Data in High-Z High-Z High-Z Write Active L H L X H L H H High-Z Data in High-Z High-Z Write Active L H L X H H L H High-Z High-Z Data in High-Z Write Active L H L X H H H L High-Z High-Z High-Z Data in Write Active L H H H X X X X High-Z High-Z High-Z High-Z Document #: 001-67793 Rev. *M Mode Power Output Active disabled Page 25 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Ordering Information Speed (ns) 25 30 45 Ordering Code Package Diagram Package Type CY14B116L-ZS25XI 51-85087 44-pin TSOP II CY14B116L-ZS25XIT 51-85087 44-pin TSOP II CY14E116L-ZS25XI 51-85087 44-pin TSOP II CY14E116L-ZS25XIT 51-85087 44-pin TSOP II CY14B116N-ZSP25XI 51-85160 54-pin TSOP II CY14E116N-ZSP25XI 51-85160 54-pin TSOP II CY14B116N-BZ25XI 51-85195 165-ball FBGA CY14B116N-BZ25XIT 51-85195 165-ball FBGA CY14B116S-BZ25XI 51-85195 165-ball FBGA CY14B116S-BZ25XIT 51-85195 165-ball FBGA CY14E116S-BZ25XI 51-85195 165-ball FBGA CY14E116S-BZ25XIT 51-85195 165-ball FBGA CY14B116L-Z30XI 51-85183 48-pin TSOP I CY14B116L-Z30XIT 51-85183 48-pin TSOP I CY14E116L-Z30XI 51-85183 48-pin TSOP I CY14E116L-Z30XIT 51-85183 48-pin TSOP I CY14B116N-Z30XI 51-85183 48-pin TSOP I CY14B116N-Z30XIT 51-85183 48-pin TSOP I CY14E116N-Z30XI 51-85183 48-pin TSOP I CY14E116N-Z30XIT 51-85183 48-pin TSOP I CY14B116L-ZS45XI 51-85087 44-pin TSOP II CY14B116L-ZS45XIT 51-85087 44-pin TSOP II CY14E116L-ZS45XI 51-85087 44-pin TSOP II CY14E116L-ZS45XIT 51-85087 44-pin TSOP II CY14B116L-Z45XI 51-85183 48-pin TSOP I CY14B116L-Z45XIT 51-85183 48-pin TSOP I CY14E116L-Z45XI 51-85183 48-pin TSOP I CY14E116L-Z45XIT 51-85183 48-pin TSOP I CY14B116N-Z45XI 51-85183 48-pin TSOP I CY14B116N-Z45XIT 51-85183 48-pin TSOP I CY14B116N-ZSP45XI 51-85160 54-pin TSOP II CY14B116N-ZSP45XIT 51-85160 54-pin TSOP II CY14E116N-Z45XI 51-85183 48-pin TSOP I CY14E116N-Z45XIT 51-85183 48-pin TSOP I CY14B116N-BZ45XI 51-85195 165-ball FBGA CY14B116N-BZ45XIT 51-85195 165-ball FBGA CY14B116S-BZ45XI 51-85195 165-ball FBGA CY14B116S-BZ45XIT 51-85195 165-ball FBGA Operating Range Industrial All parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Document #: 001-67793 Rev. *M Page 26 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Ordering Code Definitions CY14 B 116 L - ZS 25 X I T Option: T - Tape & Reel Blank - Std. Pb-Free Package: ZS P- 44-TSOP II ZS P- 48-TSOP I ZSP - 54-TSOP II BZA - 165-FBGA Temperature: I - Industrial (–40 to 85 °C) Speed: 25 - 25 ns 30 - 30 ns 45 - 45 ns Data Bus: L - ×8 N - ×16 S - ×32 Density: 116 - 16-Mbit Voltage: B - 3.0 V E - 5.0 V 14 - nvSRAM Cypress Document #: 001-67793 Rev. *M Page 27 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Package Diagrams Figure 21. 44-Pin TSOP II package outline (51-85087) 51-85087 *E Document #: 001-67793 Rev. *M Page 28 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Package Diagrams (continued) Figure 22. 48-Pin TSOP I Package Outline (51-85183) 51-85183 *D Document #: 001-67793 Rev. *M Page 29 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Package Diagrams (continued) Figure 23. 54-Pin TSOP II Package Outline (51-85160) 51-85160 *E Document #: 001-67793 Rev. *M Page 30 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Package Diagrams (continued) Figure 24. 165-ball FBGA (15 mm × 17 mm × 1.40 mm) Package Outline (51-85195) 51-85195 *C Document #: 001-67793 Rev. *M Page 31 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Acronyms Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor EIA Electronic Industries Alliance °C degrees celsius FBGA Fine-Pitch Ball Grid Array Hz hertz I/O Input/Output Kbit kilobit JESD JEDEC Standards kHz kilohertz nvSRAM nonvolatile Static Random Access Memory k kilohm RoHS Restriction of Hazardous Substances A microampere RWI Read and Write Inhibited mA milliampere TSOP II Thin Small Outline Package F microfarad Mbit megabit MHz megahertz s microsecond ms millisecond ns nanosecond pF picofarad V volt ohm W watt Symbol Unit of Measure All errata for this product are fixed, effective date code 1431 (YY=14, WW=31). For more information, refer to datasheet 001-67793 Rev. *J, or contact Cypress Technical Support at http://www.cypress.com/support. Document #: 001-67793 Rev. *M Page 32 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Document History Page Document Title: CY14B116L/CY14B116N/CY14B116S/CY14E116L/CY14E116N/CY14E116S, 16-Mbit (2048 K × 8/1024 K × 16/512 K × 32) nvSRAM Document Number: 001-67793 Rev. ECN No. Orig. of Change Submission Date ** 3186783 GVCH 03/02/2011 New datasheet. *A 3202367 GVCH 03/22/2011 Updated DC Electrical Characteristics (Changed maximum value of ISB parameter from 3 mA to 500 µA). *B 3459888 GVCH 12/09/2011 Changed status from “Advance” to “Preliminary”. Updated Pinouts (Updated Figure 5 and Figure 6). Updated Pin Definitions (Updated ZZ pin description). Updated DC Electrical Characteristics (Changed maximum value of ICC1 parameter from 70 mA to 95 mA for tRC = 25 ns, changed maximum value of ICC1 parameter from 50 mA to 75 mA for tRC = 45 ns, changed typical value of ICC3 parameter from 35 mA to 50 mA, changed maximum value of ICC4 parameter from 10 mA to 6 mA, changed maximum value of ISB parameter from 500 µA to 650 µA, added VCAP parameter values for CY14C116X, changed minimum value of VCAP parameter from 20 µF to 19 µF, changed typical value of VCAP parameter from 27 µF to 22 µF respectively, added Note 16 and referred the same note in VCAP parameter). Updated Thermal Resistance (Added values). Updated AC Switching Characteristics (Added Note 20 and referred the same note in Parameters column). Updated AutoStore/Power-Up RECALL Characteristics (Changed maximum value of tHRECALL parameter from 40 ms to 60 ms for CY14C116X, changed maximum value of tHRECALL parameter from 20 ms to 30 ms for CY14B116X/CY14E116X, changed maximum value of tWAKE parameter from 40 ms to 60 ms for CY14C116X, changed maximum value of tWAKE parameter from 20 ms to 30 ms for CY14B116X/CY14E116X). Updated Software Controlled STORE and RECALL Characteristics (Changed maximum value of tRECALL parameter from 300 µs to 600 µs, changed maximum value of tSS parameter from 200 µs to 500 µs). Updated Ordering Information (Updated part numbers). Updated Package Diagrams (To current revision). *C 3510173 GVCH 01/27/2012 Updated Ordering Information (Removed CY14E116N-ZS25XI and added CY14B116N-Z25XI part number). Updated in new template. *D 3733467 GVCH 09/14/2012 Updated Device Operation (Added Figure 8 under Sleep Mode). Updated Maximum Ratings (Changed “Ambient temperature with power applied” to “Maximum junction temperature”). Updated DC Electrical Characteristics (Added VVCAP parameter and its details, added Note 18 and referred the same note in VVCAP parameter, also referred Note 19 in VVCAP parameter). Updated Capacitance (Changed maximum value of CIN and COUT parameters from 7 pF to 11.5 pF). Added Sleep Mode and Figure 16 (Corresponding to SLEEP Mode). Updated Package Diagrams (spec 51-85087 (Changed revision from *D to *E). Document #: 001-67793 Rev. *M Description of Change Page 33 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Document History Page (continued) Document Title: CY14B116L/CY14B116N/CY14B116S/CY14E116L/CY14E116N/CY14E116S, 16-Mbit (2048 K × 8/1024 K × 16/512 K × 32) nvSRAM Document Number: 001-67793 Rev. ECN No. Orig. of Change Submission Date Description of Change *E 4198509 GVCH 01/23/2014 Updated Features: Removed 2.5 V operating range voltage support. Added 54-pin TSOP II package related information. Updated Logic Block Diagram Updated Device Operation: Updated AutoStore Operation (Power-Down): Removed sentence “The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress.” Updated DC Electrical Characteristics: Updated Test Conditions of ISB parameter and also updated the corresponding values. Changed maximum value of VIH parameter from “VCC + 0.3 V” to “VCC + 0.5 V”. Updated VCAP value from 20 uF to 19.8 uF. Added Note 20. Updated Capacitance: Changed maximum value of CIN and COUT parameters from 11.5 pF to 8 pF. Updated Sleep Mode: Changed maximum value of tZZH parameter from 20 ns to 70 ns. Updated Figure 8 and Figure 16 for more clarity. Updated Truth Table For SRAM Operations for more clarity. Updated Ordering Information (Updated part numbers). Updated Package Diagrams: Added 54-pin TSOP II package related information (Figure 23). *F 4303589 GVCH 03/20/2014 Updated Thermal Resistance: Updated values of JA and JC parameters. Updated in new template. Completing Sunset Review. *G 4366689 GVCH 05/01/2014 Updated Sleep Mode: Updated description. Updated DC Electrical Characteristics: Removed “RTC running on backup power supply” in test conditions of IZZ parameter. Added Note 14 and 25. Updated Ordering Information (Updated part numbers (Added Part numbers namely CY14B116N-ZSP45XI, CY14B116N-ZSP45XIT, CY14E116S-BZ25XI and CY14E116S-BZ25XIT)). Added . *H 4409843 GVCH 06/17/2014 Updated DC Electrical Characteristics: Updated maximum value of VVCAP parameter to 5.0 V for CY14B116X and CY14E116X. *I 4417851 GVCH 06/24/2014 Added footnote 15 Capacitance: Updated CIN and COUTvalue from 8 pF to 10 pF for 165-FBGA package Added CIO parameter Updated Ordering Code Definitions to add package code for 48-TSOP I package *J 4432183 GVCH 07/07/2014 DC Electrical Characteristics: Updated maximum value of VCAP parameter from 120.0 F to 82.0 F Document #: 001-67793 Rev. *M Page 34 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Document History Page (continued) Document Title: CY14B116L/CY14B116N/CY14B116S/CY14E116L/CY14E116N/CY14E116S, 16-Mbit (2048 K × 8/1024 K × 16/512 K × 32) nvSRAM Document Number: 001-67793 Rev. ECN No. Orig. of Change Submission Date *K 4456803 ZSK 07/31/2014 Removed Errata section. Added a note at the end of the document mentioning when the errata items were fixed. *L 4562106 GVCH 11/05/2014 Added related documentation hyperlink in page 1. Updated package diagram 51-85160 to current revision. *M 4616093 GVCH 01/07/2015 Changed datasheet status from Preliminary to Final. Updated 48-pin TSOP I package outline. Document #: 001-67793 Rev. *M Description of Change Page 35 of 36 CY14B116L/CY14B116N/CY14B116S CY14E116L/CY14E116N/CY14E116S Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/psoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-67793 Rev. *M Revised January 7, 2015 All products and company names mentioned in this document are the trademarks of their respective holders. Page 36 of 36