Product Overview MC100EPT25: Translator, Differential LVECL / ECL to LVTTL For complete documentation, see the data sheet Product Description The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the Dbar input for a non-inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 µF capacitor. Features • • • • • • • • • 1.1ns Typical Propagation Delay Maximum Frequency > 275 MHz Typical Operating Range: VCC = 3.0 V to 3.6 V; VEE = -5.5 V to -3.0 V; GND = 0 V 24mA TTL outputs Q Output will default LOW with inputs open or at GND VBB Output Open Input Default State Safety Clamp on Inputs Pb-Free Packages are Available Part Electrical Specifications Product Compliance Status Channels Input Level Output Level VCC Typ (V) fMax Typ (MHz) tpd Typ (ns) tR & tF Max (ps) Package Type MC100EPT25DG Pb-free Active 1 ECL TTL 3.3 275 0.95 1400 SOIC-8 Halide free MC100EPT25DR2G Pb-free 600 Active 1 ECL TTL 3.3 275 0.95 Halide free MC100EPT25DTG Pb-free Pb-free Active 1 ECL TTL 3.3 275 0.95 Pb-free Active 1 ECL TTL 3.3 TSSOP-8 275 0.95 600 TSSOP-8 1400 Active 1 ECL TTL 3.3 Halide free For more information please contact your local sales support at www.onsemi.com Created on: 6/30/2016 1400 600 Halide free MC100EPT25MNR4G SOIC-8 1400 Halide free MC100EPT25DTR2G 600 275 0.95 1400 600 DFN-8