MC100EPT25
Differential LVECL/ECL to
LVTTL Translator
The MC100EPT25 is a Differential LVECL/ECL to LVTTL
translator. This device requires +3.3V, –3.3V to –5.2V, and ground.
The small outline 8–lead SOIC package and the single gate of the
EPT25 make it ideal for applications which require the translation of a
clock or data signal.
The VBB output allows the EPT25 to also be used in a single–ended
input mode. In this mode the VBB output is tied to the D input for a
non–inverting buffer or the D input for an inverting buffer. If used, the
VBB pin should be bypassed to ground via a 0.01mF capacitator.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.1ns Typical Propagation Delay
275MHz Fmax (Clock bit stream, not pseudo–random)
Differential LVECL/ECL inputs
Small Outline SOIC Package
24mA TTL outputs
Flow Through Pinouts
Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D
Q Output will default LOW with inputs open or at GND
ESD Protection: >4000V HBM, >200V MM
VBB Output
New Differential Input Common Mode Range
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 111 devices
VEE 1
D
2
D
3
8
LVTTL
VCC
7
Q
6
NC
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MARKING
DIAGRAMS*
8
SO–8
D SUFFIX
CASE 751
8
1
1
8
TSSOP–8
DT SUFFIX
CASE 948R
8
1
1
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
FUNCTION
Q
LVTTL Output
D, D
Differential LVECL Input Pair
VCC
Positive Supply
VBB
GND
Output Reference Voltage
VEE
Negative Supply
Ground
Device
4
5
GND
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
Semiconductor Components Industries, LLC, 2000
May, 2000 – Rev. 1
HR25
ALYW
ORDERING INFORMATION
LVECL
VBB
HPT25
ALYW
1
Package
Shipping
MC100EPT25D
SO–8
98 Units / Rail
MC100EPT25DR2
SO–8
2500 / Reel
MC100EPT25DT
TSSOP–8
98 Units / Rail
MC100EPT25DTR2
TSSOP–8
2500 / Reel
Publication Order Number:
MC100EPT25/D
MC100EPT25
MAXIMUM RATINGS*
Value
Unit
VCC
Symbol
Power Supply (Referenced to GND, VEE = –3.3V)
Parameter
0 to 3.8
VDC
VEE
Power Supply (Referenced to GND, VCC = +3.3V)
–6.0 to 0
VDC
VI
Input Voltage (VI not more positive than GND)
0 to 3.8
VDC
Iout
Output Current
50
100
mA
IBB
VBB Sink/Source Current{
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature
–65 to +150
°C
θJA
Thermal Resistance (Junction–to–Ambient)
190
130
°C/W
θJC
Thermal Resistance (Junction–to–Case)
41 to 44 ± 5%
°C/W
Tsol
Solder Temperature (<2 to 3 Seconds: 245°C desired)
265
°C
Continuous
Surge
Still Air
500lfpm
* Maximum Ratings are those values beyond which damage to the device may occur.
{ Use for inputs of same package only.
DC CHARACTERISTICS, ECL/LVECL (VCC = +3.3V; VEE = –5.5V to –3.0V, GND = 0V)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
8.0
16
25
8.0
16
25
8.0
16
25
mA
IEE
Power Supply Current
(Note 1.)
VIH
Input HIGH Voltage Single Ended
(Note 4.)
–1165
–880
–1165
–880
–1165
–880
mV
VIL
Input LOW Voltage Single Ended
(Note 4.)
–1810
–1625
–1810
–1625
–1810
–1625
mV
VBB
Output Voltage Reference
–1550
–1350
–1550
–1350
–1550
–1350
mV
0.0
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 3.)
IIH
Input HIGH Current
IIL
Input LOW Current
–1450
VEE+2.0
0.0
150
D
D
0.5
–150
–1450
VEE+2.0
0.0
150
0.5
–150
–1450
VEE+2.0
0.5
–150
µA
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
1. (VCC = +3.3V, GND = 0V, VEE = –3.3V), all other pins floating.
2. All loading with 500 ohms to GND, CL = 20pF.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
4. Input and output parameters vary 1:1 with VCC.
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2
MC100EPT25
TTL OUTPUT DC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V; VEE = –3.3V ± 0.3V; TA = –40°C to 85°C)
Symbol
Characteristic
Min
Typ
Max
Unit
ICCH
Power Supply Current (Outputs set to HIGH)
6.0
10
14
mA
ICCL
Power Supply Current (Outputs set to LOW)
7.0
12
17
mA
VOH
Output HIGH Voltage (IOH = –3.0mA) (Note 5.)
2.2
VOL
Output LOW Voltage (IOL = 24mA) (Note 5.)
V
0.5
V
IOS
Output Short Circuit Current
–130
–60
mA
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
5. All loading with 500 ohms to GND, CL = 20pF.
AC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V)
–40°C
Symbol
Characteristic
Min
25°C
Typ
Max
1200
1800
Min
85°C
Typ
Max
1100
1600
Typ
Max
1100
1600
Maximum Toggle Frequency
275
tPLH,
tPHL
Propagation Delay to
Output Differential
800
tSK+ +
tSK– –
tSKPP
Output–to–Output Skew++
Output–to–Output Skew– –
Part–to–Part Skew (Note 6.)
60
25
500
60
25
500
60
25
500
ps
tJITTER
Cycle–to–Cycle Jitter
TBD
TBD
TBD
ps
VPP
Input Voltage Swing
(Differential) (Note 7.)
800
800
275
Unit
fmax
100
275
Min
800
MHz
ns
1200
100
800
1200
100
800
1200
mV
tr
Output Rise/Fall Times
Q, Q
450
600
750
tf
900
1160
1400
(0.8V – 2.0V)
6. Skews are measured between outputs under identical conditions.
7. 200mV input guarantees full logic swing at the output.
450
900
600
1100
750
1400
450
900
600
1100
750
1400
ps
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MC100EPT25
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–06
ISSUE T
D
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
5
0.25
H
E
M
B
M
1
4
h
B
e
X 45 _
q
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
S
DIM
A
A1
B
C
D
E
e
H
h
L
q
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MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
MC100EPT25
PACKAGE DIMENSIONS
TSSOP–8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R–02
ISSUE A
8x
0.15 (0.006) T U
K REF
0.10 (0.004)
S
2X
L/2
8
1
PIN 1
IDENT
S
T U
S
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
S
5
0.25 (0.010)
B
–U–
L
0.15 (0.006) T U
M
M
4
A
–V–
F
DETAIL E
C
0.10 (0.004)
–T– SEATING
PLANE
D
–W–
G
DETAIL E
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5
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC100EPT25
Notes
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MC100EPT25
Notes
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MC100EPT25
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC100EPT25/D