Data Sheet, Rev 2.1, April 2007 TLE7259G LIN Transceiver Automotive Power LIN Transceiver 1 TLE7259G Overview Features • • • • • • • • • • • • • • • • Transmission rate up to 20 kBaud Compliant to LIN specification 1.2, 1.3, 2.0 and 2.1 Support of K-line function (ISO 9141) Very high ESD Robustness Very low Electromagnetic Emission (EME) Very High Electromagnetic Immunity (EMI) Very low current consumption in sleep mode Very low leakage current on the BUS output Control output for voltage regulator Wake up source recognition (local/remote) For 3.3 V and 5 V micro controller I/O Suitable for 12V and 24V board-net Bus short to VBAT protection Bus short to GND handling Over temperature protection AEC Qualified P-DSO-8 Description The TLE7259G is a transceiver for the Local Interconnect Network (LIN) with integrated wake-up and protection features. It is designed for in-vehicle networks using data transmission rates from 2.4 kBaud to 20 kBaud. The TLE7259G functions as a bus driver between the protocol controller and the physical bus inside the LIN network. Compliant to all LIN standards and with a wide operational supply range the TLE7259G can be used in all automotive applications. Different operation modes and the INH output allow the TLE7259G to control external components, like voltage regulators. In Sleep-mode the TLE7259G draws less than 8 µA of quiescent while still being able to wake up off of LIN bus traffic and a local wake-up input. The very low leakage current on the BUS pin makes the TLE7259G especially suitable for “Mixed Power Supply“ applications and supports the low quiescent current requirements of the LIN network. Based on the Infineon Smart Power Technology SPT®, the TLE7259G provides excellent ESD Robustness together with a very high electromagnetic immunity (EMI). The TLE7259G reaches a very low level of electromagnetic emission (EME) within a broad frequency range and independent form the battery voltage. The Infineon Smart Power Technology SPT® allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuit. The TLE7259G and the Infineon SPT® technology are AEC qualified and tailored to withstand the harsh condition of the Automotive Environment. Type Package Marking TLE7259G P-DSO-8 7259G Data Sheet 2 Rev 2.1, 2007-04-27 TLE7259G Block Diagram 2 Block Diagram VS 8 7 Supply Output Stage RBUS Bus 6 Driver INH 5V 2 Mode Control Temp.Protection Current Limit EN REN TxD Input 4 Timeout Receiver TxD RTD 1 RxD Filter Local-wake and bus-wake Comparator 3 WK Figure 1 Data Sheet 5 GND Filter Functional Block Diagram 3 Rev 2.1, 2007-04-27 TLE7259G Pin Configuration 3 Pin Configuration 3.1 Pin Assignment RxD 1 8 INH EN 2 7 VS WK 3 6 BUS TxD 4 5 GND Figure 2 Pin Configuration (top view) 3.2 Pin Definitions and Functions Table 1 Pin Definitions and Functions Pin No. Symbol Function 1 RxD Receive data output; External Pull Up necessary LOW in dominant state, active LOW after a wake-up event at Bus or WK pin 2 EN Enable input; integrated pull-down, device in normal operation mode when HIGH 3 WK Wake input; active LOW, negative edge triggered, internal pull-up 4 TxD Transmit data input; integrated pull-down, LOW in dominant state; active LOW after wake-up via WK pin 5 GND Ground 6 Bus Bus output/input; LIN bus line input/output LOW in dominant state Internal pull-up 7 VS Battery supply input 8 INH Inhibit output; battery supply related output HIGH (VS) in Normal and Stand-By operation mode can be used to control an external voltage regulator can be used to control external bus termination resistor when the device will be used as Master node Data Sheet 4 Rev 2.1, 2007-04-27 TLE7259G Functional Description 4 Functional Description The LIN Bus is a single wire, bi-directional bus, used for in-vehicle networks. The LIN Transceiver TLE7259G is the interface between the micro controller and the physical LIN Bus (see Figure 11 and Figure 12). The logical values of the micro controller are driven to the LIN bus via the TxD input of the TLE7259G. The transmit data stream on the TxD input is converted to a LIN bus signal with optimized slew rate to minimize the EME level on the LIN bus. The RxD output reads back the information from the LIN bus to the micro controller, regardless of the logical value of the TxD input. The receiver has an integrated filter network to suppress noise on the LIN Bus and to increase the EMI level of the transceiver. Two logical states are possible on the LIN bus according to the LIN Specification 2.1. The dominate state (voltage near ground) on the LIN bus represents a “logic 0“ on the TxD input of the TLE7259G; the recessive state (voltage near supply voltage VS) represents a “logic 1” on the TxD input (see timing diagram Figure 9). Every LIN network consists of a master node and one or more slave nodes. To configure the TLE7259G for master node applications, a resistor in the range of 1 kΩ and a reverse diode must be connected between the LIN bus and the power supply VS or the INH pin of the TLE7259G (see Figure 11 and Figure 12). 4.1 Operating Modes The TLE7259G has 3 different operation modes. After a power-up event the TLE7259G starts from the Stand-By mode. By setting the EN pin to “logic 1“ the micro controller can change the mode into Normal-Operation mode. Power-Up Normal Mode EN INH High High EN High Stand-By EN Low EN High EN RxD TxD INH Low Low 1) Floating 2) Low 3) High 4) High Sleep Mode EN INH Low Floating Wake Up via Bus: t > twake,bus via Wake: t > twake 1) After wake up (via Bus or Wake) 2) After start up 3) After wake up via Wake (internal strong pull down, > 1.9 mA) 4) After wake up via Bus (internal weak pull down, 350 k Ω ) AEA03514.VSD Figure 3 Data Sheet Operation Mode State Diagram 5 Rev 2.1, 2007-04-27 TLE7259G Functional Description Table 2 Operating modes Mode EN INH TxD Sleep Low Floating Low RxD LIN Bus Comments Termination High1) High Impedance No wake-up request detected Stand-By Low High Low2) High3) Low High 1) 30 kΩ (typical) RxD “Low” after local or bus wake-up RxD “High“ after power-up TxD strong pull down after local wake-up (WK pin)2) TxD weak pull down after bus wake-up or powerup3) Normal High Low High Low High 30 kΩ (typical) RxD reflects the signal on the LIN bus TxD driven by the micro controller High 1) Pull-up resistor to micro controller power supply (VIO) required (see Figure 11 and Figure 12). 2) TxD indicates logical “Low“ in case the micro controller output is set to “High“ and the micro controller output current is limited to less than 1.9 mA. 3) TxD indicates logical “High“ in case the micro controller output is set to “High“. 4.2 Normal Operation Mode The TLE7259G enters the normal mode after the micro controller sets EN = high (see Figure 3). In Normal operation mode the LIN bus receiver and the LIN bus transmitter are active. Data from the micro controller is transmitted to the LIN bus via the TxD pin, the receiver detects the data stream on the LIN bus and outputs it to the RxD pin. 4.3 Stand-By Mode The Stand-By mode is entered automatically after: • • • • A power-up event on the supply VS. A wake-up event on the LIN bus. A local wake-up event on the pin WK. A power on reset caused by power supply VS dropping below VS,UV,PON (VS < VS,UV,PON). In Stand-By mode no communication on the LIN Bus is possible. The output stage is disabled and the LIN Bus termination remains activated. The RxD and TxD pins are indicating the wake-up source. The RxD pin remains “Low“ after a local and bus wake-up event. A power-up event is indicated by a logical “High“ on RxD pin. The signal on the TxD pin indicates the wake-up source, a weak pull-down signals a bus wake-up event and a strong pulldown signals a local wake-up event caused by the WK pin (see Table 2). In order to detect a wake-up event via the TxD pin, the external micro controller needs outputs needs to provide a logical “high” signal. The wake-up flags indicating the wake-up source on the pins TxD and RxD are reset by changing the operation mode to Normal operation. The signal on the EN pin remains “Low“ due to an internal pull-down resistor. Setting the EN pin to “High“, by the micro controller the device returns to Normal operation mode. Entering the Stand-By mode switches the INH output to VS. Depending on the operation mode of the TLE7259G external circuitry, like a voltage regulator, can be controlled by the INH output. Data Sheet 6 Rev 2.1, 2007-04-27 TLE7259G Functional Description 4.4 Sleep Mode In order to reduce the current consumption the TLE7259G offers a Sleep mode. In Sleep mode the quiescent current on VS and the leakage current on the pin Bus, are cut back to a minimum. Switching the TLE7259G from Normal operation mode to Sleep mode, the EN pin needs to be set to “Low”. A logical “High” on the EN pin sets the device direct back to Normal operation mode (see Figure 3). While the TLE7259G is in Sleep mode the following functions are available: • • • • • • • The output stage is disabled and the internal bus termination is switched off (High Impedance on the Bus pin). An internal current source on the Bus pin ensures that the level on the Bus pin remains dominate and protects the LIN network against accidental bus wake-up events. The receiver is turned off RxD and TxD pins are disabled. The logical state on the TxD pin is low, due to the internal pull-down resistor. The RxD pin is “High” driven by the external pull-up resistor The INH output is switched off and floating. The BUS wake-up comparator is active and turns the TLE7259G to Stand-By mode in case of a bus wake-up. The WK pin is active and turns the TLE7259G to Stand-By mode in case of a local wake-up. The EN pin remains active, switching EN pin to “High“ changes the operation mode to Normal operation. 4.5 Wake-up Events There are 3 different ways to wake-up the TLE7259G from Sleep mode. • • • Bus or also called remote wake-up via a dominate signal on the LIN bus. Local wake-up via a minimum dominant time (tWK) on the WK pin. Mode change from Sleep mode to Normal operation mode, by setting EN pin to logical “High”. Data Sheet 7 Rev 2.1, 2007-04-27 TLE7259G Functional Description 4.6 Bus Wake-up LIN Bus Signal VBUS VBUS,wk VBUS,dom tWK,bus Sleep Mode Stand-By Mode INH Figure 4 Bus wake-up behavior The bus wake-up, often called remote wake-up, changes the operation mode from Sleep mode to Stand-By mode. A falling edge on the LIN bus, followed by a dominate bus signal t > tWK,bus results in a bus wake-up. The mode change to Stand-By mode becomes active with the following rising edge on the LIN bus. The TLE7259G remains in Sleep mode until it detects a change from dominate to recessive on the LIN bus (see Figure 4). In Stand-By mode the TxD pin indicates the source of the wake-up event. A weak pull-down on the pin TxD indicates a bus wake-up event (see Figure 3). The RxD pin signals if a wake-up event occurred or the power-up event. A logical “Low” on the RxD pin reports a local or bus wake-up event, a logical “High“ signal on RxD indicates a power-up event. Data Sheet 8 Rev 2.1, 2007-04-27 TLE7259G Functional Description 4.7 Local Wake-up WK Signal VWK VWK,L tWK Stand-By Mode Sleep Mode INH Figure 5 Local wake-up behavior Beside the remote wake-up, a wake-up of the TLE7259G via the WK pin is possible. This wake-up event is called local wake up. A falling edge on the WK pin followed by a logical “Low“ for t > tWK results in a local wake up (see Figure 5) and change the operation mode to Stand-By Mode. In Stand-By mode the TxD pin indicates the source of the wake-up event. A strong pull down on the pin TxD indicates a local wake-up event via the pin WK (see Figure 3). The RxD pin signals if a wake-up event occurred or the power-up event. A logical “Low” on the RxD pin reports a local or bus wake-up event, a logical “High“ signal on RxD indicates a power-up event. Data Sheet 9 Rev 2.1, 2007-04-27 TLE7259G Functional Description 4.8 Mode Transition via EN pin EN Signal VEN VEN,ON EN Hysteresis VEN,OFF tsnorm Sleep Mode / Stand-By Mode Figure 6 tnsleep Normal Operation Mode Sleep Mode Mode transition via EN pin It is also possible to change from Sleep mode to Normal operation mode by setting the EN pin to logical “Low“.This feature is useful if the external micro controller is continuously powered and not connected to the INH pin. The EN pin has an integrate pull-down resistor to ensure the device remains in Sleep or Stand-By mode even if the voltage on the EN pin is floating. The EN pin has an integrated hysteresis (see Figure 6). A transition from logical “High“ to logical “Low“ on the EN pin changes the operation mode from Normal operation mode to Sleep mode. If the TLE7259G is already in Sleep mode, changing the EN from “Low“ to “High” results into a mode change from Sleep mode to Normal operation mode. If the device is in Stand-By mode a change from “Low“ to “High” on the EN pin changes the mode to Normal operation mode (see Figure 3). Data Sheet 10 Rev 2.1, 2007-04-27 TLE7259G Functional Description 4.9 Power-On Reset 6XSSO\YROWDJH9V 3RZHURQUHVHWOHYHO9689321 5HVHWGHYLFHVHWWR6WDQG%\0RGH 3RZHURQUHVHW 1RUPDORSHUDWLRQ PRGH %ODQNLQJWLPHWEODQN89 5HVHWDQG &RPPXQLFDWLRQ EORFNHG 6WDQG%\ PRGH 6XSSO\YROWDJH9V 8QGHUYROWDJHOHYHO9689%/. 3RZHURQUHVHWOHYHO9689321 %ODQNLQJWLPHWEODQN89 1RUPDORSHUDWLRQ PRGH Figure 7 1RUPDORSHUDWLRQ PRGH &RPPXQLFDWLRQ EORFNHG Power-on reset and Undervoltage situation A drooping power supply VS on a local ECU can effect the communication of the whole LIN network. To avoid any blocking of the LIN network by a local ECU the TLE7259G has an integrated power-on reset and undervoltage detection. In case the supply voltage is dropping below the power on reset level VS < VS,UV,PON, the TLE7259G changes the operation mode to Stand-By mode. In Stand-By mode the output stage of the TLE7259G is disabled and no communication to the LIN bus is possible. The internal bus termination remains active as well as the INH pin (see Figure 7). In Stand-By mode the RxD pin signals the low power supply condition with a logical “High“ Signal. A logical “High“ on the EN pin changes the operation mode back to Normal operation mode. In case the supply voltage VS is dropping below the specified operation range (see Table 5), the TLE7259G disables the output and receiver stages. The feature secures the communication on the LIN bus, even if the local ECU power supply of the TLE7259G drops below the specified operating range. If the power supply reaches a higher level as the undervoltage level VS > VS,UV,PON the TLE7259G continues with normal operation. A mode change only apply if the power supply VS drops below the power on reset level (VS < VS,UV,PON). Data Sheet 11 Rev 2.1, 2007-04-27 TLE7259G Functional Description 4.10 TxD time out function If the TxD signal is dominant for a time t > ttimeout the TxD time-out function deactivates the transmission of the LIN signal to the bus. This is realized to prevent the bus from being permanently blocked by a permanent “Low” signal on the TxD pin due to an error. The transmission is released again, after a rising edge at TxD has been detected. 4.11 Over temperature protection The TLE7259G has an integrated over temperature sensor, to protect the device against thermal overstress. In case of an over temperature event, the temperature sensor will disable the output stage. An over temperature event will not cause any mode change nor will it be signaled by either the RxD pin or the TxD pin. When the junction temperature falls below the thermal shut down level TJ < TjSD, the output stage is re-enabled and data communication can start again. A10°C hysteresis avoids toggling during the temperature shut down. 4.12 3.3 V and 5 V Logic Capability The TLE7259G can be used for 3.3 V and 5 V micro controllers. The inputs (TxD, EN) take the reference voltage from the connected micro controller pins. The RxD output must have an external pull-up resistor to the micro controller supply, to define the output voltage level. 4.13 BUS Short to GND Feature The TLE7259G has a feature implemented to protect the battery from running out of charge in the case the LIN bus is shorted to GND. In this failure case a normal master termination, a 1 kΩ resistor and a diode connected between the Bus pin and the power supply VS, would cause a constant current between VS and GND, even in sleep mode. The resulting resistance between VS and GND of this LIN bus short to GND is lower than 1 kΩ. To avoid this current during a generator off state, like in a parked car, the TLE7259G has a Bus Short to GND feature implemented. This feature is only applicable, if the master termination is connected to the INH pin, instead of the VS power supply (see Figure 11 and Figure 12). In Sleep mode the INH pin is switched of and no currently can flow between VS and GND. The internal 30 kΩ bus termination is also switched off (see Figure 1 and Table 2) to minimize the discharge current. 4.14 LIN Specifications 1.2, 1.3, 2.0 and 2.1 The device fulfills the Physical Layer Specification of LIN 1.2, 1.3, 2.0 and 2.1. The differences between LIN specification 1.2 and 1.3 is mainly the physical layer specification. The reason was to improve the compatibility between the nodes. The LIN specification 2.0 is a super set of the 1.3 version. The 2.0 version offers new features. However, it is possible to use the LIN 1.3 slave node in a 2.0 node cluster, as long as the new features are not used. Vice versa it is possible to use a LIN 2.0 node in the 1.3 cluster without using the new features. In terms of the physical layer the LIN 2.1 Specification doesn’t include any changes and is fully compliant to the LIN Specification 2.0. LIN 2.1 is the latest version of the LIN specification, released in December 2006. Data Sheet 12 Rev 2.1, 2007-04-27 TLE7259G General Product Characteristics 5 General Product Characteristics 5.1 Absolute Maximum Ratings Table 3 Absolute Maximum Ratings Voltages, Currents and Temperatures1) Tj = -40 °C to 150 °C; all voltages with respect to ground; positive current flowing into pin; (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Remarks LIN Spec 2.1 Param. 10 Min. Max. VS -0.3 40 V -40 -40 40 40 V V -40 -40 40 40 V V – -0.3 5.5 V – Voltages 5.1.1 Battery supply voltage 5.1.2 Bus input voltage versus GND versus VS t<1s 5.1.3 Wake input versus GND Wake input versus VS 5.1.4 Logic voltages at EN, TxD, RxD VBUS,G VBUS,Vs VWK,G VWK,Vs Vlogic 5.1.5 Inhibit Voltage versus GND Versus VS VINH,G VINH, Vs -0.3 -40 40 0,3 V V IINH -150 80 mA 2) Tj TS -40 150 °C – -55 150 °C – Unit Remarks Currents 5.1.6 Output current at INH Temperatures 5.1.7 Junction temperature 5.1.8 Storage temperature 1) Not subject to production test specified by design 2) Output current is internally limited to -150 mA Absolute Maximum Ratings ESD Resistivity1) Table 4 Pos. Parameter Symbol Limit Values Min. Max. VESD -6 6 kV Human Body Model2) (100 pF via 1.5 kΩ) 5.1.10 Electrostatic discharge voltage execpt VS versus Bus VESD -2 2 kV Human Body Model2) (100 pF via 1.5 kΩ) 5.1.11 Electrostatic discharge voltage at Bus versus VS VESD -1 1 kV Human Body Model (100 pF via 1.5 kΩ)2) 5.1.9 Electrostatic discharge voltage at VS,Bus, Wk versus GND 1) Not subject to production test specified by design 2) ESD susceptibility HBM according to EIA / JESD 22-A 114B Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Data Sheet 13 Rev 2.1, 2007-04-27 TLE7259G General Product Characteristics 5.2 Functional Range Table 5 Operating Range Pos. 5.2.1 Parameter Symbol Supply Voltage range VS Limit Values Unit Remarks Min. Max. VS 6 40 V LIN Spec 2.1 Param. 10 Tj -40 150 °C 1) Thermal parameters 5.2.2 Junction temperature 1) Not subject to production test, specified by design 5.3 Thermal Resistance Table 6 Thermal Resistance1) Pos. 5.3.1 Parameter Symbol RthJA Junction to Ambient Limit Values Min. Max. – 185 Unit Remarks K/W 2) 1) Not subject to production test, specified by design 2) JESD 51-2, 51-3, FR4 76,2 mm x 114,3 mm x 1,5 mm, 70µm, Cu, minimal footprint, TA = 27°C 5.4 Electrical Characteristics Table 7 Electrical Characteristics 7.0 V < VS < 27 V; RL = 500 Ω; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Remarks Current Consumption 5.4.1 Current consumption at VS in recessive state IS,rec 0.1 0.8 1.5 mA recessive state, without RL; VTxD = VCC 5.4.2 Current consumption at VS in dominant state IS,dom 0.1 1.3 2.5 mA dominant state, without RL; VTxD = 0 V 5.4.3 Current consumption in sleep mode IS,sleep 1 – 14 µA 5.4.4 Current consumption in sleep mode IS,sleep,typ 1 – 8 µA 5.4.5 Current consumption in stand-by mode IS,stby 0.1 – 1.5 mA Current consumption in sleep mode, bus shorted to ground IS,sleep,short 5 5.4.6 Data Sheet sleep mode, VWK = VS; VBUS = VS sleep mode, Tj=85°C VWK = VS; VBUS = VS stand-by mode, VWK = VS; VBUS = VS 10 60 µA sleep mode, VWK = VS; VBUS = 0V 14 Rev 2.1, 2007-04-27 TLE7259G General Product Characteristics Table 7 Electrical Characteristics (cont’d) 7.0 V < VS < 27 V; RL = 500 Ω; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Remarks Reset Levels 5.4.7 Blocking Undervoltage Detection at VS VS,UV,BLK 5 – 6 5.4.8 Power on reset VS,UV,PON – 2.4 4 V Device reset to Stand-byMode (see Figure 7) 5.4.9 Blanking time power on reset detection tblank,UV – 10 – µs 1) TjSD ∆T 150 170 190 °C 1) – 10 – K 1) 5.4.12 HIGH level leakage current IRD,H -5 0 5 µA 5.4.13 LOW level output current IRD,L 1.3 – 10 mA VRxD = 5 V; VBUS = VS VRxD = 0.9 V; VBUS = 0 V 5.4.14 HIGH level input voltage threshold VTD,H – – 0.7 × V recessive state 3.0 V < VEN < 5.5 V 5.4.15 TxD input hysteresis VTD,hys – 0.12 × – mV 3.0 V < VEN < 5.5 V 5.4.16 LOW level input voltage threshold VTD,L 0.3 × – – V dominant state 3.0 V < VEN < 5.5 V 5.4.17 TxD pull-down resistance RTD ITD 100 350 800 kΩ -1 – 10 µA ITD,L 1.5 3 6 mA VTxD = 5 V VEN = 0 V; VTxD = 0 V VBUS = VS VTxD = 0.9 V VBUS = VS 5.4.20 HIGH level input voltage threshold VEN,on 0.95 – 2 V normal mode see Figure 6 5.4.21 LOW level input voltage threshold VEN,off 0.8 – 1.85 V low power mode see Figure 6 5.4.22 EN input hysteresis VEN,hys REN IEN, hc 150 300 450 mV – 15 30 60 kΩ – 50 – 400 µA VEN = 5 V, 3 V Communication blocked (see Figure 7) Thermal Shutdown (Junction Temperature) 5.4.10 Thermal shutdown temp. 5.4.11 Thermal shutdown temp. Receiver Output RxD Transmission Input TxD 5.4.18 TxD low level leakage current Wake = VS 5.4.19 TxD dominant current Wake = 0 V; VS = 12 V; standby mode VEN VEN VEN Enable Input EN 5.4.23 EN pull-down resistance 5.4.24 Enable inhibit high current Data Sheet 15 Rev 2.1, 2007-04-27 TLE7259G General Product Characteristics Table 7 Electrical Characteristics (cont’d) 7.0 V < VS < 27 V; RL = 500 Ω; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Pos. Parameter Symbol Limit Values Unit Remarks IINH = -15 mA VINH = 0 V Min. Typ. Max. RINH,on IINH 22 36 50 Ω -150 – -40 mA IINH,lk -5.0 – 5.0 µA VWK,H VWK,L VS - 1 – -0.3 – Inhibit Output INH 5.4.25 Inhibit Ron resistance 5.4.26 Maximum INH output current 5.4.27 Leakage current sleep mode; VINH = 0 V Wake Input WK 5.4.28 High level input voltage 5.4.29 Low level input voltage VS + 3 V VS -3.3 V – – V -60 -30 -3 µA – 5.4.31 High level leakage current IWK,PU IWK,L -5 – 5 µA VS = 0 V; VWK = 40 V 5.4.32 Dominant time for wake-up tWK 30 – 150 µs – 0.4 x VS 0.48 × – V – 0 – 0.4 x VS V LIN Spec 2.1 Param. 17 – 0.52 × 0.6 x VS V VS VBUS,rec < VBUS < 27 V – VS V LIN Spec 2.1 Param. 18 LIN Spec 2.1 Param. 19 5.4.30 Pull-up current Bus Receiver 5.4.33 Receiver threshold voltage, Vth,rd recessive to dominant edge 5.4.34 Receiver dominant state VBUSdom 5.4.35 Receiver threshold voltage, Vth,dr dominant to recessive edge VS 5.4.36 Receiver recessive state VBUSrec 0.6 x VS 5.4.37 Receiver center voltage VBUS_CNT 0.475 × 0.5 × 0.525 × V VS VS VS 5.4.38 Receiver hysteresis VHYS 0.02 × 0.04 × 0.1 × VS VS VS VBUS,wk 0.40 × 0.5 × 0.6 × VS VS VS tWK,bus 30 – 150 5.4.39 Wake-up threshold voltage 5.4.40 Dominant time for bus wake-up Data Sheet 16 V LIN Spec 2.1 Param. 20 2) V – µs – Rev 2.1, 2007-04-27 TLE7259G General Product Characteristics Table 7 Electrical Characteristics (cont’d) 7.0 V < VS < 27 V; RL = 500 Ω; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Pos. Parameter Symbol Limit Values Min. Typ. Max. 0.8 × – VS 0.8 – – – 1.2 0.2 x VS 2.0 0.6 0.8 – – 1.2 2.0 40 100 150 Unit Remarks V VTxD = high Level V VTxD = 0 V; RL = 500 Ω; 6.0 V ≤ VS ≤ 7.3 V 7.3 V < VS ≤ 10 V 10 V < VS ≤ 18 V VTxD = 0 V; RL = 1000 Ω; VS = 7.3 V; VS = 18 V; VBUS = 13.5 V; Bus Transmitter 5.4.41 Bus recessive output voltage VBUS,ro 5.4.42 Bus dominant output voltage maximum load VBUS,do VS 0.6 5.4.43 Bus dominant output voltage minimum load VBUS,do 5.4.44 Bus short circuit current IBUS_LIM V mA LIN Spec 2.1 Param. 12 5.4.45 Leakage current IBUS_NO_GND -500 -70 0 µA 5.4.46 Leakage current IBUS_NO_BAT – 5 8 µA VS = 0 V; VBUS = -12V; LIN Spec 2.1 Param. 15 VS = 0 V; VBUS = 18 V; LIN Spec 2.1 Param. 16 5.4.47 Leakage current IBUS_PAS_dom -1 – – mA VS = 18 V; VBUS = 0 V; LIN Spec 2.1 Param. 13 5.4.48 Leakage current IBUS_PAS_rec – – 20 µA VS = 8 V; VBUS = 18 V; LIN Spec 2.1 Param. 14 5.4.49 Bus pull-up resistance RSLAVE 20 30 47 kΩ Normal mode LIN Spec 2.1 Param. 26 5.4.50 LIN output current IBUS -60 -30 -5 µA Sleep mode VS = 12V; EN = 0V Data Sheet 17 Rev 2.1, 2007-04-27 TLE7259G General Product Characteristics Table 7 Electrical Characteristics (cont’d) 7.0 V < VS < 27 V; RL = 500 Ω; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Remarks 3) Dynamic Transceiver Characteristics 5.4.51 Slew rate falling edge tfslope -3 – -1 V/µs 60% > Vbus > 40%; 1 µs < (τ = RL × CBUS) < 5 µs; VS = 13.5 V; normal mode; 5.4.52 Slew rate rising edge trslope 1 – 3 V/µs 3) 40% < Vbus < 60%; 1 µs < (τ = RL × CBUS) < 5 µs; VS = 13.5 V; normal mode; 5.4.53 Slope symmetry tslopesym -5 – 5 µs 5.4.54 Propagation delay TxD LOW to bus td(L),T 0.1 1 4 µs tfslope - trslope; VS = 13.5 V; VEN = 5 V; 5.4.55 Propagation delay TxD HIGH to bus td(H),T 0.1 1 4 µs VEN = 5 V; 5.4.56 Propagation delay bus dominant to RxD LOW td(L),R 0.1 1 6 µs 5.4.57 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 1 6 µs tsym,R 5.4.59 Transmitter delay symmetry tsym,T -2 – 2 µs -2 – 2 µs VCC = 5 V; CRxD = 20 pF; RRxD = 2.4 kΩ; VCC = 5 V; CRxD = 20 pF; RRxD = 2.4 kΩ; tsym,R = td(L),R - td(H),R; tsym,T = td(L),T - td(H),T 5.4.58 Receiver delay symmetry 5.4.60 Delay time for change sleep/stand by mode normal mode tsnorm 0.1 – 10 µs – 5.4.61 Delay time for change normal mode - sleep mode tnsleep 0.1 – 10 µs – 5.4.62 TxD dominant time out ttimeout 6 12 20 ms VTxD = 0 V 5.4.63 TxD dominant time out recovery time ttorec 1 5 10 µs 1) Data Sheet 18 Rev 2.1, 2007-04-27 TLE7259G General Product Characteristics Table 7 Electrical Characteristics (cont’d) 7.0 V < VS < 27 V; RL = 500 Ω; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Pos. Parameter Symbol Limit Values Unit Remarks Min. Typ. Max. 5.4.64 Duty cycle D1 tduty1 (for worst case at 20 kBit/s) 0.396 – – duty cycle 1 3) THRec(max) = 0.744 × VS; THDom(max) =0.581 × VS; VS = 7.0 … 18 V; tbit = 50 µs; D1 = tbus_rec(min)/2 tbit; LIN Spec 2.1 Param. 27 5.4.65 Duty cycle D2 tduty2 (for worst case at 20 kBit/s) – – 0.581 duty cycle 2 3) THRec(max) = 0.422 × VS; THDom(max) = 0.284 × VS VS = 7.6 … 18 V; tbit = 50 µs; D2 = tbus_rec(max)/2 tbit; LIN Spec 2.1 Param. 28 1) Not subject to production test, specified by design 2) VHYS = VBUSrec - VBUSdom 3) Bus load concerning LIN Spec 2.1 Load 1 = 1 nF / 1 kΩ = CBUS / RBUS Load 2 = 6.8 nF / 660 Ω = CBUS / RBUS Load 3 = 10 nF / 500Ω = CBUS / RBUS Data Sheet 19 Rev 2.1, 2007-04-27 TLE7259G Diagrams 6 Diagrams VS EN 100 nF INH VµC TxD RL RRxD RxD CRxD Bus CBus Figure 8 GND WK Test Circuits 97[' 9&& *1' WG/7 9%XV WG+7 W 96 9%XVUG 9%XVGU WG/5 WG+5 *1' WG/75 95[' W WG+75 9&& [9&& [9&& *1' W $(769* Figure 9 Data Sheet Timing Diagrams for Dynamic Characteristics according to LIN 1.3 20 Rev 2.1, 2007-04-27 TLE7259G Diagrams W%LW 7[' W%LW W%LW LQSXWWR WUDQVPLWWLQJQRGH W%XVBGRPPD[ 9683 7UDQVFHLYHUVXSSO\ RIWUDQVPLWWLQJ QRGH W%XVBUHFPLQ 7+5HFPD[ 7+'RPPD[ 7KUHVKROGVRI UHFHLYLQJQRGH 7+5HFPLQ 7+'RPPLQ 7KUHVKROGVRI UHFHLYLQJQRGH W%XVBGRPPLQ W%XVBUHFPD[ 5[' RXWSXWRIUHFHLYLQJ QRGH WU[BSGI WU[BSGU 5[' RXWSXWRIUHFHLYLQJ QRGH WU[BSGU Figure 10 Data Sheet WU[BSGI Timing Diagrams for Duty cycle measurements according to LIN 2.1 21 Rev 2.1, 2007-04-27 TLE7259G Application Information 7 Application Information 7.1 ESD Robustness according to IEC61000-4-2 Test for ESD robustness according to IEC61000-4-2 “Gun test” (150 pF, 330 Ω) have been performed. The results and test conditions are available in a seperate test report. Table 8 ESD “Gun test” Performed Test Result Unit Remarks Electrostatic discharge voltage at pin VS, Bus, Wk ≥ +8 versus GND kV 1) Electrostatic discharge voltage at pin VS, Bus, Wk ≤ -8 versus GND kV 1) Positive pulse Negative pulse 1) ESD susceptibility “ESD GUN” according LIN EMC 1.3 Test Specification, Section 4.3. (IEC 61000-4-2) -Tested by external testhouse (IBEE Zwickau, EMC Testreport Nr. 16-05-06). 7.2 Master Termination To achieve the required timings for the dominant to recessive transition of the bus signal an additional external termination resistor of 1 kΩ is mandatory. It is recommended to place this resistor at the master node. To avoid reverse currents from the bus line into the battery supply line it is recommended to place a diode in series with the external pull-up. For small systems (low bus capacitance) the EMC performance of the system is supported by an additional capacitor of at least 1 nF in the master node (see Figure 11 and Figure 12, application circuit). 7.3 External Capacitors A capacitor of 22 µF at the supply voltage input VS buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line. The 100 nF capacitors close to the VS pins of the TLE7259G and the voltage regulator help to improve the EMC behavior of the system. Data Sheet 22 Rev 2.1, 2007-04-27 TLE7259G Application Information 7.4 Application Example VBat LIN Bus VµC Master Node VS TLE7259 EN RxD TxD 100 nF 1 kΩ µC Bus 1 nF INH GND WK GND 100 nF VQ INH 5V e. g. TLE4263 22 µF VI 22 µF GND 100 nF ECU 1 VµC Slave Node TLE7259 VS EN RxD TxD 100 nF 220 pF µC Bus INH GND WK GND 100 nF VQ INH 5V e. g. TLE4263 VI 22 µF 22 µF GND ECU X 100 nF AEA03511.VSD Figure 11 Data Sheet Application Circuit with Bus Short to GND Feature Applied 23 Rev 2.1, 2007-04-27 TLE7259G Application Information VBat LIN Bus VµC Master Node VS TLE 7259 EN RxD TxD 100 nF 1 kΩ µC Bus 1 nF INH GND WK 100 nF 5V VQ INH GND e. g. TLE 4263 22 µF VI 22 µF GND 100 nF ECU 1 VµC Slave Node TLE 7259 VS EN RxD TxD 100 nF Bus VS 220 pF INH µC GND WK VQ INH 100 nF GND 5V e. g. TLE 4263 VI 22 µF 22 µF GND 100 nF ECU X AEA03512NEW.VSD Figure 12 Data Sheet Application Circuit without Bus Short to GND Feature 24 Rev 2.1, 2007-04-27 TLE7259G Package Outlines 8 Package Outlines 0.33 ±0.08 x 45˚ Index Marking 0.2 8 5 1 4 5 -0.21) M 8˚ MAX. .01 C 0.1 0.41 +0.1 -0.05 0.2 +0.05 -0 1.75 MAX. 0.1 MIN. (1.5) 1.27 4 -0.21) 0.64 ±0.25 A C x8 6 ±0.2 A Index Marking (Chamfer) 1) Does not include plastic or metal protrusion of 0.15 max. per side GPS09032 Figure 13 P-DSO-8 (Plastic Dual Small Outline) For further information on alternative packages, please visit our website: http://www.infineon.com/packages Dimensions in mm Data Sheet 25 Rev 2.1, 2007-04-27 TLE7259G Revision History 9 Revision History Version Date Changes Rev 2.0 2006-07-19 Creation of Data sheet Rev. 2.1 2007-04-30 Changes are described in a seperate Delta Sheet for TLE7259G Revision 1.0 Data Sheet 26 Rev 2.1, 2007-04-27 Edition 2007-04-27 Published by Infineon Technologies AG 81726 Munich, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.