SC2545
High Performance Wide Input Range
Dual Synchronous Buck Controller
POWER MANAGEMENT
Description
Features
The SC2545 is a high performance dual PWM controller.
It is designed to convert a wide ranged input voltage down
to two independent output rails. The SC2545 support
“peel off ” tracking for the two outputs at start up which
means the two outputs ramp up together till the one
with lower output level reaching the regulation. The PWM
operations of the two channels are 180 degree out of
phase which can greatly reduce the size and the cost of
the input capacitors. Synchronous Buck PWM topology
and voltage mode control allow high efficiency operation,
fast transient responses, and flexible component selection for easy designs. A 10V internal linear regulator provides the bias for the controller, and this voltage is optimized for gate drivers to deliver high efficiency. The power
sequencing is fully supported including independent start
up, and power good output. In the shut down mode the
controller only draws 100nA from the supply. The controller also offers full protection features for the conditions of under voltage, over voltage, and the over current.
There is no need for a current sensing resistor because
the MOSFET on resistance is used for the sensing
element. The switching frequency is adjustable from 100
kHz to 300 kHz. Two packages TSSOP-24 and MLPQ-24
are offered.
Independent dual-outputs
“Peel off “start up trackingIndependent dual-outputs
Wide input voltage range: 4.5V~28V
Adjustable output voltage down to 0.75V
Flexible power sequencing with enable and power
good output
Synchronous Buck topology with voltage mode
control
Out of phase operation to reduce cost of input
capacitor
10V internal regulator for gate driver to deliver high
efficiency
Programmable switching frequency:
100kHz~300kHz
Full protection: UVLO, OVP and programmable
OCP
No need for current sense resistor
Low shutdown current (100nA typical)
24 lead TSSOP and MLPQ packages
Fully WEEE and RoHS Compliant
Applications
Systems with 4.5V~28V input
LCDTV and PDPTV
Network and telecom systems
Typical Application Circuit
SC2545
VIN+
VO1
1
VCC
2
3
ENABLE
4
FB1
5
6
VIN+
7
8
VO1
9
10
11
FB1
12
VIN
AGND
VCC
ROSC
EN
PWRGD
FB1
FB2
ERROUT1
ERROUT2
SS1
SS2
ILIM1
ILIM2
BST1
BST2
DRVH1
DRVH2
PHASE1
PHASE2
DRVL1
DRVL2
PGND
PVCC
24
23
22
PWGRD
21
FB2
20
19
VIN+
18
17
16
VO2
15
14
13
VCC
FB2
Pinout shown as TSSOP-24.
Revision: August 10, 2005
1
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SC2545
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction.
Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
U nits
BST1, BST2 to PGND
V b st
38
V
VIN to PGND
Vin
28
V
VIN
V
14
V
+/- 0.3
V
-0.3 to 14
V
-0.3 to VC C
V
-3
V
ILIM1, ILIM2 and EN to PGND
VC C and PVC C to PGND
PGND to AGND
BST1 to PH1, BST2 to PH2, D RVH1 to PH1, D RVH2 to PH2
D RVL1, D RVL2 to PGND
PHASE, D RVL to AGND pulse (100nS), peak voltage
All Other Pi ns to AGND
-0.3 to VC C
V
TSTG
-60 to +150
o
TJ
-40 to +150
o
C
TLEAD
260
o
C
Thermal Resi stance Juncti on to C ase
TSSOP-24
MLP-24
θJC
23
2
o
C /W
Thermal Resi stance Juncti on to Ambi ent
TSSOP-24
MLP-24
θJA
78
25
o
C /W
ESD
TBD
Storage Temperature Range
Juncti on Temperature
Lead Temperature (Solderi ng) 10 Sec for TSSOP-24
Lead Temperature (IR Reflow) for MLPQ-24
ESD Rati ng (Human Body Model)
C
kV
Note: This device is ESD sensitive. Use of standard ESD handling precautions is required.
Electrical Characteristics
o
Unless specified: TA = 25 C, VIN=16V, Fs=200kHz .
Parameter
Test C onditions
Min
Typ
Max
U nit
4.5
V
U ndervoltage Lockout
Start Threshold
Vcc ri si ng
UVLO Hysteresi s
Vcc falli ng
200
SS1/SS2/EN =Hi gh, FS=200kHz
6.0
VIN > 12V
10
V
I_load=0~20mA
2
%
Vi n=12~24V
2
%
200KHz, 1nF on HG, 1nF on LG
14
mA
EN=low
0.1
Li ne Regulati on
5V<Vi n <28V
0.5
%
Load Regulati on
0A<load current <10A
0.5
%
mV
Pow er Supply
Operati ng C urrent (I IN-IPVCC)
Vcc Regulated
Vcc Load Regulati on Level
Vcc Li ne Regulati on
PVcc Operati ng C urrent
D i sable Qui escent C urrent
10
mA
10
uA
Main Sw itcher output
Output Voltage Accuracy
2005 Semtech Corp.
Wi thout feedback attenuati on ,
TA = -40 oC to +85 oC
2
0.735
0.750
0.765
V
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SC2545
POWER MANAGEMENT
Electrical Characteristics (Cont.)
o
Unless specified: TA = 25 C, VIIN=16V, Fs=200kHz
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SC2545
POWER MANAGEMENT
Electrical Characteristics (Cont.)
o
Unless specified: TA = 25 C, VIN=16V, Fs=200kHz
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Ordering Information
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Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free package. Device is fully WEEE and RoHS compiant.
Pin Configurations
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MLPQ-24
ã 2005 Semtech Corp.
4
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SC2545
POWER MANAGEMENT
Pin Descriptions for SC2545TSTRT (TSSOP)
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SC2545
POWER MANAGEMENT
Pin Descriptions for SC2545MLTRT (MLPQ)
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6
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SC2545
POWER MANAGEMENT
Block Diagram (One PWM channel
shown)
PVCC
BST
Protect 1
DRVH
PHASE
ROSC
Ramp1
Oscillator
Ramp
generator
3
PHASE1
PVCC
+
PWM
2
PVCC
1
-
S
DRVL
Q
CLK1
R
Protect 1
ERROUT
FB
FB
-
E/A
0.65V
0.75V
+
OUT
+
SS
OUT
+
OUT -
Clamp
VCC
R
S
R
R
/Q
Protect 1
10u A
UVLO
ILIM
OCP
OUT
+
VCC
VCC
+
OVP
VIN
OUT
-
ENABLE
EN
ON/OFF
VCC
0.89V
0.75V
Band
Gap 1
10V
LDO
Band
Gap 2
PWRGD
0.75V
0.675V
FB1
UVLO
FB2
AGND
© 2005 Semtech Corp.
FB1
7
+
-
OUT
OVP
OCP
-
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SC2545
POWER MANAGEMENT
Applications Information
Sof t Star t and ”P
P eel of f ”T
Tracking
Overview
The SC2545 is a constant frequency 2-phase voltage
mode step-down PWM switching controller driving all Nchannel MOSFETs. The two channels of the controller
operate at 180 degree out of phase from each other.
Since input currents are interleaved in a two-phase
converter, input ripple current is lower and smaller input
capacitance can be used for filtering. Also, with lower
inductor current and smaller inductor ripple current per
phase, overall I2 R losses are reduced.
During start-up, the reference voltage of the error
amplifier equals 30% of the voltage on Css (soft-start
capacitor) which is connected between the SS pin and
ground. When the controller is enabled (by pulling EN
pin high), one internal 84uA current source, ISS, (soft
start current) will charge the soft-start capacitor
gradually. The PWM output starts pulsing when the
soft start voltage reaches 1V.
This soft start scheme will ensure the duty cycle to
increase slowly, therefore limiting the charging current
into the output capacitor and also ensuring the
inductor does not saturate. The soft start capacitor
will eventually be charged up to 2.5V.
F req
uency Se
tting
requency
Setting
The frequency of the SC2545 is user- programmable.
The oscillator of SC2545 can be programmed with an
external resistor from the Rosc pin to the ground. The
step-down controller is capable of operating up to
300kHz. The relationship between oscillation frequency
versus oscillation resistor is shown in Figure 1.
The soft-start sequence is initiated when EN pin is high
and Vcc >4.5V or during recovery from a fault condition
( OCP, OVP, or UVLO).
The advantages of using constant frequency operation
are simple passive component selection and ease of
feedback compensation. Before setting the operating
frequency, the following trade-offs should be considered.
1) Passive component size
2) Circuitry efficiency
3) EMI condition
4) Minimum switch on time
5) Maximum duty ratio
For a given output power, the sizes of the passive
components are inversely proportional to the switching
frequency, whereas MOSFETs/Diodes switching losses
are proportional to the operating frequency. Other issues
such as heat dissipation, packaging and cost issues are
also to be considered. The frequency bands for signal
transmission should be avoided because of EM
interference.
The period of start up can be programed by the soft
start capacitor:
Tss =
By tieing the two soft start pins together, the two
output rails track each other at start up till the rail with
lower set level reaching regulation. Please refer the
waveform on page 20.
Shutdown
When the EN pin is pulled low, an internal 15uA current
source discharges the soft-start capacitor and DRVH/
DRVL signals stop pulsing. The output voltage ramps
down at a rate determined by the load condition.
The SC2545 can also be shutdown by pulling down
directly on the SS pin. The designer needs to consider
the slope of the SS pin voltage and choose a suitable
pull down resistor to prevent the output from
undershooting.
350
300
Fsw(KHz)
Css × 2.5V
84 µA
250
Shutdown can also be triggered when an OCP condition
occurs. When an OCP condition is detected, DRVH and
DRVL will stop pulsing and enter a “tri-state shutdown”
with the output voltage ramping down at a rate determined by the load condition. The internal 15uA current
source will begin discharging the soft-start capacitor
and when the soft-start voltage reaches 0.65V, DRVL
will go high.
200
150
100
50
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
Rosc(KOHM)
Figure 1. Switching frequency versus Rosc.
© 2005 Semtech Corp.
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SC2545
POWER MANAGEMENT
Applications Information (Cont.)
Over Current Protection (OCP)
The inductor current is sensed by using the low side
MOSFET Rds(on) . After low side MOSFET is turned on,
the OCP comparator starts monitoring the voltage
drop across the MOSFET. The OCP trip level is programmed by the resistor from the ILIM pin to the
phase node. There is an internal current source that
flows out of the ILIM pin which will generate a voltage
drop on the setting resistor. When the sum of the
setting resistor voltage and the MOSFET drain to
source voltage is less then zero, the OCP condition will
be flagged. This functionality is depicted in Figure 2.
The following formula is used to set the OCP level
TG
IL
100nS
Blanking
Figure 3. OCP comparator timing chart.
U nder V
oltage Lock Out (UVL
O)
Voltage
(UVLO)
10 µ A × RILIM = I L _ PEAK × RDS ( ON )
The UVLO circuitry monitors Vcc and the soft start
begins once Vcc ramps up above 4.5V. There is a built
in 200mV hysteresis for the UVLO ramp down
threshold. The gate driver output will be in “tri-state”
(both high side and low side MOSFET off) once Vcc
ramps down bellow 4.2V (typical), and the soft start
cap will be discharged by internal 15uA current sink.
When OCP is tripped, both high side and low side
MOSFETs will be turned off and this condition is
latched. At the same time, the soft start cap will be
discharged by the internal current source of 15uA.
When the Vss drops bellow 0.65V, the DRVL pin will go
high again.
Ov
er V
oltage Pr
o t ection (O
VP)
Over
Voltage
Pro
(OVP)
To avoid switching noise during the phase node
commutation, a 100nS blanking time is built in after
the low side MOSFET is turned on, as shown in Fig. 3.
The OVP circuitry monitors the feedback voltages, If
either feedback voltage exceeds 0.89V, the OVP
condition is registered. Under this condition, the DRVH
pins will be pulled low, and the DRVL pins will be pulled
high. This will create a “crow bar” condition for the
input power rail in case the high side MOSFET is failed
short. The crow bar operation may trip the input supply
to prevent the load from seeing more voltage.
VCC
10uA
+
OCP
DRVH
ILIM
OCP Active
OUTPUT
Power Good Output
Out
-
DRVL
The power good is an open collector output. The
PWRGD pin is pulled low at start up if any of the two
feedback voltages below 90% of its regulation level.
The ramp down threshold of the signal is 80% of the
regulation target. External pull up is required for the
PWRGD pin, and the pull up resistor should be chosen
such that the pin does not sink more than 2mA when
PWRGD is low.
Figure 2. Block diagram of over current
protection.
© 2005 Semtech Corp.
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SC2545
POWER MANAGEMENT
Applications Information (Cont.)
,/UPV
General Design Procedure for a Step-down Power
Converter
The following step-down converter specifications are
needed:
Input voltage range: Vin,min and Vin,max
Input voltage ripple (peak-to-peak): DVin
Output voltage: Vo
Output voltage accuracy: e
Output voltage ripple (peak-to-peak): DVo
Nominal output (load) current: Io
Maximum output current limit: Io,max
Output (load) current transient slew rate: dIo (A/ s)
Circuit efficiency: K
Output Capacitor (C o) and V out Ripple
Inductor (L) and Ripple Current
The output capacitor provides output current filtering in
steady state and serves as a reservoir during load
transient. The output capacitor can be modeled as an
ideal capacitor in series with its parasitic ESR and ESL
as shown in Figure 4.
Both step-down controllers in the SC2545 operate in
synchronous continuous-conduction mode (CCM)
regardless of the output load level. The output inductor
selection/design is based on the output DC and transient
requirements. Both output current and voltage ripples
are reduced with larger inductance but it takes longer to
change the inductor current during load transients.
Conversely smaller inductance results in lower DC copper
losses but the AC core losses (flux swing) and the winding
AC resistance losses are higher. A compromise is to
choose the inductance such that peak-to-peak inductor
ripple-current is 20% to 30% of the rated output load
current.
Assuming that the inductor current ripple (peak-to-peak)
value is
*Io, the
G inductance value will then be
&R
ã 2005 Semtech Corp.
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If the current through the branch is i b(t), the voltage
across the terminals will then be
9R '
G,R IV
W
YR W 9R /2)*Io
and the RMS current is
/HVO
Figure 4. An equivalent circuit of output.
The peak current in the inductor becomes
(1+
G
The followings are to be considered when choosing
inductors.
a) Inductor core material: For higher efficiency
applications above 300 kHz, ferrite, Kool-Mu and
polypermalloy materials should be used. Low-cost
powdered iron cores can be used for cost sensitiveapplications below 300 kHz but with attendant higher
core losses.
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The
designer can choose the adjacent (larger) standard
inductance value. The inductance varies with
temperature and DC current. It is a good engineering
practice to re-evaluate the resultant current ripple at
the rated DC output current.
c) Current rating: The saturation current of the inductor
should be at least 1.5 times of the peak inductor current
under all conditions.
Selection criterias and design procedures for the following parameters are described:
1) Output inductor (L) type and value
2) Output capacitor (Co) type and value
3) Input capacitor (Cin) type and value
4) Power MOSFETs
5) Current sensing and limiting circuit
6) Voltage sensing circuit
7) Loop compensation network
/
,R GL W
LE WGW /HVO E 5HVULE W
GW
&R ³
This basic equation illustrates the effects of ESR, ESL,
and Co on the output voltage.
G
10
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SC2545
POWER MANAGEMENT
Applications Information (Cont.)
The voltage rating of aluminum capacitors should be at
least 1.5Vo. The RMS current ripple rating should also
be greater than
The first term is the DC voltage across Co at time t=0.
The second term is the voltage variation caused by the
charge balance between the load and the converter
output. The third term is voltage ripple due to ESL and
the fourth term is the voltage ripple due to ESR. The
total output voltage ripple is then a vector sum of the
last three terms.
δIo
2 3
Usually it is necessary to have several capacitors of the
same type in parallel to satisfy the ESR requirement.
The voltage ripple caused by the capacitor charge/
discharge should be an order of magnitude smaller than
the voltage ripple caused by the ESR. To guarantee this,
the capacitance should satisfy
Since the inductor current is a triangular waveform with
peak-to-peak value δ *Io, the ripple-voltage caused by
inductor current ripples is
∆vC ≈
Co >
δIo
,
8Cofs
δ Io
,
D
and the ESR ripple-voltage is
Remark 1: High frequency ceramic capacitors may
not carry most of the ripple current. It also depends on
the capacitor value. Only when the capacitor value is set
properly, the effect of ceramic capacitor low ESR starts
to be significant. For example, if a 10 µ F, 4m Ω ceramic
capacitor is connected in parallel with 2x1500 µ F,
90m Ω electrolytic capacitors, the ripple current in the
ceramic capacitor is only about 42% of the current in the
electrolytic capacitors at the ripple frequency. If a 100 µ F,
2m Ω ceramic capacitor is used, the ripple current in
the ceramic capacitor will be about 4.2 times of that in
the electrolytic capacitors. When two 100 µ F, 2m Ω
ceramic capacitors are used, the current ratio increases
to 8.3. In this case most of the ripple current flows in
the ceramic decoupling capacitor. The ESR of the ceramic
capacitors will then determine the output ripple-voltage.
∆vESR = ResrδIo .
Aluminum capacitors (e.g. electrolytic) have high
capacitances and low ESLs. The ESR has the dominant
effect on the output ripple voltage. It is therefore very
important to minimize the ESR. Other types to choose
are solid OS-CON, POSCAP, and tantalum.
When determining the ESR value, both the steady state
ripple-voltage and the dynamic load transient need to be
considered. To meet the steady state output ripplevoltage spec, the ESR should satisfy
Re sr1〈
∆VO
δ IO
To limit the dynamic output voltage overshoot/
undershoot within a (say 3%) of the steady state output
voltage from no load to full load, the ESR value should
satisfy
Re sr 2〈
Remark 2: The total equivalent capacitance of the filter
bank is not simply the sum of all the paralleled capacitors.
The total equivalent ESR is not simply the parallel
combination of all the individual ESR’s either. Instead
they should be calculated using the following formula.
3%VO
IO
2
Then, the required ESR value of the output capacitors
should be
Resr = min{Resr1,Resr2 }.
2005 Semtech Corp.
10
.
2πfsR esr
In many applications, several low ESR ceramic
capacitors are added in parallel with the aluminum
capacitors in order to further reduce ESR and improve
high frequency decoupling. Because the values of
capacitance and ESR are usually different in ceramic and
aluminum capacitors, the following remarks are made
to clarify some practical issues.
the ripple-voltage due to ESL is
∆ v ESL = L esl f s
.
Ceq( ω ) =
11
2
(R1a + R1b )2 ω2C1a C1b + (C1a +C1b )2
2
2
(R1a C1a + R1b C1b )ω2C1aC1b + (C1a + C1b )
www.semtech.com
SC2545
POWER MANAGEMENT
Applications Information (Cont.)
In Figure 6 the DC input voltage source has an internal
impedance Rin and the input capacitor Cin has an ESR of
Resr. MOSFET and input capacitor current waveforms, ESR
voltage ripple and input voltage ripple are shown in Figure
7.
R1aR1b (R1a + R1b )ω2 C1a C1b + (R1b C1b + R1a C1a )
2
(ω))=:=
CReqeq(ω
2
2
2
(R1a + R1b ) ω C1a C1b + (C1a + C1b )
2
2
2
2
2
where R 1a and C 1a are the ESR and capacitance of
electrolytic capacitors, and R1b and C1b are the ESR and
capacitance of the ceramic capacitors, respectively
(Figure 5).
i Q1
C1a
C1b
Ceq
R1a
R1b
Req
i Cin
Vesr
Figure 5. Equivalent RC branch.
VCin
Req and Ceq are both functions of frequency. For rigorous
design, the equivalent ESR should be evaluated at the
ripple frequency for voltage ripple calculation when both
ceramic and electrolytic capacitors are used. If R1a = R1b
= R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and
Figure 7. Typical waveforms at converter input.
It can be seen that the current in the input capacitor
pulses with high di/dt. Capacitors with low ESL should be
used. It is also important to place the input capacitor
close to the MOSFETs on the PC board to reduce trace
inductances around the pulse current loop.
Req = 1/2 R1 and Ceq = 2C1.
Input Capacitor (Cin)
The RMS value of the capacitor current is approximately
The input supply to the converter usually comes from a
pre-regulator. Since the input supply is not ideal, input
capacitors are needed to filter the current pulses at the
switching frequency. A simple buck converter is shown in
Figure 6.
ICin = Io D[(1 +
δ2
D
D
)(1 − )2 + 2 (1 − D) ].
12
η
η
The power dissipated in the input capacitors is then
PCin = ICin2Resr.
2
1
L1
For reliable operation, the maximum power dissipation
in the capacitors should not result in more than 10oC of
temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS) rating of the
capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be high
enough to handle the ripple current. It is common pratice
that multiple capacitors are placed in parallel to increase
the ripple current handling capability.
Rin
Resr
2
Q1
D1
Ro
1
Co
VDC
Cin
Figure 6. A simple model for the converter input.
© 2005 Semtech Corp.
12
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SC2545
POWER MANAGEMENT
Applications Information (Cont.)
Choosing Power MOSFETs
Main considerations in selecting the MOSFETs are power
dissipation, MOSFETs cost, and packaging. Switching
losses and conduction losses of the MOSFETs are
directly related to the total gate charge (Cg) and channel
on-resistance (Rds(on)). In order to judge the performance
of MOSFETs, the product of the total gate charge and
on-resistance is used as a figure of merit (FOM).
Transistors with the same FOM follow the same curve in
Figure 8.
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input voltage
ripple due to the ESR is
'Y (65
G
5 HVU ,R The peak-to-peak input voltage ripple due to the capacitor
is
'Y & |
',R
&LQ IV
From these two expressions, CIN can be found to meet
the input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce
ripple. The two step-down channels of the SC2545
operate at 180 degrees from each other. If both stepdown channels in the SC2545 are connected to the same
input rail, the input RMS currents will be reduced. Ripple
cancellation effect of interleaving allows the use of
smaller input capacitors.
&
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WD &J *
When two channels with a common input are interleaved,
the total DC input current is simply the sum of the
individual DC input currents. The combined input current
waveform depends on duty ratio and the output current
waveform. Assuming that the output current ripple is
small, the following formula can be used to estimate the
RMS value of the ripple current in the input capacitor.
5GV 5GV
2QUHVLVWDQFHP2KP
MOSFET selection also depends on applications. In many
applications, either switching loss or conduction loss
dominates for a particular MOSFET. For synchronous buck
converters with high input to output voltage ratios, the
top MOSFET is hard switched but conducts with very low
duty cycle. The bottom switch conducts at high duty cycle
but switches at near zero voltage. For such applications,
MOSFETs with low Cg are used for the top switch and
MOSFETs with low Rds(on) are used for the bottom switch.
If D1>0.5 and (D1-0.5) < D2<0.5, then
,&LQ | ,R ' ,R ,R ' ' ,R If D1>0.5 and D2 < (D1-0.5) < 0.5, then
MOSFET power dissipation consists of
a) conduction loss due to the channel resistance Rds(on);
b) switching loss due to the switch rise time tr and fall
time tf; and
c) the gate loss due to the gate resistance RG.
,&LQ | ,R ' ,R ,R ' ' ,R If D1>0.5 and D2 > 0.5, then
5GV The closer the curve is to the origin, the lower is the FOM.
This means lower switching loss or lower conduction loss
or both. It may be difficult to find MOSFETs with both
low Cg and low Rds(on. Usually a trade-off between Rds(on
and Cg has to be made.
,&LQ | ',R ' ,R Figure 8. Figure of Merit curves.
If D1<0.5 and D2<0.5, then
5GV )20A^`
)20A^`
)20A^`
Let the duty ratio and output current of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2, respectively.
,&LQ | ' ' ,R ,R ' ,R ' ,R ã 2005 Semtech Corp.
13
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SC2545
POWER MANAGEMENT
Applications Information (Cont.)
In Figure 9, Qgs1 is the gate charge needed to bring the
gate-to-source voltage Vgs to the threshold voltage Vgs_th.
Qgs2 is the additional gate charge required for the switch
current to reach its full-scale value I ds, and Q gd is the
.
charge needed to charge gate-to-drain (Miller) capacitance
when Vds is falling.
Top Switc
h
Switch
The RMS value of the top switch current is calculated as
The conduction losses are then
Ptc = IQ1,rms2 Rds(on).
Switching losses occur during the time interval [t1, t3].
Defining tr = t3-t1 and tr can be approximated as
Rds(on) varies with temperature and gate-source voltage.
Curves showing R ds(on) variations can be found in
manufacturers’ data sheet. From the Si4860 datasheet,
Rds(on) is less than 8m Ω when V gs is greater than 10V.
However R ds(on) increases by 50% as the junction
temperature increases from 25oC to 110oC.
tr =
Vcc − Vgsp
.
where Rgt is the total resistance from the driver supply
rail to the gate of the MOSFET. It includes the gate driver
internal impedance Rgi, external resistance Rge and the
gate resistance Rg within the MOSFET :
The switching losses can be estimated using the simple
formula
Rgt = Rgi+Rge+Rg.
Vgsp is the Miller plateau voltage shown in Figure 9.
Similarly an approximate expression for tf is
Pts = 21 ( t r + t f )(1 + 2δ )Io Vin fs .
where t r is the rise time and t f is the fall time of the
switching process. Different manufactures have different
definitions and test conditions for t and t . To clarify
r
f
these, we sketch the typical MOSFET switching
characteristics under clamped inductive mode in Figure
9.
tf =
(Q gs 2 + Q gd )R gt
Vgsp
.
Only a portion of the total losses Pg = QgVccfs is dissipated
in the MOSFET package. Here Qg is the total gate charge
specified in the datasheet. The power dissipated within
the MOSFET package is
Vds
Volts
(Q gs 2 + Q gd )R gt
Ids
Miller plateau
Ptg =
Vgs
Rg
R gt
Q g Vcc fs .
The total power loss of the top switch is then
Vgs th
Pt = Ptc+Pts+Ptg.
Qgs1 Qgs2
t0
t1
t2
Qgd
t3
If the input supply of the power converter varies over a
wide range, then it will be necessary to weigh the
relative importance of conduction and switching losses.
This is because conduction losses are inversely proportional to the input voltage. Switching loss however
increases with the input voltage. The total power loss
of MOSFET should be calculated and compared for
high-line and low-line cases. The worst case is then
used for thermal design.
Gate charge
Figure 9. MOSFET switching characteristics
© 2005 Semtech Corp.
14
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SC2545
POWER MANAGEMENT
Applications Information (Cont.)
Bottom Switch
The RMS current in bottom switch is given by
Main Control Loop Design
The goal of compensation is to shape the frequency response charatericstics of the buck converter to achieve
a better DC accuracy and a faster transient response
for the output voltage, while maintaining the loop stability.
G
,4UPV ,R ' The conduction losses are then
The block diagram in Figure 10 represents the control
loop of a buck converter designed with the SC2545. The
control loop consists of a compensator, a PWM modulator, and an LC filter.
Pbc=IQ2,rms2 Rds(on).
where Rds(on) is the channel resistance of bottom MOSFET.
If the input voltage to output voltage ratio is high (e.g.
Vin=12V, Vo=1.5V), the duty ratio D will be small. Since
the bottom switch conducts with duty ratio (1-D), the
corresponding conduction losses can be quite high.
The LC filter and PWM modulator represent the small
signal model of the buck converter operating at fixed
switching frequency. The transfer function of the model
is given by:
Due to non-overlapping conduction between the top and
the bottom MOSFETs, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the
bottom MOSFET. The bottom MOSFET switches on with
only a diode voltage between its drain and source
terminals. The switching loss is negligible due to near zerovoltage switching.
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Pb=Pbc+Pbg.
Fig. 10. Block diagram of the control loop.
Once the power losses for the top and bottom MOSFETs
are known, thermal and package design at component
and system level should be done to verify that the
maximum die junction temperature (Tj,max, usually 125oC)
is not exceeded under the worst-case condition. The
equivalent thermal impedance from junction to ambient
( T ja) should satisfy
T d
MD
7
MPD[
7
DPD[
3
where VIN is the input voltage, Vm is the amplitude of the
internal ramp, and R is the equivalent load.
The model is a second order system with a finite DC gain,
a complex pole pair at Fo, and an ESR zero at Fz, as
shown in Figure 11. The locations of the poles and zero
are determined by:
T ja depends on the die to substrate bonding, packaging
material, the thermal contact surface, thermal compound
property, the available effective heat sink area, and the
air flow condition (natual or forced convection). Actual
temperature measurement of the prototype should be
carried out to verify the thermal design.
ORVV
ã 2005 Semtech Corp.
15
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SC2545
POWER MANAGEMENT
Applications Information (Cont.)
The compensator in Figure 10 includes an error amplifier and impedance networks Zf and Zs. It is implemented
by the circuit in Figure 12. The compensator provides an
integrator, double poles, and double zeros. As shown in
Figure 11, the integrator is used to boost the gain at low
frequency. Two zeros are introduced to compensate excessive phase lag at the loop gain crossover due to
the integrator (-90deg) and the complex pole pair (180deg). Two high frequency poles are designed to compensate the ESR zero and to attenuate high frequency
noise.
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A resistive divider is used to program the output voltage.
The top resistor Rtop of the divider in Fig. 12 can be chosen from 20k : to 30k : . Then the bottom resistor
Rbot is found from:
5ERW
where 0.75V is the internal reference voltage of the
SC2545.
The other components of the compensator can be calculated using following design procedure:
(1). Plot the converter gain, including LC filter and PWM
modulator.
(2). Select the open loop crossover frequency Fc located
at 10% to 20% of the switching frequency. At Fc, find the
required DC gain.
(3). Use the first compensator pole Fp1 to cancel the
ESR zero Fz.
(4). Have the second compensator pole Fp2 at half the
switching frequency to attenuate the switching ripple and
high frequency noise.
(5). Place the first compensator zero Fz1 at or below
50% of the power stage resonant frequency Fo.
(6). Place the second compensator zero Fz2 at or below
the power stage resonant frequency Fo.
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Fig. 11. Bode plots for control loop design.
A MathCAD program is available upon request for the
calculation of the compensation parameters.
&
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9
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Fig. 12. Compensation network.
ã 2005 Semtech Corp.
16
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SC2545
POWER MANAGEMENT
Applications Information (Cont.)
PC Board Layout Issues
Circuit board layout is very important for the proper operation of high frequency switching power converters. A
power ground plane is required to reduce ground bounces.
The followings are suggested for proper layout.
Control Section
6) The frequency-setting resistor Rosc should be placed
close to Pin 23. Trace length from this resistor to the
analog ground should be minimized.
7) Place the bias decoupling capacitor right across the
VCC and analog ground AGND.
Power Stage
1) Separate the power ground from the signal ground. In
SC2545 design, use an isolated local ground plane for
the controller and tie it to power grand.
2) Minimize the size of the high pulse current loop. Keep
the top MOSFET, the bottom MOSFET and the input
capacitors within a small area with short and wide
traces. In addition to the aluminum energy storage
capacitors, add multi-layer ceramic (MLC) capacitors
from the input to the power ground to improve high
frequency bypass.
3) Reduce high frequency voltage ringing. Widen and
shorten the drain and source traces of the MOSFETs to
reduce stray inductances. Add a small RC snubber if
necessary to reduce the high frequency ringing at the
phase node. Sometimes slowing down the gate drive
signal also helps in reducing the high frequency ringing at
the phase node if the EMI is a concern for the system.
4) Shorten the gate drive trace. Integrity of the gate
drive (voltage level, leading and falling edges) is important
for circuit operation and efficiency. Short and wide gate
drive traces reduce trace inductances. Bond wire
inductance is about 2~3nH. If the length of the PCB
trace from the gate driver to the MOSFET gate is 1 inch,
the trace inductance will be about 25nH. If the gate drive
current is 2A with 10ns rise and falling times, the voltage
drops across the bond wire and the PCB trace will be
0.6V and 5V respectively. This may slow down the
switching transient of the MOSFETs. These inductances
may also ring with the gate capacitance.
5) Put the decoupling capacitor for the gate drive power
supplies (BST and PVCC) close to the IC and power
ground.
ã 2005 Semtech Corp.
17
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SC2545
POWER MANAGEMENT
Typical Application Circuit
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Vin: 4.5V ~ 28V
Vout: 3.3V/6A and 5V/6A
ã 2005 Semtech Corp.
18
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SC2545
POWER MANAGEMENT
Evaluation Board - Bill of Material
SC2544MLTRT
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ã 2005 Semtech Corp.
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www.semtech.com
SC2545
POWER MANAGEMENT
Typical Characteristics
CH1:
CH2:
CH3:
CH4:
CH1:Vi
CH2:Ven
CH3:VSS
CH4:Vo
TG1
BG1
TG2
BG2
Shut down by pulling down EN pin
voltage.
Gate waveform
CH1:TG
CH2:BG
CH3:VSS
CH4:Vo
CH3:Vo
CH4:Io
Start up.
Transient response(0-5A).
CH1:TG
CH2:BG
CH3:TG
CH4:BG
Vss
Vo1
Vo2
Over current protection (5A/10mV)
“Peel off “Start up tracking by
tieing SS1 and SS2 together.
© 2005 Semtech Corp.
20
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SC2545
POWER MANAGEMENT
Typical Characteristics (Cont.)
Vin=8V
Vin=16V
190
100%
188
Fs (khz)
Efficient
80%
60%
40%
184
182
180
20%
178
-40
0%
0
1
2
3
4
5
6
Io(A)
7
8
9
-10
10
20
50
110
Freq. vs. Temp. ( Rosc=75kohm, Vin=16V).
10.5
10.3
350
Vcc (V)
300
250
200
150
10.1
9.9
9.7
9.5
100
50
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
10 12 14 16 18 20 22 24 26 28 30
Vin (V)
Rosc(KOHM)
Operating frequency vs. Rosc.
Vcc vs. Vin ( Ta=25 Degree C).
9
10.13
8
10.11
Vcc (V)
Io(A)
80
Temperature (Degree C)
Efficiency Curve for Vout=3.3V.
Fsw(KHz)
186
7
6
10.09
10.07
5
10.05
4
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5
10.03
-40
0
20
40
60
80
100
120
Tj (Degree C)
RILIM(KOHM)
RILIM vs. OCP (Vi=12V).
© 2005 Semtech Corp.
-20
Vcc vs. Temp.
21
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SC2545
POWER MANAGEMENT
Typical Characteristics (Cont.)
7.0
Icc (mA)
6.5
6.0
5.5
5.0
8
10
12
14
16
18
20
22
24
26
28
Vin(V)
DRVL min Ton(nS)
Icc vs. Vin (25 DegreeC).
500
480
460
440
420
400
-40
-20
0
20
40
60
80
100 120
Tj (Degree C)
DL min Ton vs. Tj (Vin=16V).
Dead time (nS)
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100
120
Tj (Degree C)
Dead time vs. Tj (Vin=16V, DH falling to DL rising).
© 2005 Semtech Corp.
22
www.semtech.com
SC2545
POWER MANAGEMENT
Outline Drawing - TSSOP-24
A
DIM
D
e
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
N
2X E/2
E1
E
PIN 1
INDICATOR
ccc C
2X N/2 TIPS
1 2 3
e/2
B
.047
.002
.006
.042
.031
.007
.012
.003
.007
.303 .307 .311
.169 .173 .177
.252 BSC
.026 BSC
.018 .024 .030
(.039)
24
0
8
.004
.004
.008
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
7.70 7.80 7.90
4.30 4.40 4.50
6.40 BSC
0.65 BSC
0.45 0.60 0.75
(1.0)
24
0
8
0.10
0.10
0.20
D
aaa C
SEATING
PLANE
DIMENSIONS
MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX
A2 A
C
H
A1
bxN
bbb
c
GAGE
PLANE
C A-B D
0.25
L
(L1)
SEE DETAIL
SIDE VIEW
DETAIL
A
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-153, VARIATION AD.
Land Pattern - TSSOP-24
X
DIM
(C)
G
C
G
P
X
Y
Z
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
© 2005 Semtech Corp.
23
www.semtech.com
SC2545
POWER MANAGEMENT
Outline Drawing - MLPQ-24 (4 x 4mm)
A
D
B
DIM
PIN 1
INDICATOR
(LASER MARK)
Top View
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
E
A2
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.031 .035 .040
.000 .001 .002
- (.008) .007 .010 .012
.151 .157 .163
.100 .106 .110
.151 .157 .163
.100 .106 .110
.020 BSC
.011 .016 .020
24
.004
.004
0.80 0.90 1.00
0.00 0.02 0.05
- (0.20) 0.18 0.25 0.30
3.85 4.00 4.15
2.55 2.70 2.80
3.85 4.00 4.15
2.55 2.70 2.80
0.50 BSC
0.30 0.40 0.50
24
0.10
0.10
A
SEATING
PLANE
aaa C
A1
C
D1
LxN
E/2
Bottom View
E1
2
1
N
bxN
bbb
e
C A B
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPQ-24 (4 x 4mm)
K
(C)
G
H
DIM
C
G
H
K
P
X
Y
Z
Z
DIMENSIONS
INCHES
MILLIMETERS
(.155)
(3.95)
3.10
.122
.106
2.70
.106
2.70
.021
0.50
.010
0.25
.033
0.85
.189
4.80
X
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
© 2005 Semtech Corp.
24
www.semtech.com