INFINEON TLE6259-2

Final Datasheet, Version 2.06, 2003-02-21
LIN Transceiver
TLE 6259-2
Automotive and
Industrial
N e v e r
s t o p
t h i n k i n g .
Single-Wire-Transceiver
TLE 6259-2
Final Datasheet
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
Single-wire transceiver, suitable for LIN protocol
Transmission rate up to 20 kBaud
Compatible to LIN specification 1.2
Compatible to ISO 9141 functions
Very low current consumption in sleep mode
Control output for voltage regulator
Bus short to GND protection
Short circuit proof to ground and battery
Overtemperature protection
P-DSO-8-3, -6
Type
Ordering Code
Package
TLE 6259-2G
Q 67006 - A 9596
P-DSO-8-3
Description
The TLE 6259-2 is a monolithic integrated circuit in a P-DSO-8-3 package. It works as
an interface between the protocol controller and the physical bus. The TLE 6259-2 is
especially suitable to drive the bus line in LIN systems in automotive and industrial
applications. Further it can be used in standard ISO9141 systems. The TLE6259-2 has
a BUS short to GND feature implemented, to avoid a battery decharge.
In order to reduce the current consumption, the TLE 6259-2 offers a sleep operation
mode. In this mode a voltage regulator can be controlled to minimize the current
consumption of the whole application. A wake-up caused by a message on the bus,
enables the voltage regulator and sets the RxD output LOW until the device is switched
to normal operation mode.
The IC is based on the Smart Power Technology SPT® which allows bipolar and CMOS
control circuitry in accordance with DMOS power devices existing on the same
monolithic circuit.
The TLE 6259-2 is designed to withstand the severe conditions of automotive
applications.
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1.2
Pin Configuration (top view)
RxD
1
8
INH
EN
2
7
Vs
Vcc
3
6
Bus
TxD
4
5
GND
P-DSO-8-3
Figure 1
1.3
Pin Definitions and Functions:
Pin No.
Symbol
Function
1
RxD
Receive data output; integrated pull up, LOW in dominant state,
2
EN
Enable input; integrated 30 kW pull down, transceiver in normal
operation mode when HIGH
3
VCC
5V supply input;
4
TxD
Transmit data input; integrated pull up, LOW in dominant state
5
GND
Ground;
6
Bus
Bus output/input; internal 30 kW pull up, LOW in dominant state
7
Vs
Battery supply input;
8
INH
Inhibit output; to control a voltage regulator, becomes HIGH
when wake-up via LIN bus occurs
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1.4
Functional Block Diagram
Vs
7
30 k9
Bus
Output
Stage
Mode
Control
Driver
8
INH
3
Vcc
2
EN
4
TxD
1
RxD
5
GND
30 k9
6
Temp.Protection
Filter
Receiver
TLE 6259-2G
Figure 2
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1.5
Application Information
Start Up
Power Up
Normal Mode
EN
high
EN
INH
high
Vcc
ON
EN
low
high
Stand-By
EN
(VCC
high
ON)
EN INH RxD VCC
low high low1) ON
high3)
Sleep Mode
EN
low
1)
2)
3)
INH
VCC
floating OFF2)
Wake Up
t > tWAKE
after wake-up via bus
ON when INH not connected to voltage regulator
after start up
Figure 3: operation mode state diagram
Master Termination
For fail safe reasons, the TLE6259-2 already has a pull up resistor of 30kW implemented.
To achieve the required timings for the dominant to recessive transition of the bus signal
an additional external termination resistor of 1kW is required. It is recommended to place
this resistor in the master node. To avoid reverse currents from the bus line into the
battery supply line in case of an unpowered node, it is recommended to place a diode in
series to the external pull up. For small systems (low bus capacitance) the EMC
performance of the system is supported by an additional capacitor of at least 1nF in the
master node (see figure 6 and 7, application circuit).
External Capacitors
An capacitor of 22µF at the supply voltage input VS buffers the input voltage. In
combination with the required reverse polarity diode this prevents the device from
detecting power down conditions in case of negative transients on the supply line.
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The 100nF capacitors close to the VS pins of the 6259-2 and the voltage regulator help
to improve the EMC behavior of the system.
Sleep Mode
In order to reduce the current consumption the TLE 6259-2 offers a sleep operation
mode. This mode is selected by switching the enable input EN low (see figure 3, state
diagram). In the sleep mode, a voltage regulator can be controlled via the INH output in
order to minimize the current consumption of the whole application. A wake-up caused
by a message on the communication bus, automatically enables the voltage regulator by
switching the INH output high. In parallel the wake-up is indicated by setting the RxD
output LOW. When entering the normal mode this wake-up flag is reset and the RxD
output is released to transmit the bus data.
In case the voltage regulator control input is not connected to INH output or the
microcontroller is active respectively, the TLE6259-2 can be set in normal operation
mode without a wake-up via the communication bus.
Bus Short to GND Feature
The TLE6259-2 also has a BUS short to GND feature implemented, in order to protect
the battery from running out of charge. A normal master termination connection like
described above, 1kW resistor and diode between bus and VS, whould cause a
constantly drawn current via this path. The resulting resistance of this short to GND is
lower than 1kW. To avoid this current during a generator off state, like a parked car, the
sleep mode has a bus short to GND feature implemented in the 6259-2. This feature is
only applicable, if the master termination is connected with the INH pin, instead of the
VS. For a more detailed information see the application circuit in figure 6 and 7.
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2
Electrical Characteristics
2.1
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
VCC
VS
Vbus
Vbus
VI
-0.3
6
V
-0.3
40
V
-20
32
V
-20
40
V
t < 1s
-0.3
VCC +
V
0 V < VCC < 5.5 V
VINH
-0.3
Voltages
Supply voltage
Battery supply voltage
Bus input voltage
Bus input voltage
Logic voltages at
EN, TxD, RxD
Input voltages at INH
Output current at INH
Electrostatic discharge
voltage at Vs, Bus
Electrostatic discharge
voltage
IINH
VESD
0.3
VS +
V
0.3
20
mA
-4
4
kV
human body model
(100 pF via 1.5 kW)
VESD
-2
2
kV
human body model
(100 pF via 1.5 kW)
Tj
-40
150
°C
–
Temperatures
Junction temperature
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause
irreversible damage to the integrated circuit.
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2.2
Operating Range
Parameter
Supply voltage
Battery Supply Voltage
Junction temperature
Symbol
Limit Values
Unit
Remarks
min.
max.
VCC
VS
Tj
4.5
5.5
V
6
35
V
– 40
150
°C
–
Rthj-a
–
185
K/W
–
Thermal Resistances
Junction ambient
Thermal Shutdown (junction temperature)
Symbol
Thermal shutdown temp.
Thermal shutdown hyst.
Version 2.06
TjSD
DT
Limit Values
Unit
min.
typ.
max.
150
170
190
°C
–
10
–
K
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Final Datasheet TLE 6259-2
2.3
Electrical Characteristics
4.5 V < VCC < 5.5 V; 6.0 V < VS < 27 V; RL =500 W; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect
to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
min.
Unit Remarks
typ.
max.
0.3
0,7
mA
recessive state;
VTxD = VCC
0.4
0.8
mA
dominant state;
VTxD = 0 V
0.8
1.5
mA
recessive state,
without Rload;
VTxD = VCC
1.3
2
mA
dominant state,
without Rload;
VTxD = 0 V
ICC
3
10
µA
external VR
activated INH=H
IS
ICC
18
30
µA
-
-
µA
IS
18
30
µA
Current Consumption
Current consumption
inNormal Mode
ICC
IS
Current consumption
in Standby Mode
Current consumption
in Sleep Mode
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deactivated INH=L
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Final Datasheet TLE 6259-2
2.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 27 V; RL =500 W; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect
to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min.
typ.
max.
-1.2
-0.8
-0.5
mA
VRD = 0.8 x VCC,
0.5
0.8
1.2
mA
VRD = 0.2 x VCC,
2.9
0.7 x
V
recessive state
Receiver Output R´D
HIGH level output current
LOW level output current
IRD,H
IRD,L
Transmission Input T´D
HIGH level input voltage
threshold
VTD,H
TxD input hysteresis
VTD,hys
VTD,L
LOW level input voltage
threshold
TxD pull up current
VCC
300
700
900
0.3 x 2.1
mV
V
dominant state
VCC
ITD
-150
-110
-70
µA
VTxD<0.3Vcc
2.8
0.7 x
V
normal mode
V
low power mode
Enable input (pin EN)
HIGH level input voltage
threshold
VEN,on
LOW level input voltage
threshold
VEN,off
EN input hysteresis
VEN,hys
REN
EN pull down resistance
VCC
0.3 x 2.2
VCC
300
600
900
mV
15
30
60
kW
65
120
W
IINH = - 15 mA
5.0
µA
sleep mode;
VINH = 0 V
Inhibit output (pin INH)
Inhibit Ron resistance
RonINH
Leakage current
IINH,lk
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Final Datasheet TLE 6259-2
2.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 27 V; RL =500 W; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect
to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
min.
typ.
0.44
x VS
0.5 x
Unit Remarks
max.
Bus receiver
Receiver threshold voltage,
recessive to dominant edge
Vbus,rd
Receiver threshold voltage,
dominant to recessive edge
Vbus,dr
Receiver hysteresis
Vbus,hys 0.02
x VS
Vwake
0.40
x VS
wake-up threshold voltage
V
-8V<Vbus<Vbus,dom
V
Vbus,rec<Vbus<20 V
mV
Vbus,hys =
Vbus,rec - Vbus,dom
VS
0.56
x VS
0.6 x
0.04
x VS
0.1 x
VS
VS
0.5 x 0.6 x
VS
V
VS
Bus transmitter
Bus recessive output voltage Vbus,rec
0.9 x
VS
V
VTxD = VCC
0.15
x VS
V
VTxD = 0 V;
8V<VS<27V
1.2
V
6V<VS<8V
150
mA
Vbus,short = 13.5 V
mA
VCC = 0 V, VS = 0 V,
Vbus = -8 V
25
mA
VCC = 0 V, VS = 0 V,
Vbus = 20 V
10
µA
VLIN=VS=13,5V
VS
Bus dominant output voltage Vbus,dom
Bus short circuit current
Leakage current
Ibus,sc
Ibus,lk
40
100
-150
-70
10
Bus pull up resistance
Lin output current
Version 2.06
Rbus
Ilin
20
30
47
kW
Normal mode
5
30
60
µA
Sleep mode
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Final Datasheet TLE 6259-2
2.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 27 V; RL =500 W; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect
to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
min.
typ.
Unit Remarks
max.
Dynamic Transceiver Characteristics
Slope fall time
tfslope
22,5
µs
100% > Vbus > 0%
Cbus= 10 nF; RL=500W
VCC = 5 V; VS = 13.5 V
Slope rise time
trslope
22,5
µs
0% > Vbus >10 0%
Cbus= 10 nF; RL=500W
VCC = 5 V; VS = 13.5 V
Slope symmetry
5
µs
tfslope-trslope
Slope fall time
tslopesym -5
tfslope
22.5
µs
100% > Vbus > 0%
Cbus= 6,8nF;RL=660W
Tambient < 85 °C;
VCC = 5 V; VS = 13.5 V
Slope rise time
trslope
22.5
µs
0% > Vbus >100%
Cbus= 6,8nF;RL=660W
VCC = 5 V; VS = 13.5 V
Slope symmetry
tslopesym -4
td(L),T
4
µs
tfslope-trslope
1
3
µs
VCC = 5 V
Propagation delay
TxD HIGH to bus
td(H),T
1
3
µs
VCC = 5 V
Propagation delay
bus dominant to RxD LOW
td(L),R
1
6
µs
VCC = 5V;
CRxD = 20pF
Propagation delay
bus recessive to RxD HIGH
td(H),R
1
6
µs
VCC = 5 V;
CRxD = 20 pF
Receiver delay symmetry
tsym,R
tsym,T
twake
-2
2
µs
tsym,R = td(L),R - td(H),R
-2
2
µs
tsym,T = td(L),T - td(H),T
150
µs
Tj £ 125°
170
µs
Tj £ 150°
Delay time for change sleep/ tsnorm
stand by mode-normal mode
10
µs
Delay time for change normal tnsleep
mode - sleep mode
10
µs
Propagation delay
TxD LOW to bus
Transmitter delay symmetry
Wake-up delay time
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3
Diagrams
EN
Vs
100 nF
INH
1 k9
TxD
RxD
Bus
20 pF
Cbus
GND
VCC
100 nF
Figure 4: Test circuits
VCC
VTxD
GND
td(L),T
t
td(H),T
VS
Vbus
Vbus,rd
Vbus,dr
GND
t
td(H),R
td(L),R
VCC
0.7*VCC
VRxD
0.3*VCC
GND
td(L),TR
td(H),TR
t
Figure 5: Timing diagrams for dynamic characteristics
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4
Application
Vbat
LIN bus
master node
Vs
TLE 6259-2G
EN
RxD
100 nF
1 k
Bus
1nF
INH
µP
TxD
GND
VCC
GND
100 nF
INH
100 nF
5V
VQ
e.g. TLE 4263
VI
22 µF
22 µF
GND
100 nF
ECU 1
slave node
TLE 6259-2G
Vs
EN
100 nF
RxD
INH
µP
TxD
Bus
GND
VCC
GND
100 nF
VI
100 nF
VQ
e.g. TLE 4278
100 nF
5V
22 µF
GND
22 µF
ECU X
Figure 6
Application circuit with bus short to GND feature applied
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Vbat
LIN bus
master node
TLE 6259-2G
Vs
EN
RxD
100 nF
1 k
µP
TxD
Bus
1nF
INH
GND
VCC
GND
100 nF
INH
100 nF
5V
VQ
e.g. TLE 4263
VI
22 µF
22 µF
GND
100 nF
ECU 1
slave node
TLE 6259-2G
Vs
EN
100 nF
RxD
INH
µP
TxD
Bus
GND
VCC
GND
100 nF
VI
100 nF
VQ
e.g. TLE 4278
100 nF
5V
22 µF
GND
22 µF
ECU X
Figure 7
Application circuit without bus short to GND feature
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5
Package Outlines
P-DSO-8-3
(Plastic Dual Small Outline Package)
0.33 ±0.08 x 45˚
Index
Marking
0.2
8
5
1
4
5 -0.21)
M
8˚ MAX.
0.2
C
0.1
0.41 +0.1
-0.05
+0.05
-0.01
1.75 MAX.
0.1 MIN.
(1.5)
1.27
4 -0.21)
0.64 ±0.25
A C x8
6 ±0.2
A
Index Marking (Chamfer)
1)
Does not include plastic or metal protrusion of 0.15 max. per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Dimensions in mm
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Final Datasheet TLE 6259-2
Edition 1999-10-12
Published by Infineon Technologies AG
St.-Martin-Strasse 53
D-81541 München
© Infineon Technologies AG1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and
charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
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For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office
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Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to
support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
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