CYRF6936 WirelessUSB™ LP 2.4 GHz Radio SoC WirelessUSB™ LP 2.4 GHz Radio SoC Features ■ Battery Voltage Monitoring Circuitry ■ Supports coin-cell operated applications ■ Operating voltage from 1.8 V to 3.6 V ■ Operating temperature from 0 °C to 70 °C ■ Space saving 40-pin QFN 6 × 6 mm package ■ 2.4 GHz Direct Sequence Spread Spectrum (DSSS) radio transceiver ■ Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz to 2.483 GHz) ■ 21 mA operating current (Transmit at –5 dBm) ■ Transmit power up to +4 dBm ■ Receive sensitivity up to –97 dBm ■ Wireless Keyboards and Mice ■ Sleep Current less than 1 A ■ Wireless Gamepads ■ DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps ■ Remote Controls ■ Low external component count ■ Toys ■ Auto Transaction Sequencer (ATS) - no MCU intervention ■ VOIP and Wireless Headsets ■ Framing, Length, CRC16, and Auto ACK ■ White Goods ■ Power Management Unit (PMU) for MCU/Sensor ■ Consumer Electronics ■ Fast Startup and Fast Channel Changes ■ Home Automation ■ Separate 16-byte Transmit and Receive FIFOs ■ Automatic Meter Readers ■ AutoRate™ - dynamic data rate reception ■ Personal Health and Entertainment ■ Receive Signal Strength Indication (RSSI) Applications Support ■ Serial Peripheral Interface (SPI) control while in sleep mode ■ 4 MHz SPI microcontroller interface Applications See www.cypress.com for development tools, reference designs, and application notes. Logic Block Diagram VBAT L/D VREG VDD VCC Power Management IRQ SS SCK MISO MOSI SPI Data Interface and Sequencer PACTL GFSK Modulator RFBIAS DSSS Baseband & Framer GFSK Demodulator RSSI Xtal Osc RFP RFN Synthesizer RST XTAL XOUT Cypress Semiconductor Corporation Document Number: 38-16015 Rev. *K • GND 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 24, 2014 CYRF6936 Contents Functional Description ..................................................... 3 Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Functional Overview ........................................................ 4 Data Transmission Modes ........................................... 4 Link Layer Modes ........................................................ 4 Packet Buffers ............................................................. 5 Auto Transaction Sequencer (ATS) ............................ 6 Data Rates .................................................................. 6 Functional Block Overview .............................................. 6 2.4 GHz Radio ............................................................. 6 Frequency Synthesizer ................................................ 6 Baseband and Framer ................................................. 6 Packet Buffers and Radio Configuration Registers ..... 6 SPI Interface ................................................................ 6 Interrupts ..................................................................... 8 Clocks .......................................................................... 8 Power Management .................................................... 8 Low Noise Amplifier and Received Signal Strength Indication ................................... 9 Receive Spurious Response ....................................... 9 Application Examples .................................................... 10 Registers ......................................................................... 15 Document Number: 38-16015 Rev. *K Absolute Maximum Ratings .......................................... 16 Operating Conditions ..................................................... 16 DC Characteristics ......................................................... 16 AC Characteristics ......................................................... 18 SPI Interface .............................................................. 18 RF Characteristics .......................................................... 19 Radio Parameters ..................................................... 19 Typical Operating Characteristics ................................ 21 AC Test Loads and Waveforms for Digital Pins .......... 23 Ordering Information ...................................................... 24 Ordering Code Definitions ......................................... 24 Package Diagram ............................................................ 25 Acronyms ........................................................................ 27 Document Conventions ................................................. 27 Units of Measure ....................................................... 27 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 30 Worldwide Sales and Design Support ....................... 30 Products .................................................................... 30 PSoC® Solutions ...................................................... 30 Cypress Developer Community ................................. 30 Technical Support ..................................................... 30 Page 2 of 30 CYRF6936 Functional Description The CYRF6936 WirelessUSB™ LP radio is a second generation member of the Cypress WirelessUSB Radio System-On-Chip (SoC) family. The CYRF6936 is interoperable with the first generation CYWUSB69xx devices. The CYRF6936 IC adds a range of enhanced features, including increased operating voltage range, reduced supply current in all operating modes, higher data rate options, reduced crystal start up, synthesizer settling, and link turnaround times. Pinouts Figure 1. 40-pin QFN pinout NC 31 NC 32 VI/O 33 RST 34 VDD 35 NC 36 38 L/D 37 VBAT0 NC 39 VREG 40 Corner tabs XTAL 1 30 PACTL / GPIO NC 2 29 XOUT / GPIO VCC 3 28 MISO / GPIO NC 4 27 MOSI / SDAT CYRF6936 WirelessUSB LP 40-Pin QFN 26 IRQ / GPIO NC 5 VBAT1 6 VCC 7 24 SS VBAT2 8 23 NC NC 9 25 SCK 22 NC * E-PAD Bottom Side 21 NC RFBIAS 10 20 NC 19 RESV 18 NC 17 NC 16 VCC 15 NC 14 NC 13 RFN 12 GND 11 RFP Pin Definitions Pin Number Name Type Default Description 1 XTAL I I 2, 4, 5, 9, 14, 15, 17, 18, 20, 21, 22, 23, 31, 32, 36, 39 NC NC Connect to GND. 3, 7, 16 VCC Pwr VCC = 2.4 V to 3.6 V. Typically connected to VREG. 6, 8, 38 VBAT(0-2) Pwr 10 RFBIAS O O RF I/O 1.8 V reference voltage. 11 RFP I/O I Differential RF signal to and from antenna. 12 GND GND 13 RFN I/O 19 RESV I 24 SS I I SPI enable, active LOW assertion. Enables and frames transfers. 25 SCK I I SPI clock. Interrupt output (configurable active HIGH or LOW), or GPIO. 12 MHz crystal. VBAT = 1.8 V to 3.6 V. Main supply. Ground. I Differential RF signal to and from antenna. Must be connected to GND. 26 IRQ I/O O 27 MOSI I/O I SPI data input pin (Master Out Slave In), or SDAT. 28 MISO I/O Z SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode). Tri-states when SPI 3PIN = 0 and SS is deasserted. Document Number: 38-16015 Rev. *K Page 3 of 30 CYRF6936 Pin Definitions (continued) Pin Number Name Type Default Description 29 XOUT I/O O Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO. Tri-states in sleep mode (configure as GPIO drive LOW). 30 PACTL I/O O Control signal for external PA, T/R switch, or GPIO. 33 VI/O Pwr 34 RST I 35 VDD Pwr 37 L/D O 40 VREG Pwr E-PAD GND GND Corner Tabs NC NC I/O interface voltage, 1.8–3.6 V. I Device reset. Internal 10 kohm pull down resistor. Active HIGH, connect through a 0.47 F capacitor to VBAT. Must have RST = 1 event the first time power is applied to the radio. Otherwise the state of the radio control registers is unknown. Decoupling pin for 1.8 V logic regulator, connect through a 0.47 F capacitor to GND. PMU inductor/diode connection, when used. If not used, connect to GND. PMU boosted output voltage feedback. Must be soldered to Ground. Do Not solder the tabs and keep other signal traces clear. All tabs are common to the lead frame or paddle which is grounded after the pad is grounded. While they are visible to the user, they do not extend to the bottom. Functional Overview The CYRF6936 IC provides a complete WirelessUSB SPI to antenna wireless MODEMs. The SoC is designed to implement wireless device links operating in the worldwide 2.4 GHz ISM frequency band. It is intended for systems compliant with worldwide regulations covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry Canada), and TELEC ARIB_T66_March, 2003 (Japan). The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). The baseband performs DSSS spreading/despreading, Start of Packet (SOP), End of Packet (EOP) detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both. In addition, the CYRF6936 IC has a Power Management Unit (PMU), which enables direct connection of the device to any battery voltage in the range 1.8 V to 3.6 V. The PMU conditions the battery voltage to provide the supply voltages required by the device, and may supply external devices. Document Number: 38-16015 Rev. *K Data Transmission Modes The SoC supports four different data transmission modes: ■ In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. ■ In 8DR mode, eight bits are encoded in each derived code symbol transmitted. ■ In DDR mode, two bits are encoded in each derived code symbol transmitted (As in the CYWUSB6934 DDR mode). ■ In SDR mode, one bit is encoded in each derived code symbol transmitted (As in the CYWUSB6934 standard modes). Both 64 chip and 32 chip Pseudo Noise (PN) codes are supported. The four data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, lower data rates reduce packet error rate in any given environment. Link Layer Modes The CYRF6936 IC device supports the following data packet framing features: SOP Packets begin with a two-symbol SoP marker. This is required in GFSK and 8DR modes, but is optional in DDR mode and is not supported in SDR mode. If framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the “body” of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. Length There are two options for detecting the end of a packet. If SOP is enabled, then the length field must be enabled. GFSK and 8DR must enable the length field. This is the first eight bits after Page 4 of 30 CYRF6936 the SOP symbol, and is transmitted at the payload data rate. When the length field is enabled, an EoP condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16. The alternative to using the length field is to infer an EOP condition from a configurable number of successive noncorrelations; this option is not available in GFSK mode and is only recommended when using SDR mode. calculated using either the loaded seed value or a zero seed; the received data CRC16 is checked against both the configured and zero CRC16 seeds. CRC16 detects the following errors: ■ Any one bit in error. ■ Any two bits in error (irrespective of how far apart, which column, and so on). ■ Any odd number of bits in error (irrespective of the location). ■ An error burst as wide as the checksum itself. CRC16 The device may be configured to append a 16 bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver verifies the calculated CRC16 for the payload data against the received value in the CRC16 field. The seed value for the CRC16 calculation is configurable, and the CRC16 transmitted may be Figure 2 shows an example packet with SOP, CRC16, and lengths fields enabled, and Figure 3 shows a standard ACK packet. Figure 2. Example Packet Format Preamble n x 16us P 2nd Framing Symbol* SOP 1 SOP 2 Length Payload Data Packet length 1 Byte Period 1st Framing Symbol* CRC 16 *Note:32 or 64us Figure 3. Example ACK Packet Format 2nd Framing Symbol* Preamble n x 16us P SOP 1 1st Framing Symbol* SOP 2 CRC 16 CRC field from received packet. 2 Byte periods Packet Buffers All data transmission and reception use the 16 byte packet buffers - one for transmission and one for reception. The transmit buffer allows loading a complete packet of up to 16 bytes of payload data in one burst SPI transaction. This is then transmitted with no further MCU intervention. Similarly, the receive buffer allows receiving an entire packet of payload data up to 16 bytes with no firmware intervention required until the packet reception is complete. Document Number: 38-16015 Rev. *K *Note:32 or 64us The CYRF6936 IC supports packets up to 255 bytes. However, the actual maximum packet length depends on the accuracy of the clock on each end of the link and the data mode. Interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing. Page 5 of 30 CYRF6936 Auto Transaction Sequencer (ATS) The CYRF6936 IC provides automated support for transmission and reception of acknowledged data packets. Table 1. Internal PA Output Power Step Table When transmitting in transaction mode, the device automatically: PA Setting Typical Output Power (dBm) 7 +4 ■ starts the crystal and synthesizer 6 0 ■ enters transmit mode 5 –5 ■ transmits the packet in the transmit buffer 4 –13 ■ transitions to receive mode and waits for an ACK packet 3 –18 transitions to the transaction end state when an ACK packet is received or a timeout period expires 2 –24 1 –30 Similarly, when receiving in transaction mode, the device automatically: 0 –35 ■ ■ waits in receive mode for a valid packet to be received Frequency Synthesizer ■ transitions to transmit mode, transmits an ACK packet ■ transitions to the transaction end state (receive mode to await the next packet, and so on.) Before transmission or reception may begin, the frequency synthesizer must settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. The contents of the packet buffers are not affected by the transmission or reception of ACK packets. In each case, the entire packet transaction takes place without any need for MCU firmware action (as long as packets of 16 bytes or less are used). To transmit data, the MCU must load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware must retrieve the fully received packet in response to an interrupt request indicating reception of a packet. Data Rates The CYRF6936 IC supports the following data rates by combining the PN code lengths and data transmission modes described in the previous sections: ■ 1000 kbps (GFSK) ■ 250 kbps (32 chip 8DR) ■ 125 kbps (64 chip 8DR) ■ 62.5 kbps (32 chip DDR) ■ 31.25 kbps (64 chip DDR) ■ 15.625 kbps (64 chip SDR) Functional Block Overview The ‘fast channels’ (less than 100 s settling time) are every third channel, starting at 0 up to and including 72 (for example, 0, 3, 6, 9 …. 69, 72). Baseband and Framer The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception, CRC16 generation and checking, and EOP detection and length field. Packet Buffers and Radio Configuration Registers Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet (as in the CYWUSB6934). Configuration registers allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, and so on. SPI Interface The CYRF6936 IC has an SPI interface supporting communication between an application MCU and one or more slave devices (including the CYRF6936). The SPI interface supports single-byte and multi-byte serial transfers using either 4-pin or 3-pin interfacing. The SPI communications interface consists of Slave Select (SS), Serial Clock (SCK), Master Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data (SDAT). 2.4 GHz Radio SPI communication may be described as the following: The radio transceiver is a dual conversion low IF architecture optimized for power, range, and robustness. The radio employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in seven steps. The supply current of the device is reduced as the RF output power is reduced. ■ Command Direction (bit 7) = ‘1’ enables SPI write transaction. A ‘0’ enables SPI read transactions. ■ Command Increment (bit 6) = ‘1’ enables SPI auto address increment. When set, the address field automatically increments at the end of each data byte in a burst access. Otherwise the same address is accessed. ■ Six bits of address ■ Eight bits of data Document Number: 38-16015 Rev. *K Page 6 of 30 CYRF6936 ensure that the MOSI pin on the MCU is in a high impedance state except when MOSI is actively transmitting data. The device receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the MISO pin. The active LOW Slave Select (SS) pin must be asserted to initiate an SPI transfer. The device registers may be written to or read from one byte at a time, or several sequential register locations may be written or read in a single SPI transaction using incrementing burst mode. In addition to single byte configuration registers, the device includes register files. Register files are FIFOs written to and read from using nonincrementing burst SPI transactions. The application MCU can initiate SPI data transfers using a multi-byte transaction. The first byte is the Command/Address byte, and the following bytes are the data bytes shown in Table 2 through Figure 6 on page 8. The SPI communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as required. A burst transaction is terminated by deasserting the slave select (SS = 1). The IRQ pin function may be optionally multiplexed onto the MOSI pin. When this option is enabled, the IRQ function is not available while the SS pin is LOW. When using this configuration, user firmware must ensure that the MOSI pin on the MCU is in a high impedance state whenever the SS pin is HIGH. The SPI communications interface single read and burst read sequences are shown in Figure 4 on page 7 and Figure 5 on page 7, respectively. The SPI interface is not dependent on the internal 12 MHz clock. Registers may therefore be read from or written to when the device is in sleep mode, and the 12 MHz oscillator disabled. The SPI communications interface single write and burst write sequences are shown in Figure 6 on page 8 and Figure 7 on page 8, respectively. The SPI interface and the IRQ and RST pins have a separate voltage reference pin (VI/O). This enables the device to interface directly to MCUs operating at voltages below the CYRF6936 IC supply voltage. This interface may be optionally operated in a 3-pin mode with the MISO and MOSI functions combined in a single bidirectional data pin (SDAT). When using 3-pin mode, user firmware must Table 2. SPI Transaction Format Parameter Byte 1 Byte 1+N Bit # 7 6 [5:0] [7:0] Bit Name DIR INC Address Data Figure 4. SPI Single Read Sequence SCK SS cmd MOSI DIR 0 INC addr A5 A4 A3 A2 A1 A0 data to mcu MISO D7 D6 D5 D4 D3 D2 D1 D0 Figure 5. SPI Incrementing Burst Read Sequence SCK SS cmd MOSI DIR 0 INC addr A5 A4 A3 A2 A1 A0 data to mcu1 MISO Document Number: 38-16015 Rev. *K D7 D6 D5 D4 D3 data to mcu1+N D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Page 7 of 30 CYRF6936 Figure 6. SPI Single Write Sequence SCK SS cmd MOSI DIR 1 INC addr A5 A4 A3 A2 data from mcu A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MISO Figure 7. SPI Incrementing Burst Write Sequence SCK SS cmd MOSI DIR 1 INC addr A5 A4 A3 A2 data from mcu1 A1 A0 D7 D6 D5 D4 D3 D2 data from mcu1+N D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MISO Interrupts ■ Frequency Stability: ±30 ppm The device provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events. The IRQ pin may be programmed to be either active HIGH or active LOW, and be either a CMOS or open drain output. The available interrupts are described in the section Registers on page 15. ■ Series Resistance: <60 ohms ■ Load Capacitance: 10 pF ■ Drive Level: 100 µW The CYRF6936 IC features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled or disabled. The contents of the enable registers are preserved when switching between transmit and receive modes. Power Management If more than one interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without the IRQ pin, by polling the status registers to wait for an event, rather than using the IRQ pin. Clocks A 12 MHz crystal (30 ppm or better) is directly connected between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output may be used to clock an external microcontroller (MCU) or ASIC. This output is enabled by default, but may be disabled. The requirements to directly connect the crystal to the XTAL pin and GND are: ■ Nominal Frequency: 12 MHz ■ Operating Mode: Fundamental Mode ■ Resonance Mode: Parallel Resonant Document Number: 38-16015 Rev. *K The operating voltage of the device is 1.8 V to 3.6 V DC, which is applied to the VBAT pin. The device can be shut down to a fully static sleep mode by writing to the FRC END = 1 and END STATE = 000 bits in the XACT_CFG_ADR register over the SPI interface. The device enters sleep mode within 35 µs after the last SCK positive edge at the end of this SPI transaction. Alternatively, the device may be configured to automatically enter sleep mode after completing the packet transmission or reception. When in sleep mode, the on-chip oscillator is stopped, but the SPI interface remains functional. The device wakes from sleep mode automatically when the device is commanded to enter transmit or receive mode. When resuming from sleep mode, there is a short delay while the oscillator restarts. The device can be configured to assert the IRQ pin when the oscillator has stabilized. The output voltage (VREG) of the Power Management Unit (PMU) is configurable to several minimum values between 2.4 V and 2.7 V. VREG may be used to provide up to 15 mA (average load) to external devices. It is possible to disable the PMU and provide an externally regulated DC supply voltage to the device’s main supply in the range 2.4 V to 3.6 V. The PMU also provides a regulated 1.8 V supply to the logic. The PMU is designed to provide high boost efficiency (74–85% depending on input voltage, output voltage, and load) when using a Schottky diode and power inductor, eliminating the need for an external boost converter in many systems where other components require a boosted voltage. However, reasonable efficiencies (69–82% depending on input voltage, output voltage, Page 8 of 30 CYRF6936 and load) may be achieved when using low cost components such as SOT23 diodes and 0805 inductors. ranges. Disabling AGC and enabling LNA is recommended, unless receiving from a device using external PA. The current through the diode must stay within the linear operating range of the diode. For some loads the SOT23 diode is sufficient, but with higher loads it is not and an SS12 diode must be used to stay within this linear range of operation. Along with the diode, the inductor used must not saturate its core. In higher loads, a lower resistance/higher saturation coil such as the inductor from Sumida must be used. When the device is in receive mode the RSSI_ADR register returns the relative signal strength of the on-channel signal power. The PMU also provides a configurable low battery detection function, which may be read over the SPI interface. One of seven thresholds between 1.8 V and 2.7 V may be selected. The interrupt pin may be configured to assert when the voltage on the VBAT pin falls below the configured threshold. LV IRQ is not a latched event. Battery monitoring is disabled when the device is in sleep mode. Low Noise Amplifier and Received Signal Strength Indication The gain of the receiver can be controlled directly by clearing the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of the RX_CFG_ADR register. Clearing the LNA bit reduces the receiver gain approximately 20 dB, allowing accurate reception of very strong received signals (for example, when operating a receiver very close to the transmitter). Approximately 30 dB of receiver attenuation can be added by setting the Attenuation (ATT) bit. This limits data reception to devices at very short Document Number: 38-16015 Rev. *K When receiving, the device automatically measures and stores the relative strength of the signal being received as a five bit value. An RSSI reading is taken automatically when the SoP is detected. In addition, a new RSSI reading is taken every time the previous reading is read from the RSSI_ADR register, allowing the background RF energy level on any given channel to be easily measured when RSSI is read while no signal is being received. A new reading can occur as fast as once every 12 µs. Receive Spurious Response The transmitter may exhibit spurs around 50 MHz offset at levels approximately 50dB to 60dB below the carrier power. Receivers operating at the transmit spur frequency may receive the spur if the spur level power is greater than the receive sensitivity level. The workaround for this is to program an additional byte in the packet header which contains the transmitter channel number. After the packet is received, the channel number can be checked. If the channel number does not match the receive channel then the packet is rejected. Page 9 of 30 NEG2 NEG1 POS 3 "-" 2 "+" 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 KB 26 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 J1 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 COL18 COL17 COL16 COL15 COL14 COL13 COL12 COL11 COL10 COL9 COL8 COL7 COL6 COL5 COL4 COL3 COL2 COL1 Keyboard Interface BATT CON 2xAA BH1 VBAT 1B 2B R1 is a zero ohm resistor that should be installed for production units only, following programming. A 2-pin jumper installed from J3.1 to J2.1 enables the radio to power the processor. Jumper removal is required when programming U2 to disconnect the radio from the Miniprog 5V source. VCC Serial debug header SW PUSHBUTTON 1A 2A S1 BIND 3 2 1 COL17 COL18 P4_0 P4_1 P4_2 P4_3 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P1_0 P1_1 P1_2 P1_3 / SSEL P1_4 / SCLK P1_5 / SMOSI P1_6 / SMISO P1_7 EVCC P1_0 P1_1 0402 XRES SCLK SDATA NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 P0_0 / CLKIN P0_1 / CLKOUT P0_2 / INT0 P0_3 / INT1 P0_4 / INT2 P0_5 / TIO0 P0_6 / TIO1 P0_7 5 PIN HDR 1 2 3 4 5 J2 ISSP CY7C60123-PVXC 7 6 42 43 34 35 36 37 38 39 40 41 25 26 28 29 30 31 32 33 U2 Layout J3 and J2.1 in a 0.100" spacing configuration 1 PIN HDR 1 J3 NO LOAD R1 3 PIN HDR J4 COL9 COL10 COL11 COL12 COL13 COL14 COL15 COL16 P1_0 P1_1 SW1 nSS SCK MOSI MISO IRQ 0603 Power Supply EVCC 27 5 1 2 3 4 45 46 47 48 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 0.01 uFd C19 0402 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 E 100 uFd 10v + C18 VBAT 0.01 uFd C20 1210 No Load C6 L3 10 uH TV8 0402 0402 2 1 BAT400D SOT23 IRQ TV7 D1 nSS SCK MOSI MISO RST TV2 TV3 TV4 TV5 0805 10 uFd 6.3V C7 2 4 5 9 14 15 17 18 37 26 24 25 27 28 34 0805 TP2 10 uFd 6.3V C12 TP1 VCC NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 L/D IRQ SS SCK MOSI MISO RST RF VCO and VCO Buffer Filter U1 CYRF6936 0.047 uFd C13 C17 0.47 uFd VBAT 0402 C8 1 uFd 6.3V 47 R3 1 1% VCC C15 0402 C16 0.047 uFd C11 0.047 uFd 0402 R2 8 6 38 VBAT2 VBAT1 VBAT0 C9 0.047 uFd C10 0.047 uFd C5 0.047 uFd 0402 For reference design part numbers, please refer to the Bill of Materials file 121-26504_A.xls. VBAT 19 20 21 22 23 31 32 36 39 29 1 30 13 11 10 IND0402 TV6 L2 1.8 nH CLKOUT TV1 PACTL IND0603 L1 22 nH C1 15 pFd 12 MHz Crystal Y1 2.0 pFd C3 E-PAD must be soldered to ground. RESV NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 XOUT XTAL PACTL RFn RFp RFbias 0.47 uFd Radio Decoupling Caps 0402 An alternate decoupling configuration is the following: C6=47uF ceramic R2=0ohm C7=.047uF. For this configuration, it is not required to load C18. 33 GND1 12 VIO 41 VDD2 VDD1 VSS2 VSS1 44 24 40 VREG 0402 3 7 16 VCC1 VCC2 VCC3 0402 0402 35 VDD E-PAD 0402 0402 Document Number: 38-16015 Rev. *K 0402 1.5 pFd C4 ANT1 WIGGLE 63 1 2 0805 The power supply decoupling shown for VBAT0 is a recommended cost effective configuration: C6=No Load R2= 1ohm C7=10uF ceramic. For this configuration, it is required that C18 be installed. CYRF6936 Application Examples Figure 8. Recommended Circuit for Systems where VBAT 2.4 V Page 10 of 30 CYRF6936 Table 3. Recommended BoM for Systems where VBAT 2.4 V Item Qty CY Part Number Reference ANT1 Description 1 1 NA 2.5 GHZ H-STUB WIGGLE ANTENNA FOR 63 MIL PCB 2 1 NA BH1 BATTERY CLIPS 2AA CELL 3 1 730-10012 C1 4 1 730-11955 5 1 6 Manufacturer Mfr Part Number NA NA CAP 15 PF 50 V CERAMIC NPO 0402 Panasonic ECJ-0EC1H150J C3 CAP 2.0 PF 50 V CERAMIC NPO 0402 Kemet C0402C209C5GACTU 730-11398 C4 CAP 1.5 PF 50 V CERAMIC NPO 0402 SMD PANASONIC ECJ-0EC1H1R5C 2 730R-13322 C5, C17 CAP CER 0.47 UF 6.3 V X5R 0402 Murata GRM155R60J474KE19D 7 2 730-13037 C12, C7 CAP CERAMIC 10 UF 6.3 V X5R 0805 Kemet C0805C106K9PACTU 8 1 730-13400 C8 CAP 1 uF 6.3 V CERAMIC X5R 0402 Panasonic 9 6 730-13404 C9, C10, C11, CAP 0.047 uF 16 V CERAMIC X5R AVX C13, C15, 0402 C16 Panasonic - ECG ECJ-0EB0J105M 0402YD473KAT2A 10 1 710-13201 C18 CAP 100 UF 10 V ELECT FC 11 2 730-10794 C20,C19 CAP 10000 PF 16 V CERAMIC 0402 Panasonic - ECG SMD ECJ-0EB1C103K EEU-FC1A101S 12 1 800-13317 D1 DIODE SCHOTTKY 0.5 A 40 V SOT23 DIODES INC BAT400D-7-F 13 1 NA J1 PCB COPPER PADS NONE 14 1 420-11496 J2 CONN HDR BRKWAY 5POS STR AU PCB AMP Division of TYCO 103185-5 15 1 420-11964 J3 HEADER 1 POS 0.230 HT MODII .100 CL AMP/Tyco 103185-1 16 1 800-13401 L1 INDUCTOR 22 NH 2% FIXED 0603 Panasonic - ECG SMD ELJ-RE22NGF2 17 1 800-11651 L2 INDUCTOR 1.8 NH +/-.3 NH FIXED Panasonic - ECG 0402 SMD ELJ-RF1N8DF 18 1 800-10594 L3 COIL 10 UH 1100MA CHOKE 0805 Newark 30K5421 19 1 630-11356 R2 RES 1.00 OHM 1/8 W 1% 0805 SMD Yageo 9C08052A1R00FKHFT 20 1 610-13402 R3 RES 47 OHM 1/16 W 5% 0402 SMD ERJ-2GEJ470X 21 1 800-13368 S1 LT SWITCH 6 MM 100 GF H = 7 MM Panasonic - ECG TH EVQ-PAC07K 22 1 CYRF6936-40LF U1 C IC, LP 2.4 GHz RADIO SoC QFN-40 Cypress Semiconductor CYRF6936 Rev A5 23 1 CY7C60123-PVX U2 C IC WIRELESS EnCore II CONTROLLER SSOP48 Cypress Semiconductor CY7C60123-PVXC 24 1 800-13259 Y1 CRYSTAL 12.00 MHZ HC49 SMD eCERA GF-1200008 25 1 PDC-9265-*B PCB PRINTED CIRCUIT BOARD Cypress Semiconductor PDC-9265-*B 26 1 920-11206 LABEL1 Serial Number 27 1 920-26504 *A LABEL2 PCA # Document Number: 38-16015 Rev. *K Panasonic - ECG 121-26504 *A Page 11 of 30 CYRF6936 Table 3. Recommended BoM for Systems where VBAT 2.4 V (continued) Item Qty CY Part Number Reference Description Manufacturer Mfr Part Number No Load Components - Do Not Install 28 1 730-13403 C6 CAP 47UF 6.3 V CERAMIC X5R 1210 29 1 630-10242 R2 RES CHIP 0.0 OHM 1/10W 5% 0805 Phycomp USA Inc SMD 9C08052A0R00JLHFT 30 1 730-13404 C7 CAP 0.047 uF 50 V CERAMIC X5R AVX 0402 0402YD473KAT2A 31 1 420-10921 J4 HEADER 3POS FRIC STRGHT MTA AMP/Tyco 100 644456-3 32 1 620-10519 R1 RES ZERO OHM 1/16W 5% 0603 SMD ERJ-3GEY0R00V Document Number: 38-16015 Rev. *K Panasonic Panasonic - ECG ECJ-4YB0J476M Page 12 of 30 1 2 3 4 5 6 USB A SMT PLUG VBUS DM DP GND S1 S2 R1 zero VBUS DM DP 5V 5V R2 620 SSEL/P1_3 SCLK/P1_4 MOSI/P1_5 MISO/P1_6 CY7C63803-SXC 13 14 15 16 DM/P1_1 DP/P1_0 S1 SW RA PUSH 1A 1B D1 C C LED Green Red RD GR 2A 2B "BIND" 2 1 4 3 SW1 nLED2 nLED1 "CONNECT/ACTIVITY" nSS SCK MOSI MISO 10 9 0402 P0_0 P0_1 P0_2/INT0 P0_3/INT1 P0_4/INT2 P0_5/TIO0 P0_6/TIO1 VREG 7 6 5 4 3 2 1 12 1500 pFd RST nLED2 nLED1 IRQ SW1 VCC 0805 5V 4.7 uFd C13 0805 VCC 2.2 uFd C14 C15 0.47 uFd Power Supply 0402 VCC 0402 0.047 uFd C6 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 L/D IRQ SS SCK MOSI MISO RST VCC 2 4 5 9 14 15 17 18 37 26 24 25 27 28 nSS SCK MOSI MISO IRQ 34 RST U1 CYRF6936 VCC 0402 8 6 38 VBAT2 VBAT1 VBAT0 U2 33 VIO 11 VCC VSS 8 0.047 uFd C7 0402 19 20 21 22 23 31 32 36 39 29 1 30 13 11 10 TV1 22 nH 1.8 nH IND0402 TV-20R L2 L1 IND0603 15 pFd C1 0.047 uFd C8 0402 0.047 uFd C9 0402 0.047 uFd C10 0402 0.047 uFd C11 0402 12 MHz Crystal Y1 2.0 pFd C3 0402 E-PAD must be soldered to ground. RESV NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 XOUT XTAL PACTL RFn RFp 0402 0.47 uFd C5 RFbias 40 VREG GND1 12 3 7 16 E-PAD 35 VDD VCC1 VCC2 VCC3 C12 1.5 pFd C4 ANT1 WIGGLE 32 1 2 J1 0402 Document Number: 38-16015 Rev. *K 41 0402 5V CYRF6936 Figure 9. Recommended Circuit for Systems where VBAT is 2.4 V–3.6 V (PMU Disabled) Page 13 of 30 0402 CYRF6936 Table 4. Recommended BoM for Systems where VBAT is 2.4 V–3.6 V (PMU disabled) Item Qty CY Part Number Reference Description Manufacturer Mfr Part Number 1 1 NA ANT1 2.5 GHZ H-STUB WIGGLE ANTENNA FOR 32MIL PCB NA NA 2 1 730-10012 C1 CAP 15 PF 50 V CERAMIC NPO 0402 Panasonic ECJ-0EC1H150J 3 1 730-11955 C3 CAP 2.0 PF 50 V CERAMIC NPO 0402 Kemet C0402C209C5GACTU 4 1 730-11398 C4 CAP 1.5 PF 50 V CERAMIC NPO 0402 PANASONIC SMD ECJ-0EC1H1R5C 5 1 730-13322 C5, C15 CAP 0.47 uF 6.3 V CERAMIC X5R 0402 Murata GRM155R60J474KE19D 7 6 730-13404 C6, C7, C8, CAP 0.047 uF 16 V CERAMIC X5R 0402 AVX C9, C10, C11 8 1 730-11953 C12 CAP 1500 PF 50 V CERAMIC X7R 0402 Kemet C0402C152K5RACTU 9 1 730-13040 C13 CAP CERAMIC 4.7 UF 6.3 V XR5 0805 Kemet C0805C475K9PACTU 10 1 730-12003 C14 CAP CER 2.2 UF 10 V 10% X7R 0805 11 1 800-13333 D1 LED GREEN/RED BICOLOR 1210 SMD LITEON LTST-C155KGJRKT UAR72-4N5J10 6 0402YD473KAT2A GRM21BR71A225KA01L Murata Electronics North America 12 1 420-13046 J1 CONN USB PLUG TYPE A PCB SMT 13 1 800-13401 L1 INDUCTOR 22NH 2% FIXED 0603 SMD Panasonic - ECG ELJ-RE22NGF2 ACON 14 1 800-11651 L2 INDUCTOR 1.8 NH +/-.3 NH FIXED 0402 Panasonic - ECG ELJ-RF1N8DF SMD 15 1 610-10343 R1 RES ZERO OHM 1/16W 0402 SMD Panasonic - ECG ERJ-2GE0R00X 16 1 610-13472 R2 RES CHIP 620 OHM 1/16W 5% 0402 SMD Panasonic - ECG ERJ-2GEJ621X 17 1 200-13471 S1 SWITCH LT 3.5 MM X 2.9 MM 160 GF SMD Panasonic - ECG EVQ-P7J01K 18 1 CYRF6936-40LFC U1 IC, LP 2.4 GHz RADIO SoC QFN-40 Cypress Semiconductor CYRF6936 Rev A5 19 1 CY7C63803-SXC U2 IC LOW SPEED USB ENCORE II CONTROLLER SOIC16 Cypress Semiconductor CY7C63803-SXC 20 1 800-13259 Y1 CRYSTAL 12.00 MHZ HC49 SMD eCERA GF-1200008 21 1 PDC-9263-*B PCB PRINTED CIRCUIT BOARD Cypress Semiconductor PDC-9263-*B 22 1 LABEL1 Serial Number XXXXXX 23 1 LABEL2 PCA # 121-26305 ** Document Number: 38-16015 Rev. *K Page 14 of 30 CYRF6936 Registers All registers are read and writable, except where noted. Registers may be written to or read from individually or in sequential groups.[1, 2] Table 5. Register Map Summary Address Mnemonic b7 b6 0x00 0x01 CHANNEL_ADR TX_LENGTH_ADR 0x02 TX_CTRL_ADR TX GO TX CLR 0x03 TX_CFG_ADR Not Used OS IRQ Not Used LV IRQ b5 Not Used b4 0x04 TX_IRQ_STATUS_ADR 0x05 0x06 RX_CTRL_ADR RX GO RSVD TXB15 IRQEN DATA CODE LENGTH TXB15 IRQ RXB16 IRQEN RX_CFG_ADR AGC EN RXOW IRQ RX ACK LNA SOPDET IRQ PKT ERR ATT RXB16 IRQ EOP ERR LVIRQ EN PMU Mode Force XSIRQ EN MISO OD PFET disable[3] Not Used XOUT OD PACTL OP FRC END LEN EN Not Used Not Used LNA HINT IRQ OP 0x07 0x08 0x09 0x0A RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR 0x0B[1] PWR_CTRL_ADR PMU EN 0x0C 0x0D XTAL_CTRL_ADR IO_CFG_ADR XOUT FN IRQ OD IRQ POL 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D EOP_CTRL_ADR[4] CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR 0x1E 0x1F 0x26 0x27 0x28 0x29 0x32 0x35 0x39 Register Files 0x20 0x21 0x22 0x23 0x24 0x25 XOUT OP ACK EN SOP EN Not Used Not Used SOP HEN MISO OP Not Used SOP LEN Not Used Not Used Not Used Not Used RSVD Not Used RSVD RX_OVERRIDE_ADR ACK RX RXTX DLY TX_OVERRIDE_ADR XTAL_CFG_ADR CLK_OVERRIDE_ADR CLK_EN_ADR RX_ABORT_ADR AUTO_CAL_TIME_ADR AUTO_CAL_OFFSET_ADR ANALOG_CTRL_ADR ACK TX RSVD RSVD RSVD RSVD FRC PRE RSVD RSVD RSVD RSVD RSVD RSVD TX_BUFFER_ADR RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR MFG_ID_ADR b3 b2 Channel TX Length TXB8 TXB0 IRQEN IRQEN DATA MODE TXB8 TXB0 IRQ IRQ RXB8 RXB1 IRQEN IRQEN FAST HILO TURN EN RXB8 RXB1 IRQ IRQ CRC0 Bad CRC RX Count RX Length b1 TXBERR IRQEN TXC IRQEN TXE IRQEN TXBERR IRQ RXBERR IRQEN PA SETTING TXC IRQ RXC IRQEN TXE IRQ RXE IRQEN Not Used RXBERR IRQ RX Code RXOW EN VLD EN RXC RXE IRQ IRQ RX Data Mode LVI TH Not Used PACTL OD XOUT IP END STATE Not Used PMU OUTV PACTL GPIO MISO IP FREQ SPI 3PIN IRQ GPIO PACTL IP IRQ IP ACK TO SOP TH TH32 TH64 RSSI EOP CRC SEED LSB CRC SEED MSB CRC LSB CRC MSB CRC LSB CRC MSB STRIM LSB Not Used Not Used STRIM MSB FRC SEN FRC AWAKE Not Used Not Used FRC MAN RXACK RXDR DIS CRC0 DIS RXCRC ACE MAN RSVD TXACK OVRD ACK DIS TXCRC RSVD RSVD RSVD START DLY RSVD RSVD RSVD RSVD RSVD RSVD RXF RSVD RSVD RSVD RSVD RXF ABORT EN RSVD RSVD RSVD RSVD AUTO_CAL_TIME AUTO_CAL_OFFSET RSVD RSVD RSVD RSVD RX INV TX Buffer File RX Buffer File SOP Code File Data Code File Preamble File MFG ID File b0 RST Default[1] Access[1] -1001000 00000000 00000011 -bbbbbbb bbbbbbbb bbbbbbbb --000101 --bbbbbb -------- rrrrrrrr 00000111 bbbbbbbb 10010-10 bbbbb-bb -------- brrrrrrr -------00000000 00000000 rrrrrrrr rrrrrrrr rrrrrrrr 10100000 bbbbbbbb 000--100 00000000 bbb--bbb bbbbbbbb 0000---1-000000 10100101 ----0100 ---01010 0-100000 10100100 bbbbrrrr b-bbbbbb bbbbbbbb ----bbbb ---bbbbb r-rrrrrr bbbbbbbb 00000000 00000000 --------------11111111 11111111 00000000 ----0000 00000--0 0000000- bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb ----bbbb wwwww--w bbbbbbb- 00000000 bbbbbbbb 00000000 00000000 00000000 00000000 00000011 00000000 00000000 wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww --------------Note 5 Note 6 Note 7 NA wwwwwwww rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr Not Used TX INV RSVD RSVD RSVD RSVD ALL SLOW Notes 1. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined. 2. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode. The PMU, GPIOs, and RSSI registers can be accessed in Active Tx and Rx mode. 3. PFET Bit: Setting this bit to "1" disables the FET, therefore safely allowing Vbat to be connected to a separate reference from Vcc when the PMU is disabled to the radio. 4. EOP_CTRL_ADR[6:4] must never have the value of “000”, that is, EOP Hint Symbol count must never be “0” 5. SOP_CODE_ADR default = 0x17FF9E213690C782. 6. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F. 7. PREAMBLE_ADR default = 0x333302. The count value must be great than 4 for DDR and greater than 8 for SDR. Document Number: 38-16015 Rev. *K Page 15 of 30 CYRF6936 Static Discharge Voltage (Digital) [9] ........................ >2000 V Static Discharge Voltage (RF) [9] .............................. 1100 V Latch Up Current ....................................+200 mA, –200 mA Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied .................................. –55 °C to +125 °C Supply Voltage on any power supply pin relative to VSS ..............................................–0.3 V to +3.9 V DC Voltage to Logic Inputs [8] ...............–0.3 V to VI/O +0.3 V DC Voltage applied to Outputs in High-Z State ......................................–0.3 V to VI/O +0.3 V Operating Conditions VCC ..................................................................2.4 V to 3.6 V VI/O ..................................................................1.8 V to 3.6 V VBAT .................................................................1.8 V to 3.6 V TA (Ambient Temperature Under Bias) .......... 0 °C to +70 °C Ground Voltage ................................................................ 0 V FOSC (Crystal Frequency) ......................... 12 MHz ± 30 ppm DC Characteristics (T = 25C, VBAT = 2.4 V, PMU disabled, fOSC = 12.000000 MHz) Parameter Description Conditions Min Typ Max Unit VBAT Battery Voltage 0C–70 C 1.8 – 3.6 V VREG[10] VREG[10] VI/O[11] PMU Output Voltage 2.4 V mode 2.4 2.43 – V PMU Output Voltage 2.7 V mode 2.7 2.73 – V 1.8 – 3.6 V 2.4[12] – 3.6 V VI/O Voltage 0C–70 C VCC VCC Voltage VOH1 Output High Voltage Condition 1 At IOH = –100.0 µA VI/O – 0.2 VI/O – V VOH2 VI/O – 0.4 VI/O – V VOL Output High Voltage Condition 2 At IOH = –2.0 mA Output Low Voltage At IOL = 2.0 mA – 0 0.45 V VIH Input High Voltage 0.7 VI/O – VI/O V VIL Input Low Voltage 0 – 0.3 VI/O V IIL Input Leakage Current 0 < VIN < VI/O –1 0.26 +1 µA Pin Input Capacitance except XTAL, RFN, RFP, RFBIAS – 3.5 10 pF Average TX ICC, 1 Mbps, slow channel PA = 5, 2 way, 4 bytes/10 ms – 0.87 – mA ICC (32-8DR)[13] Average TX ICC, 250 kbps, fast channel PA = 5, 2 way, 4 bytes/10 ms – 1.2 – mA ISB[14] Sleep Mode ICC – 0.8 10 µA ISB[14] Sleep Mode ICC PMU enabled – 31.4 – µA IDLE ICC Radio off, XTAL Active XOUT disabled – 1.0 – mA CIN ICC (GFSK)[13] Notes 8. It is permissible to connect voltages above VI/O to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed. 9. Human Body Model (HBM). 10. VREG depends on battery input voltage. 11. In sleep mode, the I/O interface voltage reference is VBAT. 12. In sleep mode, VCC min. can be as low as 1.8 V. 13. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK handshake. Device is in sleep except during this transaction. 14. ISB is not guaranteed if any I/O pin is connected to voltages higher than VI/O. Document Number: 38-16015 Rev. *K Page 16 of 30 CYRF6936 DC Characteristics (continued) (T = 25C, VBAT = 2.4 V, PMU disabled, fOSC = 12.000000 MHz) Parameter Description Conditions Min Typ Max Unit – 8.4 – mA – 20.8 – mA Isynth ICC during Synth Start TX ICC ICC during Transmit TX ICC ICC during Transmit PA = 6 (0 dBm) – 26.2 – mA TX ICC ICC during Transmit PA = 7 (+4 dBm) – 34.1 – mA RX ICC ICC during Receive LNA off, ATT on – 18.4 – mA RX ICC ICC during Receive LNA on, ATT off – 21.2 – mA Boost Eff PMU Boost Converter Efficiency VBAT = 2.5 V, VREG = 2.73 V, ILOAD = 20 mA – 81 – % ILOAD_EXT[8] Average PMU External Load current VBAT = 1.8 V, VREG = 2.73 V, 0C–50 C, RX Mode – – 15 mA ILOAD_EXT[8] Average PMU External Load current VBAT = 1.8 V, VREG = 2.73 V, 50 C–70 C, RX Mode – – 10 mA PA = 5 (–5 dBm) Note 8. ILOAD_EXT is dependent on external components and this entry applies when the components connected to L/D are SS12 series diode and DH53100LC inductor from Sumida. Document Number: 38-16015 Rev. *K Page 17 of 30 CYRF6936 AC Characteristics SPI Interface Parameter [9, 10] Description Min Typ Max Unit 238.1 – – ns tSCK_CYC SPI Clock Period tSCK_HI SPI Clock High Time 100 – – ns tSCK_LO SPI Clock Low Time 100 – – ns tDAT_SU SPI Input Data Setup Time 25 – – ns tDAT_HLD SPI Input Data Hold Time 10 – – ns tDAT_VAL SPI Output Data Valid Time 0 – 50 ns tDAT_VAL_TRI SPI Output Data Tri-state (MOSI from Slave Select Deassert) – – 20 ns tSS_SU SPI Slave Select Setup Time before first positive edge of SCK[11] 10 – – ns tSS_HLD SPI Slave Select Hold Time after last negative edge of SCK 10 – – ns tSS_PW SPI Slave Select Minimum Pulse Width 20 – – ns tSCK_SU SPI Slave Select Setup Time 10 – – ns tSCK_HLD SPI SCK Hold Time 10 – – ns tRESET Minimum RST Pin Pulse Width 10 – – ns Figure 10. SPI Timing tSCK_CYC tSCK_HI SCK tSCK_LO tSCK_HLD tSCK_SU nSS tSS_SU tDAT_SU tSS_HLD tDAT_HLD MOSI input tDAT_VAL tDAT_VAL_TRI MISO MOSI output Notes 9. AC values are not guaranteed if voltage on any pin exceeding VI/O. 10. CLOAD = 30 pF 11. SCK must start low at the time SS goes LOW, otherwise the success of SPI transactions are not guaranteed. Document Number: 38-16015 Rev. *K Page 18 of 30 CYRF6936 RF Characteristics Radio Parameters Parameter Description Conditions RF Frequency Range Note 12 Receiver (T = 25°C, VCC = VBAT = 3.0 V, fOSC = 12.000000 MHz, BER < 1E-3) Sensitivity 125 kbps 64-8DR BER 1E-3 Min Typ Max Unit 2.400 – 2.497 GHz – –97 – dBm BER 1E-3 – –93 – dBm Sensitivity CER 1E-3 –80 –87 – dBm Sensitivity GFSK BER 1E-3, ALL SLOW = 1 – –84 – dBm Sensitivity 250 kbps 32-8DR LNA Gain – 22.8 – dB ATT Gain – –31.7 – dB Maximum Received Signal LNA On –15 –6 – dBm RSSI Value for PWRin –60 dBm [13] LNA On – 21 – Count – 1.9 – dB/Count RSSI Slope Interference Performance (CER 1E-3) Co-channel Interference rejection Carrier-to-Interference (C/I) C = –60 dBm – 9 – dB Adjacent (±1 MHz) channel selectivity C/I 1 MHz C = –60 dBm – 3 – dB Adjacent (±2 MHz) channel selectivity C/I 2 MHz C = –60 dBm – –30 – dB Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz C = –67 dBm – –38 – dB Out-of-Band Blocking 30 MHz–12.75 MHz [14] C = –67 dBm – –30 – dBm Intermodulation C = –64 dBm, f = 5, 10 MHz – –36 – dBm Receive Spurious Emission 800 MHz 100 kHz ResBW – –79 – dBm 1.6 GHz 100 kHz ResBW – –71 – dBm 3.2 GHz 100 kHz ResBW – –65 – dBm Notes 12. Subject to regulation. 13. RSSI value is not guaranteed. Extensive variation from part to part. 14. Exceptions F/3 & 5C/3. Document Number: 38-16015 Rev. *K Page 19 of 30 CYRF6936 Radio Parameters (continued) Parameter Description Conditions Min Typ Max Unit Transmitter (T = 25°C, VCC = 3.0 V) Maximum RF Transmit Power PA = 7 +2 4 +6 dBm Maximum RF Transmit Power PA = 6 –2 0 +2 dBm Maximum RF Transmit Power PA = 5 –7 –5 –3 dBm Maximum RF Transmit Power PA = 0 – –35 – dBm – 39 – dB RF Power Range Control Step Size Seven steps, monotonic – 5.6 – dB Frequency Deviation Min PN Code Pattern 10101010 – 270 – kHz RF Power Control Range Frequency Deviation Max PN Code Pattern 11110000 – 323 – kHz Error Vector Magnitude (FSK error) >0 dBm – 10 – %rms Occupied Bandwidth –6 dBc, 100 kHz ResBW 500 876 – kHz In-band Spurious Second Channel Power (±2 MHz) – –38 – dBm In-band Spurious Third Channel Power (>3 MHz) – –44 – dBm Non-Harmonically Related Spurs (800 MHz) – –38 – dBm Non-Harmonically Related Spurs (1.6 GHz) – –34 – dBm Non-Harmonically Related Spurs (3.2 GHz) – –47 – dBm Harmonic Spurs (Second Harmonic) – –43 – dBm Harmonic Spurs (Third Harmonic) – –48 – dBm Fourth and Greater Harmonics – –59 – dBm – 0.7 1.3 ms Transmit Spurious Emission (PA = 7) Power Management (Crystal PN# eCERA GF-1200008) Crystal Start to 10ppm Crystal Start to IRQ XSIRQ EN = 1 – 0.6 – ms Synth Settle Slow channels – – 270 µs Synth Settle Medium channels – – 180 µs Synth Settle Fast channels – – 100 µs Link Turnaround Time GFSK – – 30 µs Link Turnaround Time 250 kbps – – 62 µs Link Turnaround Time 125 kbps – – 94 µs Link Turnaround Time <125 kbps – – 31 µs Max Packet Length <60 ppm crystal-to-crystal all modes except 64-DDR and 64-SDR – – 40 bytes Max Packet Length <60 ppm crystal-to-crystal 64-DDR and 64-SDR – – 16 bytes Document Number: 38-16015 Rev. *K Page 20 of 30 CYRF6936 Typical Operating Characteristics Figure 11. Typical Operating Characteristics [15] Transmit Power vs. Temperature (Vcc = 2.7v) Transmit Power vs. Channel Transmit Power vs. Vcc (PMU off) 6 6 PA6 0 -2 -4 PA5 -6 -8 -10 PA4 -12 0 20 2 PA6 0 -2 -4 PA5 -6 -8 -10 PA4 -12 -14 40 -14 2.4 60 Output Power (dBm) 2 2.6 2.8 3 3.2 3.4 PA5 -6 -8 -10 PA4 0 3.6 20 40 20 19 18 ATT ON LNA OFF RSSI Count RSSI Count LNA OFF 80 Average RSSI vs. Vcc (Rx signal = -70dBm) 17 LNA ON 60 Channel 19 24 RSSI Count -4 -12 18 16 15 17 16 15 14 13 14 12 13 11 10 2.4 12 -100 -80 -60 -40 0 -20 20 40 60 RSSI vs. Channel (Rx signal = -70dBm) 12 10 8 6 4 2 0 40 60 -82 -84 -86 CER -88 -90 8DR32 -92 -94 2.4 80 3.2 3.4 3.6 -80 Receiver Sensitivity (dBm) Receiver Sensitivity (dBm) 14 3 Rx Sensitivity vs. Temperature (1Mbps CER) -80 16 20 2.8 Vcc Rx Sensitivity vs. Vcc (1Mbps CER) 18 0 2.6 Temp (deg C) Input Power (dBm) RSSI Count -2 Average RSSI vs. Temperature (Rx signal = -70dBm) 32 0 -120 PA6 0 Vcc Typical RSSI Count vs Input Power 8 2 -14 Temp (deg C) 16 PA7 4 PA7 4 Output Power (dBm) Output Power (dBm) 6 PA7 4 -82 -84 -86 CER -88 -90 8DR32 -92 -94 2.6 2.8 Channel 3 3.2 3.4 3.6 0 20 Vcc Receiver Sensitivity vs. Frequency Offset 40 60 Temp (deg C) Receiver Sensitivity vs Channel (3.0v, Room Temp) Carrier to Interferer (Narrow band, LP modulation) -82 -84 GFSK -86 -88 -90 DDR32 -92 -94 8DR64 -96 -98 -150 -100 -50 0 50 100 Crystal Offset (ppm) 150 -81 20.0 GFSK -83 10.0 0.0 -85 C/I (dB) Receiver Sensitivity (dBm) Receiver Sensitivity (dBm) -80 CER -87 -89 -91 20 -30.0 -50.0 8DR32 -95 0 -20.0 -40.0 DDR32 -93 -10.0 40 Channel 60 80 -60.0 -10 -5 0 5 10 Channel Offset (MHz) Note 15. With LNA on, ATT off, above -2dBm erroneous RSSI values may be read. Cross-checking RSSI with LNA off/on is recommended for accurate readings. Document Number: 38-16015 Rev. *K Page 21 of 30 CYRF6936 Typical Operating Characteristics (continued) 10 10 3 1 1 GFSK vs. BER (SOP Threshold = 5, C38 slow) BER vs. Data Threshold (32-8DR) (SOP Threshold = 5, C38 slow) BER vs. Data Threshold (32-DDR) (SOP Threshold = 5, C38 slow) 0 100 0 Thru 7 10 1 6 0.01 0.01 0.001 0.001 0.0001 0.0001 0.00001 -100 -95 -90 -85 -80 -75 0.0001 -95 -90 ICC RX (LNA OFF) -70 19 18.5 18 17.5 3.3 3.0 2.7 2.4 24 23.5 23 22.5 V V V V 22 21.5 21 20.5 20 19.5 17 19 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 0 5 0 5 16 V V V V 15.5 15 14.5 16.5 16 15 14.5 5 0 10 15 20 25 30 35 40 45 50 55 60 65 70 16 15.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) Document Number: 38-16015 Rev. *K 10 15 20 25 30 35 40 45 50 55 60 65 70 ICC TX @ PA4 20.5 3.3 3.0 2.7 2.4 18.5 18 V V V V 17.5 17 16.5 16 3.3 3.0 2.7 2.4 20 19.5 19 V V V V 18.5 18 17.5 17 15.5 15 5 TEMPERATURE (C) OPERATING CURRENT (mA) 16.5 OPERATING CURRENT (mA) 17 V V V V 15.5 19 V V V V 3.3 3.0 2.7 2.4 17 ICC TX @ PA3 ICC TX @ PA2 3.3 3.0 2.7 2.4 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 18 V V V V 14 0 TEMPERATURE (C) 17.5 0 ICC TX @ PA1 OPERATING CURRENT (mA) 3.3 3.0 2.7 2.4 16.5 10 15 20 25 30 35 40 45 50 55 60 65 70 -20 17.5 14 0 5 ICC TX @ PA0 OPERATING CURRENT (mA) V V V V -40 TEMPERATURE (C) 17 3.3 3.0 2.7 2.4 3.3 3.0 2.7 2.4 TEMPERATURE (C) ICC TX SYNTH 9.2 9.1 9 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8 7.9 7.8 9.2 9.1 9 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8 7.9 7.8 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) -60 ICC RX SYNTH OPERATING CURRENT (mA) 19.5 V V V V -80 Input Power (dBm) ICC RX (LNA ON) OPERATING CURRENT (mA) OPERATING CURRENT (mA) -75 24.5 3.3 3.0 2.7 2.4 20 OPERATING CURRENT (mA) -80 25 21 OPERATING CURRENT (mA) -85 GFSK 0.00001 -100 Input Power (dBm) Input Power (dBm) 20.5 0.01 0.001 0.00001 -100 -70 0.1 %BER %BER %BER 1 0.1 0.1 16.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) Page 22 of 30 CYRF6936 Typical Operating Characteristics (continued) ICC TX @ PA5 3.3 3.0 2.7 2.4 22 29.5 V V V V 21.5 21 20.5 20 3.3 3.0 2.7 2.4 29 28.5 28 V V V V OPERATING CURRENT (mA) 23 22.5 OPERATING CURRENT (mA) OPERATING CURRENT (mA) ICC TX @ PA7 ICC TX @ PA6 30 23.5 27.5 27 26.5 26 25.5 25 19.5 24.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 0 40.5 40 39.5 39 38.5 38 37.5 37 36.5 36 35.5 35 34.5 34 33.5 33 32.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 3.3 3.0 2.7 2.4 V V V V 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) TEMPERATURE (C) AC Test Loads and Waveforms for Digital Pins Figure 12. AC Test Loads and Waveforms for Digital Pins AC Test Loads DC Test Load OUTPUT OUTPUT INCLUDING JIG AND SCOPE VCC 5 pF 30 pF R1 OUTPUT INCLUDING JIG AND Typical SCOPE Max R2 ALL INPUT PULSES Parameter R1 R2 RTH VTH VCC 1071 937 500 1.4 3.00 Document Number: 38-16015 Rev. *K Unit V V VCC GND 90% 10% Rise time: 1 V/ns 90% 10% Fall time: 1 V/ns THÉVENIN EQUIVALENT RTH VTH OUTPUT Equivalent to: Page 23 of 30 CYRF6936 Ordering Information Radio Package Name CYRF6936-40LFXC Part Number Transceiver 40-pin QFN 40-pin QFN (Pb-free) Package Type Commercial Operating Range CYRF6936-40LTXC Transceiver 40-pin QFN 40-pin QFN (Sawn type) Commercial Ordering Code Definitions CY RF 6936 - 40 XX X C Temperature Range: C = Commercial Pb-free Package Type: XX = LF or LT LF = 40-pin QFN LT = 40-pin QFN (Sawn Type) No of pins in package / KGD Level: 40 = 40 pins Part Number Marketing Code: RF = Wireless (radio frequency) product line Company ID: CY = Cypress Document Number: 38-16015 Rev. *K Page 24 of 30 CYRF6936 Package Diagram The recommended dimension of the PCB pad size for the E-PAD underneath the QFN is 3.5 mm × 3.5 mm (width × length). Figure 13. 40-pin QFN (6 × 6 × 1.0 mm) 3.5 × 3.5 E-Pad (Subcon Punch Type Package) Package Outline, 001-12917 001-12917 *D Document Number: 38-16015 Rev. *K Page 25 of 30 CYRF6936 Package Diagram (continued) The recommended dimension of the PCB pad size for the E-PAD underneath the QFN is 3.5 mm × 3.5 mm (width × length). Figure 14. 40-pin QFN (6 × 6 × 0.90 mm) 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-44328 001-44328 *F Document Number: 38-16015 Rev. *K Page 26 of 30 CYRF6936 Acronyms Document Conventions Table 6. Acronyms Used in this Document Units of Measure Acronym Description Table 7. Units of Measure ACK Acknowledge (packet received, no errors) BER Bit Error Rate dB decibel BOM Bill Of Materials dBc decibel relative to carrier CMOS Complementary Metal Oxide Semiconductor dBm decibel-milliwatt CRC Cyclic Redundancy Check °C degree Celsius GFSK Gaussian Frequency-Shift Keying Hz hertz HBM Human Body Model KB 1024 bytes Kbit 1024 bits kHz kilohertz k kilohm MHz megahertz M megaohm Symbol Units of Measure ISM Industrial, Scientific, and Medical IRQ Interrupt Request MCU Microcontroller Unit QFN Quad Flat No-leads RSSI Received Signal Strength Indication A microampere RF Radio Frequency s microsecond Rx Receive V microvolt Tx Transmit Vrms microvolts root-mean-square W microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt ohm pp peak-to-peak ppm parts per million ps picosecond V volt Document Number: 38-16015 Rev. *K Page 27 of 30 CYRF6936 Document History Page Description Title: CYRF6936, WirelessUSB™ LP 2.4 GHz Radio SoC Document Number: 38-16015 Revision ECN Orig. of Change Submission Date ** 307437 TGE See ECN New data sheet *A 377574 TGE See ECN Preliminary release– - updated Section 1.0 - Features - updated Section 2.0 - Applications - added Section 3.0 - Applications Support - updated Section 4.0 - Functional Descriptions - updated Section 5.0 - Pin Description - added Figure 5-1 - updated Section 6.0 - Functional Overview - added Section 7.0 - Functional Block Overview - added Section 9.0 - Register Descriptions - updated Section 10.0 - Absolute Maximum Ratings - updated Section 11.0 - Operating Conditions - updated Section 12.0 - DC Characteristics - updated Section 13.0 - AC Characteristics - updated Section 14.0 - RF Characteristics - added Section 16.0 - Ordering Information *B 398756 TGE See ECN ES-10 update- changed part no. - updated Section 9.0 - Register Descriptions - updated Section 12.0 - DC Characteristics - updated Section 14.0 - RF Characteristics *C 412778 TGE See ECN ES-10 update- updated Section 4.0 - Functional Descriptions - updated Section 5.0 - Pin Descriptions - updated Section 6.0 - Functional Overview - updated Section 7.0 - Functional Block Overview - updated Section 9.0 - Register Descriptions - updated Section 10.0 - Absolute Maximum Ratings - updated Section 11.0 - Operating Conditions - updated Section 14.0 - RF Characteristics *D 435578 TGE See ECN - updated Section 1.0 - Features - updated Section 5.0 - Pin Descriptions - updated Section 6.0 - Functional Overview - updated Section 7.0 - Functional Block Overview - updated Section 9.0 - Register Descriptions - added Section 10.0 - Recommended Radio Circuit Schematic - updated Section 11.0 - Absolute Maximum Ratings - updated Section 12.0 - Operating Conditions - updated Section 13.0 - DC Characteristics - updated Section 14.0 - AC Characteristics - updated Section 15.0 - RF Characteristics *E 460458 BOO See ECN Final data sheet - removed “Preliminary” notation Document Number: 38-16015 Rev. *K Description of Change Page 28 of 30 CYRF6936 Document History Page (continued) Description Title: CYRF6936, WirelessUSB™ LP 2.4 GHz Radio SoC Document Number: 38-16015 Revision ECN Orig. of Change Submission Date *F 487261 TGE See ECN - updated Section 1.0 - Features - updated Section 5.0 - Pin Descriptions - updated Section 6.0 - Functional Overview - updated Section 7.0 - Functional Block Overview - updated Section 8.0 - Application Example - updated Section 9.0 - Register Descriptions - updated Section 12.0 - DC Characteristics - updated Section 13.0 - AC Characteristics - updated Section 14.0 - RF Characteristics - added Section 15.0 - Typical Operating Characteristics *G 778236 OYR / ARI See ECN - modified radio function register descriptions - changed L/D pin description - footnotes added - changed RST Capacitor from 0.1uF to 0.47 uF - updated Figure 9, Recommended Circuit for Systems - updated Table 3, Recommended bill of materials for systems - updated package diagram from ** to *A *H 2640987 VNY / OYR / TGE / AESA 02/20/2009 - Removed range values in features description - Bit level register details removed and appended to the Wireless LP and PRoC TRM - updated register summary table 4 - updated pin description diagram (figure 1) - updated the schematic of the radio (figure 10). - Removed Backward Compatibility section. - Removed Table 2 - Updated RF table characteristics for Payload size - Added pkg diagram 001-12917 - Updated BOM Table 3 on page 11. - Updated Table on page 19 with Receiver information (T = 25°C, VCC = VBAT = 3.0 V, fOSC = 12.000000 MHz, BER < 1E-3) *I 2673333 TGE / PYRS 03/13/2009 Corrected Figure 9 on page 13 Updated packaging and ordering information for 40 QFN (sawn) package *J 3232571 JCJC 04/18/2011 Added section Receive Spurious Response on page 9. Added note # 13 and referred in Table on page 19. Updated template as per new Cypress standards. Added ordering code definitions, acronyms, and units of measure. Updated package diagrams: 001-12917: *A to *C 001-44328: *C to *D *K 4359286 DEJO 04/24/2014 Updated Package Diagram: spec 001-12917 – Changed revision from *C to *D. spec 001-44328 – Changed revision from *D to *F. Description of Change Updated in new template. Completing Sunset Review. Document Number: 38-16015 Rev. *K Page 29 of 30 CYRF6936 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF Technical Support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2005-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-16015 Rev. *K Revised April 24, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 30 of 30