GS8662T08/09/18/36E-250/200/167
72Mb SigmaDDR-II™
Burst of 2 SRAM
• Simultaneous Read and Write SigmaDDR-II™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and 144Mb
devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
Each internal read and write operation in a SigmaDDR-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 is used to initialize the pointers that control the data
multiplexer / de-multiplexer so the RAM can perform "critical
word first" operations. From an external address point of view,
regardless of the starting point, the data transfers always follow
the same sequence {0, 1} or {1, 0} (where the digits shown
represent A0).
De
sig
SigmaDDR-II™ Family Overview
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
ct
Features
250 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
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165-Bump BGA
Commercial Temp
Industrial Temp
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The GS8662T08/09/18/36E are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662T08/09/18/36E SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
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The GS8662T08/09/18/36E SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B2 RAMs are one address pin less than the advertised index
depth (e.g., the 8M x 8 has an 4M addressable index, and A0 is
not an accessible address pin).
Rev: 1.10 8/2012
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
-250
-200
-167
tKHKH
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.45 ns
0.5 ns
ct
Parameter Synopsis
3
4
5
A
CQ
MCL/SA
(144Mb)
SA
R/W
BW2
B
NC
DQ27
DQ18
SA
BW3
C
NC
NC
DQ28
VSS
SA
D
NC
DQ29
DQ19
VSS
VSS
E
NC
NC
DQ20
VDDQ
VSS
F
NC
DQ30
DQ21
VDDQ
VDD
G
NC
DQ31
DQ22
VDDQ
VDD
H
Doff
VREF
VDDQ
VDDQ
J
NC
NC
DQ32
K
NC
NC
DQ23
L
NC
DQ33
M
NC
NC
N
NC
DQ35
P
NC
NC
R
TDO
7
8
9
10
11
K
BW1
LD
SA
SA
CQ
K
BW0
SA
NC
NC
DQ8
SA0
SA
VSS
NC
DQ17
DQ7
VSS
VSS
VSS
NC
NC
DQ16
VSS
VSS
VDDQ
NC
DQ15
DQ6
VSS
VDD
VDDQ
NC
NC
DQ5
VSS
VDD
VDDQ
NC
NC
DQ14
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
me
nd
ed
for
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
DQ25
VSS
SA
SA
SA
VSS
NC
NC
DQ10
DQ26
SA
SA
C
SA
SA
NC
DQ9
DQ0
SA
SA
C
SA
SA
SA
TMS
TDI
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TCK
6
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2
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1
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2M x 36 SigmaDDR-II SRAM—Top View
SA
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
No
t
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35.
2. MCL = Must Connect Low
Rev: 1.10 8/2012
2/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
4M x 18 SigmaDDR-II SRAM—Top View
2
3
4
5
6
7
8
9
10
11
A
CQ
SA
SA
R/W
BW1
K
NC
LD
SA
SA
CQ
B
NC
DQ9
NC
SA
NC
K
BW0
SA
NC
NC
DQ8
C
NC
NC
NC
VSS
SA
SA0
SA
VSS
NC
DQ7
NC
D
NC
NC
DQ10
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
N
NC
NC
DQ16
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
R
TDO
TCK
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1
DQ17
SA
SA
C
SA
SA
NC
NC
DQ0
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
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Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17.
2. MCL = Must Connect Low
Rev: 1.10 8/2012
3/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
8M x 9 SigmaDDR-II SRAM—Top View
2
3
4
5
6
7
8
9
10
11
A
CQ
SA
SA
R/W
NC
K
NC
LD
SA
SA
CQ
B
NC
NC
NC
SA
NC
K
BW
SA
NC
NC
DQ4
C
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ5
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ2
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ7
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
R
TDO
TCK
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ct
1
DQ8
SA
SA
C
SA
SA
NC
NC
DQ0
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
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Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0. SA0 is set to 0 at the beginning
of each access.
2. MCL = Must Connect Low
Rev: 1.10 8/2012
4/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
8M x 8 SigmaDDR-II SRAM—Top View
2
3
4
5
6
7
8
9
10
11
A
CQ
SA
SA
R/W
NW1
K
NC
LD
SA
SA
CQ
B
NC
NC
NC
SA
NC
K
NW0
SA
NC
NC
DQ3
C
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
R
TDO
TCK
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1
DQ7
SA
SA
C
SA
SA
NC
NC
NC
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
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Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0. SA0 is set to 0 at the beginning
of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7
3. MCL = Must Connect Low
Rev: 1.10 8/2012
5/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Pin Description Table
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
NC
No Connect
—
—
R/W
Synchronous Read/Write
Input
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Pr
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Symbol
—
Input
Active Low
x18/x36 only
Input
Active Low
x8 only
Input
Active Low
Input
Active High
Input
Active Low
Input
Active High
Input
Active Low
Input
—
Input
—
Input
—
Output
—
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
MCL
Must Connect Low
—
—
DQ
Data I/O
Input/Output
Three State
Doff
Disable DLL when low
Input
Active Low
CQ
Output Echo Clock
Output
—
Output Echo Clock
Output
—
Power Supply
Supply
1.8 V Nominal
Isolated Output Buffer Supply
Supply
1.5 V Nominal
Power Supply: Ground
Supply
—
Synchronous Byte Writes
NW0–NW1
Nybble Write Control Pin
LD
Synchronous Load Pin
K
Input Clock
K
Input Clock
C
Output Clock
C
Output Clock
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock Input
TDO
Test Data Output
VREF
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for
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BW0–BW3
CQ
VDD
VDDQ
VSS
No
t
Re
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Notes:
1. NC = Not Connected to die or any other pin
2. C, C, K, or K cannot be set to VREF voltage.
Rev: 1.10 8/2012
6/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Background
ct
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are
unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
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Pr
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Burst Operations
Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in
the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often,
if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM from
loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer
operations.
SigmaDDR-II B2 SRAM Read Cycles
Ne
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SigmaDDR-II B2 SRAM Write Cycles
De
sig
The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read
command (LD low and R/W high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM
produces data out in response to the next rising edge of C (or the next rising edge of K, if C and C are tied high). The second beat
of data is transferred on the next rising edge of C, for a total of two transfers per address load.
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for
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.
Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command
(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures
data in on the next rising edge of K, for a total of two transfers per address load.
Rev: 1.10 8/2012
7/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Special Functions
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Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device,
“Nybble Write Enable” and “NBx” may be substituted in all the discussion above.
Data In Sample Time
BW0
BW1
Beat 1
0
1
Beat 2
1
0
Resulting Write Operation
Byte 2
D9–D17
Written
Unchanged
D0–D8
D9–D17
Data In
Don’t Care
Don’t Care
Data In
Byte 3
D0–D8
Byte 4
D9–D17
Unchanged
Written
Beat 2
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for
Beat 1
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Byte 1
D0–D8
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Example x18 RAM Write Sequence using Byte Write Enables
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Output Register Control
SigmaDDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
Rev: 1.10 8/2012
8/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Example Four Bank Depth Expansion Schematic
LD3
LD2
LD0
R/W
A0–An
K
Bank 1
A
A
LD
LD
R/W
R/W
K
CQ
K
DQ
C
C
Bank 2
Bank 3
A
A
LD
LD
R/W
R/W
K CQ
DQ
K
C
C
CQ
DQ
me
nd
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for
C
CQ
Ne
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DQ
De
sig
Bank 0
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inu
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Pr
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ct
LD1
DQ1–DQn
CQ
No
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Note:
For simplicity BWn (or NWn), K, and C are not shown.
Rev: 1.10 8/2012
9/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
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FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Rev: 1.10 8/2012
10/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
B2 Byte Write Clock Truth Table
BW
Current Operation
K↑
(tn+1)
K↑
(tn+2)
K↑
(tn)
T
T
T
D
ct
BW
D
K↑
(tn+2)
Write
Dx stored if BWn = 0 in both data transfers
D1
D2
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D1
X
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D2
F
F
Write Abort
No Dx stored in either data transfer
X
X
Current Operation
D
D
K↑
(tn)
K↑
(tn+1)
K↑
(tn+2)
Write
Dx stored if NWn = 0 in both data transfers
D1
D2
Write
Dx stored if NWn = 0 in 1st data transfer only
D1
X
n—
Di
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inu
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Pr
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u
K↑
(tn+1)
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B2 Nybble Write Clock Truth Table
De
sig
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
NW
K↑
(tn+1)
K↑
(tn+2)
T
T
T
F
F
T
Write
Dx stored if NWn = 0 in 2nd data transfer only
X
D2
F
F
Write Abort
No Dx stored in either data transfer
X
X
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for
NW
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
Rev: 1.10 8/2012
11/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
x36 Byte Write Enable (BWn) Truth Table
BW1
BW2
BW3
D0–D8
D9–D17
D18–D26
D27–D35
1
1
1
1
Don’t Care
Don’t Care
Don’t Care
Don’t Care
0
1
1
1
Data In
Don’t Care
Don’t Care
Don’t Care
1
0
1
1
Don’t Care
Data In
Don’t Care
Don’t Care
0
0
1
1
Data In
Data In
Don’t Care
Don’t Care
1
1
0
1
Don’t Care
Don’t Care
Data In
Don’t Care
0
1
0
1
Data In
Don’t Care
Data In
Don’t Care
1
0
0
1
Don’t Care
Data In
Data In
Don’t Care
0
0
0
1
Data In
Data In
Data In
Don’t Care
1
1
1
0
Don’t Care
Don’t Care
Don’t Care
Data In
0
1
1
0
Data In
Don’t Care
Don’t Care
Data In
1
0
1
0
Don’t Care
Data In
Don’t Care
Data In
0
0
1
0
Data In
Data In
Don’t Care
Data In
1
1
0
0
Don’t Care
Don’t Care
Data In
Data In
0
1
0
0
Data In
Don’t Care
Data In
Data In
1
0
0
0
Don’t Care
Data In
Data In
Data In
0
0
0
0
Data In
Data In
Data In
Data In
1
1
0
1
1
0
0
0
n—
Di
sco
nt
inu
ed
Pr
od
u
De
sig
D0–D8
D9–D17
Don’t Care
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Data In
NW1
D0–D3
D4–D7
1
Don’t Care
Don’t Care
1
Data In
Don’t Care
0
Don’t Care
Data In
0
Data In
Data In
me
nd
ed
for
BW1
Re
co
m
BW0
Ne
w
x18 Byte Write Enable (BWn) Truth Table
ct
BW0
x8 Nybble Write Enable (NWn) Truth Table
NW0
0
1
No
t
1
0
*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.
Rev: 1.10 8/2012
12/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 2.9
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
VREF
Voltage in VREF Pins
VI/O
Voltage on I/O Pins
VIN
Voltage on Other Input Pins
IIN
Input Current on Any Pin
IOUT
Output Current on Any I/O Pin
TJ
Maximum Junction Temperature
TSTG
Storage Temperature
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Symbol
V
–0.5 to VDDQ
V
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
V
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
V
+/–100
mA dc
+/–100
mA dc
o
125
C
oC
–55 to 125
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
De
sig
Recommended Operating Conditions
Power Supplies
Supply Voltage
Min.
Typ.
Max.
Unit
VDD
1.7
1.8
1.9
V
VDDQ
1.4
—
1.9
V
0.68
—
0.95
V
me
nd
ed
for
I/O Supply Voltage
Reference Voltage
Symbol
Ne
w
Parameter
VREF
Note:
The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power
down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
Operating Temperature
Symbol
Min.
Typ.
Max.
Unit
Ambient Temperature
(Commercial Range Versions)
TA
0
25
70
°C
Ambient Temperature
(Industrial Range Versions)
TA
–40
25
85
°C
No
t
Re
co
m
Parameter
Rev: 1.10 8/2012
13/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Thermal Impedance
Test PCB
Substrate
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W)
θ JC (C°/W)
165 BGA
4-layer
16.3
13.4
12.4
6.2
1.5
ct
Package
HSTL I/O DC Input Characteristics
Parameter
Symbol
DC Input Logic High
VIH (dc)
DC Input Logic Low
VIL (dc)
n—
Di
sco
nt
inu
ed
Pr
od
u
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
Min
Max
Units
Notes
VREF + 0.10
VDDQ + 0.3 V
V
1
–0.3 V
VREF – 0.10
V
1
AC Input Logic High
AC Input Logic Low
VREF Peak-to-Peak AC Voltage
Symbol
Min
Max
Units
Notes
VIH (ac)
VREF + 0.20
—
V
2,3
VIL (ac)
—
VREF – 0.20
V
2,3
VREF (ac)
—
5% VREF (DC)
V
1
me
nd
ed
for
Parameter
Ne
w
HSTL I/O AC Input Characteristics
De
sig
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers.
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
3. VIL (Min) DC = –0.3 V, VIL(Min) AC = –1.5 V (pulse width ≤ 3 ns).
4. VIH (Max) DC = VDDQ + 0.3 V, VIH(Max) AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
No
t
Re
co
m
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Rev: 1.10 8/2012
14/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKHKH
VDD + 1.0 V
VSS
n—
Di
sco
nt
inu
ed
Pr
od
u
50%
ct
50%
VDD
VSS – 1.0 V
20% tKHKH
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Symbol
Input Capacitance
CIN
Output Capacitance
COUT
Clock Capacitance
CCLK
Input high level
Unit
VIN = 0 V
4
5
pF
VOUT = 0 V
6
7
pF
—
5
6
pF
Conditions
VDDQ
0V
me
nd
ed
for
Input low level
Max.
Ne
w
AC Test Conditions
Parameter
Typ.
De
sig
Note:
This parameter is sample tested.
Test conditions
Max. input slew rate
2 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
Re
co
m
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
No
t
DQ
Rev: 1.10 8/2012
50Ω
RQ = 250 Ω (HSTL I/O)
VREF = 0.75 V
VT = VDDQ/2
15/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Symbol
Test Conditions
Min.
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–2 uA
2 uA
Doff
IINDOFF
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–2 uA
2 uA
2 uA
Output Leakage Current
IOL
Output Disable,
VOUT = 0 to VDDQ
–2 uA
2 uA
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
ct
Input and Output Leakage Characteristics
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Symbol
Min.
Max.
Units
Notes
VOH1
VDDQ/2
VDDQ
V
1, 3
VOL1
Vss
VDDQ/2
V
2, 3
VOH2
VDDQ – 0.2
VDDQ
V
4, 5
VOL2
Vss
0.2
V
4, 6
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V
4. 0Ω ≤ RQ ≤ ∞Ω
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Rev: 1.10 8/2012
16/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Operating Currents
Symbol
Test Conditions
Operating Current (x36):
DDR
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
Operating Current (x18):
DDR
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
Operating Current (x9):
DDR
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
Operating Current (x8):
DDR
IDD
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
Standby Current (NOP):
DDR
ISB1
Device deselected,
IOUT = 0 mA, f = Max,
All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V
Notes:
Notes
0
to 70°C
–40
to
85°C
0
to 70°C
–40
to
85°C
775 mA
650 mA
675 mA
550 mA
575 mA
2, 3
700 mA
725 mA
600 mA
625 mA
525 mA
550 mA
2, 3
700 mA
725 mA
575 mA
600 mA
525 mA
550 mA
2, 3
700 mA
725 mA
575 mA
600 mA
525 mA
550 mA
2, 3
255 mA
265 mA
245 mA
255 mA
300 mA
310 mA
2, 4
0
to 70°C
–40
to
85°C
750 mA
De
sig
Power measured with output pins floating.
Minimum cycle, IOUT = 0 mA
Operating current is calculated with 50% read cycles and 50% write cycles.
Standby Current is only after all pending read and write burst operations are completed.
No
t
Re
co
m
me
nd
ed
for
Ne
w
1.
2.
3.
4.
-167
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
-200
ct
-250
Rev: 1.10 8/2012
17/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Parameter
-250
Symbol
-200
-167
Units
Min
Max
Min
Max
Min
Max
8.4
ns
Notes
AC Electrical Characteristics
Clock
tKHKH
tCHCH
4.0
8.4
5.0
8.4
6.0
tTKC Variable
tKCVar
—
0.2
—
0.2
—
0.2
ns
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.6
—
2.0
—
2.4
—
ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.6
—
2.0
—
2.4
—
ns
K to K High
C to C High
tKHKH
tCHCH
1.8
—
2.2
—
2.7
—
ns
K to K High
C to C High
tKHKH
tCHCH
1.8
—
2.2
—
2.7
—
ns
K, K Clock High to C, C Clock High
tKHCH
0
1.8
0
2.3
0
2.8
ns
DLL Lock Time
tKCLock
1024
—
1024
—
1024
—
cycle
K Static to DLL reset
tKCReset
30
—
30
—
30
—
ns
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
—
0.45
—
0.45
—
0.5
ns
4
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
tKHQX
tCHQX
–0.45
—
–0.45
—
–0.5
—
ns
4
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
tKHCQV
tCHCQV
—
0.45
—
0.45
—
0.5
ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
tKHCQX
tCHCQX
–0.45
—
–0.45
—
–0.5
—
ns
tCQHQV
—
0.30
—
0.35
—
0.40
ns
8
tCQHQX
–0.30
—
–0.35
—
–0.40
—
ns
8
tCQHCQH
tCQHCQH
1.55
—
1.95
—
2.45
—
ns
tKHQZ
tCHQZ
—
0.45
—
0.45
—
0.5
ns
4
tKHQX1
tCHQX1
–0.45
—
–0.45
—
–0.5
—
ns
4
tAVKH
0.5
—
0.6
—
0.7
—
ns
1
tIVKH
0.5
—
0.6
—
0.7
—
ns
2
Control Input Setup Time (BWX, NWX)
tIVKH
0.35
—
0.4
—
0.5
—
ns
3
Data Input Setup Time
tDVKH
0.35
—
0.4
—
0.5
—
ns
CQ, CQ High Output Hold
CQ Phase Distortion
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
Setup Times
Address Input Setup Time
Re
co
m
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
No
t
Control Input Setup Time (R/W, LD)
Rev: 1.10 8/2012
Ne
w
me
nd
ed
for
CQ, CQ High Output Valid
n—
Di
sco
nt
inu
ed
Pr
od
u
De
sig
Output Times
ct
K, K Clock Cycle Time
C, C Clock Cycle Time
18/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
6
6
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Parameter
-250
Symbol
-200
-167
Min
Max
Min
Max
Min
Max
Units
Notes
AC Electrical Characteristics (Continued)
Hold Times
tKHAX
0.5
—
0.6
—
0.7
—
ns
1
Control Input Hold Time (R/W, LD)
tKHIX
0.5
—
0.6
—
0.7
—
ns
2
Control Input Hold Time (BWX, NWX)
tIVKH
0.35
—
0.4
—
0.5
—
ns
3
Data Input Hold Time
tKHDX
0.35
—
0.4
—
0.5
—
ns
1.
2.
3.
4.
5.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
Control signals are R/W, LD
Control signals BW0, BW1, (NW0, NW1 for x8) and BW2, BW3 for x36.
If C, C are tied high, K, K become the references for C, C timing parameters
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
6.
7.
8.
n—
Di
sco
nt
inu
ed
Pr
od
u
Notes:
ct
Address Input Hold Time
Rev: 1.10 8/2012
19/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
Rev: 1.10 8/2012
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
20/34
CQ
CQ
DQ
C
C
BWx
R/W
LD
Address
K
No
t
K
IVKH
KHKH
A
IVKH
KHAX
AVKH
KHKL
Read A
KHIX
KHKH
KHKL
KHIX
me
nd
ed
for
Re
co
m
NOP
B
CHCQV
CHCQX
KLKH
KHnKH
De
sig
KHnKH
Ne
w
KLKH
Read B
A
A+1
CHQX1
C
Write C
B+1
C
D
DVKH
KHIX
IVKH
Read D
C+1
CQHQV
CQHQX
B
C
CHQX
C+1
n—
Di
sco
nt
inu
ed
Pr
od
u
CHQV
NOP
C and C Controlled Read First Timing Diagram
ct
KHDX
GS8662T08/09/18/36E-250/200/167
© 2005, GSI Technology
Rev: 1.10 8/2012
CQ
CQ
DQ1
BWx
R/W
LD
Address
K
No
t
K
BVKH
KHKH
A
KHCQX
KHCQV
KHBX
BVKH
KLKH
B
KHBX
KHCQV
KHCQX
Ne
w
KHAX
AVKH
KHKL
Read A
me
nd
ed
for
Re
co
m
NOP
A+1
NOP
B
KHQV
C
B+1
Write C
KHQX
C
D
DVKH
C+1
KHBX
BVKH
Read D
A
CQHQV
CQHQX
C
C+1
n—
Di
sco
nt
inu
ed
Pr
od
u
KHQX1
De
sig
KHnKH
Read B
K and K Controlled Read First Timing Diagram
ct
KHDX
GS8662T08/09/18/36E-250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
21/34
© 2005, GSI Technology
Rev: 1.10 8/2012
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
22/34
CQ
CQ
DQ
C
C
BWx
R/W
LD
CHCQX
IVKH
A
KHKH
CHCQV
KHIX
CHCQX
B
KHKH
C
DVKH
A+1
KHKL
A+1
KHIX
KHnKH
KHnKH
Read C
CHQX1
D
NOP
CHQV
C
E
Write D
CHQX
D
KHDX
B
CQHQV
B+1
CQHQX
C+1
D
ct
NOP
n—
Di
sco
nt
inu
ed
Pr
od
u
KLKH
KLKH
De
sig
CHCQV
A
A
IVKH
KHIX
IVKH
KHKL
Read B
Ne
w
KHAX
AVKH
Write A
me
nd
ed
for
Re
co
m
K
Address
No
t
K
NOP
C and C Controlled Write First Timing Diagram
D+1
D+1
GS8662T08/09/18/36E-250/200/167
© 2005, GSI Technology
Rev: 1.10 8/2012
KHAX
CQ
CQ
KHCQX
KHCQV
A
DVKH
KLKH
KHDX
C
A+1
A+1
KHQX1
D
NOP
KHQV
C
E
KHQX
Write D
D
NOP
B
CQHQV
B+1
CQHQX
C+1
D
n—
Di
sco
nt
inu
ed
Pr
od
u
KHnKH
Read C
De
sig
KHBX
BVKH
KHBX
BVKH
KHKL
Read B
Ne
w
DQ
KHCQV
KHBX
B
A
KHCQX
BVKH
A
AVKH
KHKH
me
nd
ed
for
Re
co
m
Write A
BWx
R/W
LD
Address
K
No
t
K
NOP
K and K Controlled Write First Timing Diagram
ct
D+1
D+1
GS8662T08/09/18/36E-250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
23/34
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
JTAG Port Operation
ct
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDD.
n—
Di
sco
nt
inu
ed
Pr
od
u
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin Name
I/O
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Test Data In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Ne
w
TDI
Description
De
sig
Pin
JTAG Port Registers
me
nd
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for
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
Re
co
m
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
No
t
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.10 8/2012
24/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
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Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
0
De
sig
Bypass Register
0
108
1
·
2 1 0
Instruction Register
Ne
w
TDI
TDO
ID Code Register
·
· ··
2 1 0
me
nd
ed
for
31 30 29
Control Signals
TMS
TCK
Test Access Port (TAP) Controller
No
t
Re
co
m
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.10 8/2012
25/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
GSI Technology
JEDEC Vendor
ID Code
Bit #
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Not Used
Presence Register
ID Register Contents
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
Tap Controller Instruction Set
X
X
X
X
X
X
X
0
0 0 1 1 0 1 1 0 0 1
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
No
t
Re
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me
nd
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for
Ne
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De
sig
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.10 8/2012
26/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
Run Test Idle
1
Select DR
1
0
1
Capture DR
0
Capture IR
0
Shift DR
1
1
ct
0
1
Shift IR
0
1
1
Exit1 DR
0
Exit1 IR
0
0
Pause DR
1
Exit2 DR
De
sig
1
Update DR
0
0
Pause IR
1
Exit2 IR
0
1
0
0
Update IR
1
0
Ne
w
1
1
Select IR
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Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
No
t
Re
co
m
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 1.10 8/2012
27/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
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Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z except CQ.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
Places Bypass Register between TDI and TDO.
1
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Description
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Code
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Instruction
De
sig
JTAG TAP Instruction Set Summary
BYPASS
111
No
t
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.10 8/2012
28/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
JTAG Port Recommended Operating Conditions and DC Characteristics
Symbol
Min.
Max.
Unit Notes
Test Port Input Low Voltage
VILJ
–0.3
0.3 * VDD
V
1
Test Port Input High Voltage
VIHJ
0.6 * VDD
VDD +0.3
V
1
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Parameter
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
IINHJ
–300
1
uA
2
IINLJ
–1
100
uA
3
IOLJ
–1
1
uA
4
VOHJ
VDD – 200 mV
—
V
5, 6
VOLJ
—
0.4
V
5, 7
VOHJC
VDD – 100 mV
—
V
5, 8
VOLJC
—
100 mV
V
5, 9
me
nd
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for
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sig
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDD supply.
6. IOHJ = –2 mA
7. IOLJ = + 2 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Input high level
Re
co
m
Input low level
Conditions
VDD – 0.2 V
JTAG Port AC Test Load
TDO
0.2 V
1 V/ns
Input reference level
VDD/2
Output reference level
VDD/2
50Ω
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
No
t
Input slew rate
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.10 8/2012
29/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
tTH
tTS
TMS
tTKQ
TDO
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
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Pr
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tTH
tTS
ct
TDI
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
50
—
TCK Low to TDO Valid
tTKQ
—
TCK High Pulse Width
tTKH
20
TCK Low Pulse Width
tTKL
20
TDI & TMS Set Up Time
tTS
10
—
ns
TDI & TMS Hold Time
tTH
10
—
ns
De
sig
ns
ns
—
ns
—
ns
No
t
Re
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for
Ne
w
20
Rev: 1.10 8/2012
30/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW
Ø0.10 M C
Ø0.25 M C A B
Ø0.40~0.60 (165x)
ct
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER
1.0
14.0
Ne
w
10.0
15±0.05
0.20(4x)
No
t
Re
co
m
C
1.0
0.36~0.46
1.50 MAX.
SEATING PLANE
B
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
me
nd
ed
for
0.20 C
A
De
sig
17±0.05
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
n—
Di
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ed
Pr
od
u
11 10 9 8 7 6 5 4 3 2 1
Rev: 1.10 8/2012
31/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Ordering Information—GSI SigmaDDR-II SRAM
Speed
(MHz)
TA2
250
C
165-bump BGA
200
C
SigmaDDR-II B2 SRAM
165-bump BGA
167
C
GS8662T08E-250I
SigmaDDR-II B2 SRAM
165-bump BGA
250
I
8M x 8
GS8662T08E-200I
SigmaDDR-II B2 SRAM
165-bump BGA
200
I
8M x 8
GS8662T08E-167I
SigmaDDR-II B2 SRAM
165-bump BGA
167
I
8M x 9
GS8662T09E-250
SigmaDDR-II B2 SRAM
165-bump BGA
250
C
8M x 9
GS8662T09E-200
SigmaDDR-II B2 SRAM
165-bump BGA
200
C
8M x 9
GS8662T09E-167
SigmaDDR-II B2 SRAM
165-bump BGA
167
C
8M x 9
GS8662T09E-250I
SigmaDDR-II B2 SRAM
165-bump BGA
250
I
8M x 9
GS8662T09E-200I
SigmaDDR-II B2 SRAM
165-bump BGA
200
I
8M x 9
GS8662T09E-167I
SigmaDDR-II B2 SRAM
165-bump BGA
167
I
4M x 18
GS8662T18E-250
SigmaDDR-II B2 SRAM
165-bump BGA
250
C
4M x 18
GS8662T18E-200
SigmaDDR-II B2 SRAM
165-bump BGA
200
C
4M x 18
GS8662T18E-167
SigmaDDR-II B2 SRAM
165-bump BGA
167
C
4M x 18
GS8662T18E-250I
SigmaDDR-II B2 SRAM
165-bump BGA
250
I
4M x 18
GS8662T18E-200I
SigmaDDR-II B2 SRAM
165-bump BGA
200
I
4M x 18
GS8662T18E-167I
SigmaDDR-II B2 SRAM
165-bump BGA
167
I
2M x 36
GS8662T36E-250
SigmaDDR-II B2 SRAM
165-bump BGA
250
C
2M x 36
GS8662T36E-200
SigmaDDR-II B2 SRAM
165-bump BGA
200
C
2M x 36
GS8662T36E-167
SigmaDDR-II B2 SRAM
165-bump BGA
167
C
2M x 36
GS8662T36E-250I
SigmaDDR-II B2 SRAM
165-bump BGA
250
I
2M x 36
GS8662T36E-200I
SigmaDDR-II B2 SRAM
165-bump BGA
200
I
2M x 36
GS8662T36E-167I
SigmaDDR-II B2 SRAM
165-bump BGA
167
I
8M x 8
GS8662T08GE-250
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
250
C
8M x 8
GS8662T08GE-200
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
200
C
8M x 8
GS8662T08GE-167
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
167
C
8M x 8
GS8662T08GE-250I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
250
I
GS8662T08GE-200I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
200
I
GS8662T08GE-167I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
167
I
GS8662T09GE-250
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
250
C
Part Number1
Type
Package
8M x 8
GS8662T08E-250
SigmaDDR-II B2 SRAM
165-bump BGA
8M x 8
GS8662T08E-200
SigmaDDR-II B2 SRAM
8M x 8
GS8662T08E-167
8M x 8
8M x 8
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No
t
8M x 8
8M x 9
ct
Org
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8662T36E-200T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.10 8/2012
32/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Ordering Information—GSI SigmaDDR-II SRAM
Part Number1
Type
Package
Speed
(MHz)
TA2
8M x 9
GS8662T09GE-200
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
200
C
8M x 9
GS8662T09GE-167
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
167
C
8M x 9
GS8662T09GE-250I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
250
I
8M x 9
GS8662T09GE-200I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
200
I
8M x 9
GS8662T09GE-167I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
167
I
4M x 18
GS8662T18GE-250
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
250
C
4M x 18
GS8662T18GE-200
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
200
C
4M x 18
GS8662T18GE-167
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
167
C
4M x 18
GS8662T18GE-250I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
250
I
4M x 18
GS8662T18GE-200I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
200
I
4M x 18
GS8662T18GE-167I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
167
I
2M x 36
GS8662T36GE-250
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
250
C
2M x 36
GS8662T36GE-200
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
200
C
2M x 36
GS8662T36GE-167
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
167
C
2M x 36
GS8662T36GE-250I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
250
I
2M x 36
GS8662T36GE-200I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
200
I
2M x 36
GS8662T36GE-167I
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
167
I
De
sig
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Di
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inu
ed
Pr
od
u
ct
Org
No
t
Re
co
m
me
nd
ed
for
Ne
w
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8662T36E-200T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.10 8/2012
33/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology
GS8662T08/09/18/36E-250/200/167
Revision History
Format
GS8662Txx_r1; GS8662Txx_r1_01
Content
GS8662Txx_r1_01; GS8662Txx_r1_02
Content
GS8662Txx_r1_02; GS8662Txx_r1_03
Content
GS8662Txx_r1_03; GS8662Txx_r1_04
Content
GS8662Txx_r1_04, GS8662Txx_r1_05
Content
GS8662Txx_r1_05; GS8662Txx_r1_06
Content
Content
GS8662Txx_r1_07; GS8662Txx_r1_08
Content
GS8662Txx_r1_08; GS8662Txx_r1_09a
• Added RoHS-compliant information
• Updated MAX tKHKH
• Updated tKHKH, tKHCH in AC Char table
• Added tKHKH and CQ Phase Distortion to AC Char table
• Added CZ data
• Updated I/O supply voltage data
• Updated power-up sequence information
• Changed separate Read and Write pins to one R/W-bar pin.
• Updated Status to PQ
• Added VREF note to Pin Description table
• Updated FLXDrive-II Output Driver Impedance Control section
• Removed Preliminary banner due to production status
• Removed 267 MHz speed bin (T)
De
sig
GS8662Txx_r1_06; GS8662Txx_r1_07
• Creation of new datasheet
ct
GS8662Txx_r1
Revisions
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Types of Changes
Format or Content
Ne
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File Name
• (Rev1.09a: Editorial updates)
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Content
• Revised AC Electrical Characteristics table
Rev: 1.10 8/2012
34/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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