8 6 7 1 2 3 4 5 REVISIONS REV PARALLEL I/O DESCRIPTION DATE APPROVED CONNECTIONS +VADJ OPTIONAL +VADJ C DIFFIO_TX0P DIFFIO_RX1N DIFFIO_TX1N DIFFIO_RX1P DIFFIO_TX1P DIFFIO_RX2N DIFFIO_TX2N DIFFIO_RX2P DIFFIO_TX2P DIFFIO_RX3N DIFFIO_TX3N DIFFIO_RX3P DIFFIO_TX3P DIFFIO_RX4N DIFFIO_TX4N DIFFIO_RX4P DIFFIO_TX4P DIFFIO_RX5N DIFFIO_TX5N DIFFIO_RX5P DIFFIO_TX5P DIFFIO_RX6N DIFFIO_TX6N DIFFIO_RX6P DIFFIO_TX6P DIFFIO_TX7N DIFFIO_RX7N DIFFIO_RX7P DIFFIO_TX7P DIFFIO_RX8N DIFFIO_TX8N DIFFIO_RX8P DIFFIO_TX8P DIFFIO_TX9N DIFFIO_RX9N DIFFIO_TX9P DIFFIO_RX9P DIFFIO_RX10N DIFFIO_TX10N DIFFIO_RX10P DIFFIO_TX10P DIFFIO_RX11N DIFFIO_TX11N DIFFIO_RX11P DIFFIO_TX11P DIFFIO_RX12N DIFFIO_TX12N DIFFIO_RX12P DIFFIO_TX12P 3.74K R101 AA22 AA23 AC22 AC23 AB23 AB24 AE25 AE26 AB21 AB22 AC24 AC25 Y21 W21 V22 V23 AA25 AA26 U23 U24 Y24 Y25 V20 U20 U19 T19 1 2 D34A D33A D6N3 N1 N2 N4 D6+ 3 4 D5- DIFFIO_TX14N DIFFIO_RX14P DIFFIO_TX14P DNI D30A EVQ-PAC05R D5+ R132 DGND D13A 0 D32A D4- R102 3.74K D15A D35A D4+ DNI D2- J102 D16A D2+ DNI D14A 1 2 D31A N1 N3 N2 N4 D3- 3 4 D3+ D1A D1- D2A EVQ-PAC05R D27A D1+ R6 DGND D10A 0 D12A D0- D29A D0+ D9A D26A DEBUG5 D11A DEBUG6 D28A DEBUG7 I/O_1 D0A I/O_2 D17A I/O_3 I/O_4 I/O_5 Y23 W23 VREFB1N0 VREFB1N1 DGND I/O_6 BANK 1 I/O_7 I/O_8 EP2SGX30CF780C5N DGND PINOUT IS FLEXIBLE WITHIN BANKS 1 AND 2 MUST OBSERVE POLARITY FOR LVDS +/LVDS +/PAIRS MUST BE ON RX PINS DIFFIO_RX15N DIFFIO_TX15N DIFFIO_RX15P DIFFIO_TX15P DIFFIO_RX16N DIFFIO_TX16N DIFFIO_RX16P DIFFIO_TX16P DIFFIO_RX17N DIFFIO_TX17N DIFFIO_RX17P DIFFIO_TX17P DIFFIO_RX18N DIFFIO_TX18N DIFFIO_RX18P DIFFIO_TX18P DIFFIO_RX19N DIFFIO_TX19N DIFFIO_RX19P DIFFIO_TX19P DIFFIO_RX20N DIFFIO_TX20N DIFFIO_RX20P DIFFIO_TX20P DIFFIO_RX21N DIFFIO_TX21N DIFFIO_RX21P DIFFIO_TX21P DIFFIO_RX22N DIFFIO_TX22N DIFFIO_RX22P DIFFIO_TX22P DIFFIO_RX23N DIFFIO_TX23N DIFFIO_RX23P DIFFIO_TX23P DIFFIO_RX24N DIFFIO_TX24N DIFFIO_RX24P DIFFIO_TX24P DIFFIO_RX25N DIFFIO_TX25N DIFFIO_RX25P DIFFIO_TX25P DIFFIO_RX26N DIFFIO_TX26N DIFFIO_RX26P DIFFIO_TX26P DIFFIO_RX27N DIFFIO_TX27N DIFFIO_RX27P DIFFIO_TX27P DIFFIO_RX28N DIFFIO_TX28N DIFFIO_RX28P DIFFIO_TX28P LVDS TERMINATIONS 100 R104 D24A D3A DCLK2+ D8A D25A 100 R105 D0+ D6A 100 R106 D7A DEBUG1 D1+ DEBUG2 DEBUG3 100 R108 D3+ D20A D23A CSB_1 +VADJ D5A D21A D4A DNI D22A S4 1B 2B 3B 4B 5B CSB_4 D11+ DNI D14+ D4DNI D5- D15+ DNI D6- D16+ DNI D7- D17+ 100 1A 2A 3A 4A 5A D DNI D8- R113 100 R114 DNI D9- 100 R115 DNI D10- 100 R116 DNI D11- 100 R117 DNI D12- 100 R118 DNI D13- 100 R119 DNI 100 R120 DNI 100 R121 DNI 100 R122 DNI D14- D15- D16- C D17- 100 PLACE NEAR TYCO CONNECTORS UNLESS EASY TO PLACE NEAR FPGA PINS 219-5MST CSB_3 D10+ D13+ 100 R112 D7+ DNI D0- DNI D3- 100 R111 D6+ D9+ D12+ 100 R110 D5+ DNI DCLK2- DNI D2- 100 R109 D4+ CSB_2 D8+ DNI D1- 100 R107 D2+ DEBUG4 DNI DCLK1- R103 DCLK1+ D19A 3.74K DNI 0 DIFFIO_TX0N DIFFIO_RX0P D18A DNI DIFFIO_RX14N R20 R21 N20 M20 P24 P25 M24 M25 K25 K26 H25 H26 J24 J25 M21 M22 G25 G26 L23 K23 K21 K22 J23 K24 E25 E26 G23 G24 F23 F24 H22 H23 3.74K R51 DIFFIO_TX13P DNI DIFFIO_RX13P 3.74K R50 R998 DIFFIO_RX0N S9 DNI U101 VCCIO2 DIFFIO_TX13N L22 3.74K R48 D15- DNI T26 T27 T28 R28 P26 P27 N25 N26 P28 N28 M28 L28 M26 M27 K27 K28 L25 L26 J28 H28 J26 J27 G27 G28 F28 E28 F26 F27 D27 D28 C27 C28 T21 M23 DNI AF27 AF28 AE27 D15+ AE28 AB25 D11D11+ AB26 AC26 D14D14+ AC27 W24 W25 AD25 D16D16+ AD26 AD28 D13D13+ AC28 AB27 D12D12+ AB28 V25 V26 Y26 D10Y27 D10+ W26 D8W27 D8+ D9- AA28 Y28 D9+ W28 D7D7+ V28 D17+ 0 U101 Y22 VCCIO1 D17- R999 V21 R46 N21 DIFFIO_RX13N J22 U22 3.74K R47 +VADJ D DGND VREFB2N0 VREFB2N1 BANK 2 EP2SGX30CF780C5N PAIRS B B +VADJ A1 Y1 6 3 A2 Y2 4 DNI 0 +VADJ DNI EXTERNAL DNI J107 R26 R137 1 2 3 4 5 JOHNSON142-0701-201 DNI EXTCLK4 DNI DGND DGND DGND SINEWAVE DNI DNI 0 DGND JOHNSON142-0701-201 R30 EXTCLK2 0 0 .1UF 1.00K A R5 EXTCLK1 NC7WZ04P6X R130 DNI 2 3 4 5 R128 DGND DNI DGND DNI 1 J7 1.00K R16 C152 EXTERNAL DNI 2 DNI DGND DNI GND DNI EXTCLK3 INPUTS SQUAREWAVE INPUT CLK0P/DIFFIO_RX_C0P +3.3VD VCC_PLL5_OUT R139 AA8 CLK2N/DIFFIO_RX_C1N CLK2P/DIFFIO_RX_C1P PLL_ENA 1K G14 F14 AD14 AE14 CLK1N CLK1P CLK3N CLK3P PLL6_OUT0P PLL6_OUT1N PLL6_OUT1P CLK5N U101 A14 A15 D15 C15 AH14 AH15 AF14 AG14 CLK6N DGND CLK6P CLK7N CLK7P CLK12N CLK12P CLK13N CLK13P A CLK14N CLK14P CLK15N CLK15P SCHEMATIC A N A L OG DE V CES DRAWING IT IS IN PART, IS THE 3 PROPERTY NOT TO BE REPRODUCED OR USED IN OF ANALOG OR COPIED, FURNISHING PURPOSE DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL <DRAWING_TITLE_HEADER> <PRODUCT_1> TO THE TO OTHERS, DESIGN DRAWING VIEW <DESIGN_VIEW> SIZE PTD ENGINEER SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. BY PATENTS REV NO. - - INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 4 PLL6_OUT0N PLL6_FBP/OUT2P GNDA_PLL1_1 THE 5 PLL5_OUT1P PLL6_FBN/OUT2N CLK5P PLL5_OUT0P PLL5_OUT1N CLK4P OF ANALOG 6 EP2SGX30CF780C5N PLL5_FBP/OUT2P OR FOR ANY OTHER 7 VCCA_PLL1 PLL5_OUT0N CLK4N THIS 8 VCC_PLL6_OUT PLL5_FBN/OUT2N EP2SGX30CF780C5N OR GENERAL I/O AA14 J14 CLK0N/DIFFIO_RX_C0N P22 P23 R22 R23 J16 K15 W13 W14 1 1.00K U102 VCC DGND JOHNSON142-0701-201 1.00K R29 DNI JOHNSON142-0701-201 R32 1.00K R14 DGND R133 1 2 3 4 5 +VADJ 5 DCLK2+ 0 0 .1UF 2 3 4 5 J106 DNI R25 R26 U27 DCLKA1 U28 DCLKA0 T24 DCLK1T25 DCLK1+ U25 DCLKA3 U26 DCLKA2 AG17 EXTCLK4 AH17 AB15 AC15 AG16 EXTCLK2 AH16 AE15 CLK_100MHZ AF15 B16 EXTCLK1 EXTCLK3 A16 G15 RCLK F15 B17 A17 D16 C16 DCLK2- DNI 1.00K R123 1 DNI +1.2VPLL U101 DNI R44 R13 C151 EXTERNAL J5 EXTERNAL 1.00K DNI 1.00K DNI +VADJ N23 T23 J15 Y14 N22 T22 K16 V14 +VADJ +VADJ <PTD_ENGINEER> 2 DD SCALE - SHEET 1 1 OF 7 8 6 7 1 2 3 4 5 REVISIONS REV SRAM CONNECTIONS KA DNI DLLA* AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 C AD20 AD21 +1.8VD DGND R63 499 LDA* A8 R2WA* A4 DNI C59 .1UF DNI R65 499 C6 A2 A3 A9 A10 B4 B8 C5 C7 N5 N6 N7 P4 P5 P7 P8 R3 R4 R5 R7 R8 R9 B7 A5 H2 H10 H11 DGND R27 DNI DNI 249 DGND R11 R10 R2 C R207 3.74K C_N K_N CQ_N K DOFF_N SA0 CQ A1 A11 CQA* KB* KB DLLB* CQA AD0 DQ0 SA_1 DQ1 SA_2 DQ2 SA_3 DQ3 SA_4 DQ4 SA_5 DQ5 SA_6 DQ6 SA_7 DQ7 SA_8 DQ8 SA_9 DQ9 SA_10 DQ10 SA_11 DQ11 SA_12 DQ12 SA_13 DQ13 SA_14 DQ14 SA_15 DQ15 SA_16 DQ16 SA_17 DQ17 P11 M10 L11 K11 J10 F11 E11 C10 B11 B2 D3 E3 F2 G3 K3 L2 N3 P3 0 AD1 RA<17..0> AD2 1 AD3 2 AD4 +1.8VD 3 4 AD5 5 AD6 6 AD7 7 VDD 8 U201 AD8 VDDQ AD9 AD10 GS8662T18GE-250 9 AD11 10 VSS 11 AD12 12 AD13 13 AD14 14 AD15 DGND 15 AD16 16 AD17 17 AD18 AD19 SA_18 AD20 SA_19 AD21 SA_20 SA_21 +1.8VD BW0_N BW1_N DGND R208 499 LD_N A8 R2WB* A4 H2 H10 H11 VREF R209 499 C202 .1UF ZQ TDI TDO R210 249 DGND R1 DGND TMS C6 A2 A3 A9 A10 B4 B8 C5 C7 N5 N6 N7 P4 P5 P7 P8 R3 R4 R5 R7 R8 R9 B7 A5 LDB* R/W_N VREF U202 P6 R6 A6 B6 H1 R11 R10 R2 D C C_N K_N K CQ_N CQ DOFF_N SA0 DQ0 SA_1 DQ1 SA_2 DQ2 SA_3 DQ3 SA_4 DQ4 SA_5 DQ5 SA_6 DQ6 SA_7 DQ7 SA_8 DQ8 SA_9 SA_10 DQ9 DQ10 SA_11 DQ11 SA_12 DQ12 SA_13 DQ13 SA_14 DQ14 SA_15 DQ15 SA_16 DQ16 SA_17 DQ17 A1 A11 P11 M10 L11 K11 J10 F11 E11 C10 B11 B2 D3 E3 F2 G3 K3 L2 N3 P3 CQB* CQB 0 RB<17..0> 1 2 +1.8VD 3 4 5 6 7 E4 E8 F4 F8 G4 G8 H3 H4 H8 H9 J4 J8 K4 K8 L4 L8 KA* P6 R6 A6 B6 H1 +1.8VD U201 K7 K5 J7 J5 H7 H5 G7 G5 F7 F5 R28 3.74K DNI E4 E8 F4 F8 G4 G8 H3 H4 H8 H9 J4 J8 K4 K8 L4 L8 DNI K7 K5 J7 J5 H7 H5 G7 G5 F7 F5 +1.8VD C4 C8 D4 D5 D6 D7 D8 E5 E6 E7 F6 G6 H6 J6 K6 L5 L6 L7 M5 M4 N8 N4 M8 M7 M6 D APPROVED +1.8VD R206 3.74K R25 3.74K DATE VDD 8 U202 VDDQ GS8662T18GE-250 9 10 VSS 11 C4 C8 D4 D5 D6 D7 D8 E5 E6 E7 F6 G6 H6 J6 K6 L5 L6 L7 M5 M4 N8 N4 M8 M7 M6 +1.8VD DESCRIPTION 12 13 14 DGND 15 16 17 SA_18 SA_19 SA_20 C +1.8VD SA_21 BW0_N BW1_N LD_N C217 .1UF C201 .1UF R/W_N DNI C203 .1UF DNI DNI C204 .1UF DNI C205 .1UF DNI C206 .1UF C207 .1UF DNI DNI VREF C208 .1UF DNI DGND VREF ZQ TDI TDO R1 TMS TCK TCK C209 .1UF C210 .1UF C211 .1UF DNI DNI DNI GS8662T18GE-250 C212 .1UF DNI C213 .1UF C214 .1UF DNI C215 .1UF C216 .1UF DNI DNI DNI DGND GS8662T18GE-250 B AD13 AD11 AD20 AD21 AD14 RA<12> AD15 RA<0> RA<11> AD7 RA<2> RA<1> RA<4> RA<5> RA<7> RA<3> RA<8> RA<6> AD10 AD19 +1.8VD AD1 RA<16> DNI R18 51 A C26 R17 51 DNI .1UF DNI C25 .1UF R19 499 DNI DNI DGND +1.8VD C27 .1UF DNI R20 499 Y9 VCCIO7 DQ1B0 IO DQ1B1 IO DQ1B2 IO DQ1B3 IO DQ3B0 IO DQ3B1 IO DQ3B2 IO DQ3B3 IO DQ5B0 IO DQ5B1 IO DQ5B2 IO DQ5B3 IO DQ7B0 IO DQ7B1 IO DQ7B2 IO DQ7B3 +1.8VD BANKS IO DQ9B0 IO DQ9B1 IO AA11 AB9 AB10 AB11 AB12 AB13 AC9 AC11 AC12 V11 V13 W9 W10 W11 W12 Y10 Y11 Y13 RA<10> AH18 CQA* AF18 AF19 CQB CQB* AH20 AF21 KA AH21 KA* AH22 KB AG22 KB* AH23 RB<7> AF22 RB<10> AF24 LDA* AH24 RB<8> AH26 DLLA* AH25 LDB* AG26 AF26 AH19 AG20 AG23 +1.8VD AG25 AG19 AF20 R21 AF23 499 AF25 DNI AD17 AD19 CQA AD17 AD9 AD8 AD6 AD5 AD0 RA<14> AD4 AD2 RA<15> RA<17> RA<13> AD16 AD12 AD3 DQ9B2 DQ9B3 DQS1B DQS3B DQS5B DQS7B DQS9B DQSB1B DQSB3B DQSB5B DQSB7B C28 .1UF DQSB9B DNI RDN7 RUP7 R22 499 DNI Y18 AE8 AF7 AE7 AH7 AD10 AH9 AH8 AE10 AH10 AG10 AF10 AD11 AH11 AG11 AH12 AH13 AD13 AC13 AC14 AG13 AF8 AE9 AE11 AE12 AF13 AG8 AF9 AF11 AF12 AE13 AC8 AB8 AB14 AC10 WITHIN Y19 AD18 PINOUT U101 AA16 RA<9> FLEXIBLE AA13 AA10 +1.8VD U101 VCCIO8 DQ11B0 IO DQ11B1 IO DQ11B2 IO DQ11B3 IO DQ13B0 IO DQ13B1 IO DQ13B2 IO DQ13B3 IO DQ15B0 IO DQ15B1 IO DQ15B2 IO DQ15B3 IO DQ17B0 IO DQ17B1 IO DQ17B2 IO DQ17B3 IO DQS11B IO DQS13B IO DQS15B IO DQS17B IO AA19 AE23 W16 AB18 AB19 AB20 AC19 AC20 AD20 AE19 AE20 AA17 AB16 AB17 AC17 AC18 AE18 W15 Y15 Y17 B RB<0> RB<9> RB<2> RB<3> RB<4> RB<5> DLLB* RB<11> RB<6> RB<13> RB<12> R2WA* RB<17> RB<16> RB<1> RB<15> RB<14> R2WB* DQSB11B DQSB13B DQSB15B DQSB17B VREFB8N1 VREFB8N0 A EP2SGX30CF780C5N MUST OBSERVE POLARITY ON KA/KB/CQA/CQB DGND A N A L OG DE V CES VREFB7N1 EP2SGX30CF780C5N DNI FLEXIBLE PINOUT WITHIN THIS DRAWING IT IS IN PART, IS THE THE OR USED IN 5 4 3 OF ANALOG OR COPIED, FURNISHING PURPOSE DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN DRAWING VIEW <DESIGN_VIEW> SIZE PTD ENGINEER SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. BY PATENTS REV NO. - - INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 6 PROPERTY NOT TO BE REPRODUCED OF ANALOG 7 <DRAWING_TITLE_HEADER> <PRODUCT_1> BANK EXCEPT FOR VREF/RDN/VUP DGND OR FOR ANY OTHER 8 SCHEMATIC VREFB7N0 <PTD_ENGINEER> 2 DD SCALE - SHEET 2 1 OF 7 8 6 7 1 2 3 4 5 REVISIONS REV FPGA POWER AND DECOUPLING COPY DUT FOOTPRINT FROM ALTERA DESCRIPTION DATE APPROVED EVAL BOARD D U101 AH6 AH5 AH4 AH3 AH27 AH2 AG9 AG7 AG6 AG5 AG4 AG3 AG28 AG27 AG24 AG21 AG2 AG18 AG15 AG12 AG1 AF6 AF3 AF2 AF1 AE6 AE5 AE4 AE3 AE2 AE1 AD9 AD7 AD6 AD3 AD27 AD24 AD21 AD18 AD15 AD12 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AB6 AB3 AA9 AA7 AA6 AA5 AA4 AA3 AA27 AA24 AA21 D EP2SGX30CF780C5N +1.2VD U101 FPGA BYPASS CAP B A DQ1T0 U101 J9 VCCIO4 IO DQ1T1 IO DQ1T2 IO DQ1T3 IO DQ3T0 IO DQ3T1 IO DQ3T2 IO DQ3T3 IO DQ5T0 IO DQ5T1 IO DQ5T2 IO DQ5T3 IO DQ7T0 IO DQ7T1 IO DQ7T2 IO DQ7T3 IO DQ9T0 IO DQ9T1 IO DQ9T2 IO DQ9T3 IO DQS1T C122 .1UF E10 K10 K11 F11 G12 G13 H13 K12 K13 K14 L12 L13 L14 G10 G11 G9 H10 H11 J10 J11 C123 .1UF DGND +VADJ P C126 10UF N C76 .1UF C115 .1UF C124 .1UF C125 .1UF DGND +1.2VD C B GND C77 1UF C78 .1UF C80 .1UF C82 .1UF C84 .1UF C85 .1UF DGND DGND +3.3VD DQS3T DQS5T P DQS7T N DQS9T C61 10UF C62 1UF C63 .1UF C64 .1UF C65 .1UF C66 .1UF C67 .1UF C68 .1UF C69 .1UF C70 .1UF DQSB1T DQSB3T DQSB5T DGND A +1.2VD DQSB7T DQSB9T RDN4 P N RUP4 C86 10UF C74 1UF C87 .1UF C88 .1UF C89 .1UF C90 .1UF C91 .1UF C92 .1UF C117 .1UF C116 .1UF C114 .1UF C113 .1UF VREFB4N1 SCHEMATIC A N A L OG DE V CES DGND VREFB4N0 <DRAWING_TITLE_HEADER> <PRODUCT_1> EP2SGX30CF780C5N THIS DRAWING IT IS IN PART, IS THE OF ANALOG THE OR USED IN 6 5 4 3 OF ANALOG OR COPIED, FURNISHING PURPOSE DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN DRAWING VIEW <DESIGN_VIEW> SIZE PTD ENGINEER SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. BY PATENTS REV NO. - - INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 7 PROPERTY NOT TO BE REPRODUCED OR FOR ANY OTHER 8 AA20 AA2 AA18 AA15 AA12 AA1 Y6 Y5 Y3 Y20 W8 W7 W6 W5 W4 W3 W22 W20 W2 W1 V8 V6 V3 V27 V24 V18 V15 V12 V10 U9 U8 U7 U5 U4 U3 U21 U2 U17 U15 U13 U11 U10 U1 T3 T18 T16 T14 T12 R5 R4 R3 R27 R24 R2 R19 R17 R15 R13 R11 H4 H5 H6 H7 H9 J3 J5 J6 J7 K1 K2 K3 K4 K5 K6 L11 L15 L18 L21 L24 L27 L3 M1 M12 M14 M16 M18 M19 M2 M3 M4 M5 N10 N11 N13 N15 N17 N19 N24 N27 N3 N7 N8 N9 P1 P10 P12 P14 P16 P18 P19 P2 P21 P3 P4 P5 P6 P8 R1 D9 A7 D8 A8 B10 A9 C9 E11 C12 D11 A10 D12 A11 F13 A12 E13 E14 A13 B13 D14 C8 D10 C11 D13 B14 B8 C10 B11 C13 C14 D7 C7 F12 F10 J12 H14 +1.8VD EP2SGX30CF780C5N GND +3.3VD U101 GND GND K7 K8 AD8 AD22 AD23 AE16 AF16 C17 E22 F9 F25 V2 V1 T2 T1 AB2 AB1 AD2 AD1 V5 V4 T5 T4 AD5 AD4 AF5 AF4 Y2 Y1 AB5 AB4 Y4 NC VCCINT EP2SGX30CF780C5N VCCPD C T20 P20 J17 J13 Y12 Y16 +3.3VD M11 M13 M15 M17 N12 N14 N16 N18 P11 P13 P15 P17 R12 R14 R16 R18 T11 T13 T15 T17 U12 U14 U16 U18 A2 A27 A3 A4 A5 A6 B1 B12 B15 B18 B2 B21 B24 B27 B28 B3 B4 B5 B6 B7 B9 C1 C2 C3 C6 D1 D2 D3 D4 D5 D6 E12 E15 E18 E21 E24 E27 E3 E6 E7 E9 F1 F2 F3 F4 F5 F6 G3 G6 H1 H12 H15 H16 H18 H2 H21 H24 H27 H3 <PTD_ENGINEER> 2 DD SCALE - SHEET 3 1 OF 7 8 6 7 1 2 3 4 5 REVISIONS REV DESCRIPTION DATE APPROVED D D GXB CONNECTIONS R58 +3.3VD 0 GTPCLK1N DO NOT INSTALL RESISTORS DNI 220OHM 2 L18 DGND VCCA DNI VCCH_B13 VCCL_B13 C C110 .22UF VCCP VCCR L8 M8 R8 T8 49.9 DNI DNI L10 M10 R10 T10 R68 49.9 .1UF +1.2VGX C23 .22UF L7 M7 R7 T7 R3 N6 U6 GXBCLK1P FIN1017M 1 +3.3VGX C97 DGND 2 DNI DNI L9 M9 R9 T9 DGND JOHNSON142-0701-201 7 49.9 K9 L6 M6 P7 P9 R6 T6 V7 V9 DNI 4 R66 R67 GND R60 DGND R57 DNI 1.00K C DOUT+ .1UF DNI DNI 100 DNI 2 3 4 5 .1UF 8 220OHM DOUTDIN +1.2VGXB +3.3VD L14 J9 DNI VCC 2 +3.3VGXB R2 49.9 1 DNI C497 1 GXBCLK1N 0 R55 GXBCLK 1.00K C96 U1 1 U101 DGND VCCT_B13 DNI SD1- GTPCLK1P SD1+ SD2SD2+ GTPCLK2N SD3- R69 DNI Y402 1 +3.3VD C403 VCC OE GXBCLK2N 6 NC OUT_N 5 GND OUT 4 R70 GXBCLK2P DNI R9 C407 SD1+ C422 .1UF C421 .1UF GXB_TX2N GXB_TX2P GXB_RX2P GXB_RX3N GXB_TX3N EP2SGX30CF780C5N GXB_TX3P GXB_RX3P REFCLK0_B13N REFCLK0_B13P REFCLK1_B13N REFCLK1_B13P RREFB13 B R10 +1.8VD 49.9 R73 DNI SD1N C420 .1UF GXB_TX1P GXB_RX2N RESISTORS .1UF C419 .1UF GXB_TX1N GXB_RX1P DNI C408 C418 .1UF GXB_RX1N E5 E4 C5 C4 L5 L4 N5 N4 DGND DGND DNI SD1P C417 .1UF GXB_TX0P 49.9 GTPCLK2P C416 .1UF GXB_TX0N GXB_RX0P 2K 49.9 DO NOT INSTALL DNI +1.2VGX C415 .1UF J4 GXB_RX0N 0 R64 .1UF R405 GXBCLK1P GXBCLK2N DNI DNI GXBCLK2P J2 J1 G5 G4 GXBCLK1N DNI R402 156.250MHZ B R4 DNI C404 DGND 49.9 DNI 100 3 SD4+ 49.9 .1UF 2 SD4- 0 R61 SD3+ G2 G1 E2 E1 L2 L1 N2 N1 SD1- R11 49.9 .1UF 49.9 DNI DNI R74 49.9 C409 SD2P DGND SD2+ 49.9 .1UF SD2- .1UF C411 SD3+ SD3- A C434 .1UF C435 .1UF C436 .1UF C437 .1UF C438 .1UF 49.9 DNI DNI R77 DNI R31 49.9 .1UF C433 .1UF R76 49.9 C412 SD3N R75 DNI DNI R24 49.9 .1UF +3.3VGX R23 49.9 SD3P DNI 49.9 C410 SD2N DNI R12 DNI R78 49.9 C439 .1UF C413 SD4+ SD4P .1UF DGND C414 SD4- SD4N DNI R33 49.9 DNI R40 DNI 49.9 49.9 .1UF A R79 A N A L OG DE V CES 49.9 DNI DO NOT INSTALL THIS DRAWING IT IS IN PART, IS THE THE OR USED IN 5 4 3 OF ANALOG OR COPIED, FURNISHING PURPOSE DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN DRAWING VIEW <DESIGN_VIEW> SIZE PTD ENGINEER SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. BY PATENTS REV NO. - - INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 6 PROPERTY NOT TO BE REPRODUCED OF ANALOG 7 <DRAWING_TITLE_HEADER> <PRODUCT_1> DGND RESISTORS OR FOR ANY OTHER 8 SCHEMATIC DNI R80 <PTD_ENGINEER> 2 DD SCALE - SHEET 4 1 OF 7 8 6 7 1 2 3 4 5 REVISIONS REV DESCRIPTION DATE APPROVED USB CONNECTIONS D D D10 R38 LED8 +3.3VD C A LNJ308G8TRA XTALOUT RDY3 RDY4 RDY5 1 U12 2 C36 C 24.000MHZ 12PF XTALIN DGND 12PF +3.3VD USB2 USB3 R501 R49 100K DGND 3.74K R71 3.74K DGND FF_USB* XTALIN C37 .1UF USB_1 USB_2 DGND GENERAL PURPOSE I/O USB_3 USB_4 USB_5 B R8 9 22 10 R8 22 11 R8 22 12 R8 22 13 R8 22 14 R8 22 15 R8 22 16 R8 22 8 7 6 5 4 0 3 1 2 2 3 1 4 5 6 7 DATA<15..0> NSTATUS CONF_DONE NCONFIG RXD0 TXD0 CY7C68013A-128AXC RXD1 TXD1 T0 CS_N T1 WR_N T2 INT4 CLKOUT INT5_N IFCLK OE_N RDY0/SLRD RD_N RDY1/SLWR PSEN_N RDY2 50 52 42 41 1 32 38 40 39 4-1734376-8 USB3 A C LNJ308G8TRA LNJ308G8TRA DGND (GREEN) RCLK LNJ308G8TRA 24 +3.3VD DGND RDY4 A0 RDY5 A1 D0 A2 D1 A3 D2 A4 D3 A5 D4 A6 D5 A7 D6 A8 D7 A9 DMINUS A10 DPLUS A11 EA A12 RESERVED A13 RESET_N A14 WAKEUP A15 XTALIN XTALOUT PA0/INT0_N BKPT PA1/INT1_N PA2/SLOE CTL0/FLAGA PA3/WU2 CTL1/FLAGB CTL2/FLAGC PA4/FIFOADR0 PA5/FIFOADR1 CTL3 PA6/PKTEND CTL4 PA7/FLAGD/SLCS_N CTL5 PB0/FD0 PD0/FD8 PB1/FD1 PD1/FD9 PB2/FD2 PD2/FD10 PB3/FD3 PD3/FD11 PB4/FD4 PD4/FD12 PB5/FD5 PD5/FD13 PB6/FD6 PD6/FD14 PD7/FD15 PB7/FD7 PC0/GPIFADR0 PE0/T0OUT PC1/GPIFADR1 PE1/T1OUT PC2/GPIFADR2 PE2/T2OUT PC3/GPIFADR3 PE3/RXD0OUT PC4/GPIFADR4 PE4/RXD1OUT PC5/GPIFADR5 PE5/INT6 PC6/GPIFADR6 PE6/T2EX PE7/GPIFADR8 AGND PC7/GPIFADR7 34 69 70 71 66 67 98 102 103 104 105 121 122 123 124 108 109 110 111 112 113 114 115 +3.3VD +3.3VD C34 .1UF DATA<3> DATA<5> 24LC00SN 1 2 3 4 NC1 VCC NC2 NC4 NC3 SCL VSS SDA 8 7 6 5 R72 3.74K DATA<6> R52 3.74K WEN* MR* SCL_USB DATA<8> SDA_USB DATA<10> REN_A* DGND DATA<14> DATA<9> RDY2 DATA<15> XTALOUT R37 DATA<13> MR* R36 100 R35 100 R56 100 R34 24 RDY4 WEN* DATA<2> REN_B* REN_A* DATA<12> CCLK RDY1 DATA<4> REN_B* DATA<7> 100 8 FF_USB* DATA<15..0> DATA<11> 9 10 A18 C18 C19 A20 A21 C21 A22 B22 A23 C22 A24 C24 A26 A25 C26 B26 A19 B20 B23 B25 B19 C20 C23 C25 E20 E19 11 DGND 12 13 D505 R518 IO DQ11T1 IO DQ11T2 IO DQ11T3 IO DQ13T0 IO DQ13T1 IO DQ13T2 IO DQ13T3 IO DQ15T0 IO DQ15T1 IO DQ15T2 IO DQ15T3 IO DQ17T0 IO DQ17T1 IO DQ17T2 IO DQ17T3 IO DQS11T IO DQS13T IO DQS15T IO D18 D19 D20 F20 G19 G20 H19 J20 K20 L19 F18 L20 F19 G17 G18 J18 K18 K19 L17 A R519 LED3 C LED1 LNJ308G8TRA LED2 A C LED4 LNJ308G8TRA LED7 LED6 A R521 LED1 LED8 C LNJ308G8TRA RDY3 100 (GREEN) D508 RDY0 C R520 LED2 LED5 100 (GREEN) D507 LED3 100 (GREEN) D506 U101 VCCIO3 DQ11T0 100 (GREEN) A +3.3VD 100 (GREEN) DATA<1> RDY5 CS_FPGA SCLK SDO SDI DQS17T DQSB11T DQSB13T DQSB15T DQSB17T VREFB3N1 VREFB3N0 B EP2SGX30CF780C5N 14 R7 15 8 7 R7 6 R7 5 R7 4 R7 3 R7 2 R7 1 R7 DGND SDI DATA<0> U5 DGND 13 20 27 49 58 65 80 93 116 125 3 GND 94 95 96 97 117 118 119 120 126 127 128 21 22 23 24 25 11 R517 A LED4 C 100 (GREEN) D504 C LNJ308G8TRA RDY3 R516 A LED5 R522 100 (GREEN) LED6 C 499 A D503 USB D1 R45 1 4 5 2 3 6 USB2 J19 RDY2 J6 SCL H20 RDY1 C35 LNJ308G8TRA SDA H17 RDY0 37 36 51 53 29 30 31 28 106 4 5 6 7 8 9 59 60 61 62 63 86 87 88 19 18 35 33 99 101 12 82 83 84 85 89 90 91 92 44 45 46 47 54 55 56 57 72 73 74 75 76 77 78 79 C & SDO DIRECTIONS 9 22 10 22 11 22 12 22 13 22 14 22 15 22 16 22 SCLK SDI CSB_1 CSB_2 FLEXIBLE +3.3VD PINOUT WITHIN BANK CSB_3 CSB_4 CS_FPGA 10K SCL_USB R39 LED7 U3 VCC R509 SDA_USB 2 26 43 48 64 68 81 100 107 10 17 D2 AVCC 100 (GREEN) SDO ARE WRT THE DUT. +3.3VD U18 4 1 +3.3VD DNI VDD E/D 2 2 10 17 C39 .1UF C40 .1UF 126 C41 .1UF 43 64 81 C42 .1UF C43 .1UF C44 .1UF DNI CWX823-100.0MHZ 100 C45 .1UF CLK_100MHZ 24 GND C38 .1UF A R15 3 OUT DGND REFCLK OSCILLATOR A FOR IDELAYCTRL DGND SCHEMATIC A N A L OG DE V CES THIS DRAWING IT IS IN PART, IS THE OF ANALOG THE OR USED IN 7 6 5 4 3 OF ANALOG OR COPIED, FURNISHING PURPOSE DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN DRAWING VIEW <DESIGN_VIEW> SIZE PTD ENGINEER SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. BY PATENTS REV NO. - - INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 8 PROPERTY NOT TO BE REPRODUCED OR FOR ANY OTHER <DRAWING_TITLE_HEADER> <PRODUCT_1> <PTD_ENGINEER> 2 DD SCALE - SHEET 5 1 OF 7 8 6 7 1 2 3 4 5 REVISIONS REV TYCO AND MISC D15+ DCLK1+ DGND SD2P SD1P GTPCLK1P J1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 GTPCLK2N SD4N SD3N SD2N SD1N GTPCLK1N D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DCLK1- 1469028-1 J1 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 J2 D0+ D2+ D4+ D6+ D8+ D10+ D12+ D14+ D16+ DGND 1469028-1 D15- 1469028-1 D6A D8A D10A D12A D14A DCLKA2 DGND PLUG HEADER SD3P J1 D13- 1469028-1 PLUG HEADER SD4P 1469028-1 PLUG HEADER GTPCLK2P 1469028-1 D11- D4A D17+ 1469028-1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 1469028-1 D0D2D4D6D8D10D12D14D16D17- D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 J2 DNI DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 1469028-1 D5A D7A D9A D11A D13A D15A DCLKA3 1469028-1 D 1469028-1 1469028-1 DNI DNI J3 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D16A D18A D20A D22A D24A D26A D28A D30A D32A D34A DGND 1469028-1 D3A DNI DGND 1469028-1 J2 DNI D1A J3 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 PLUG HEADER D13+ D9- D2A B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 DCLKA1 J3 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D17A D19A D21A D23A D25A D27A D29A D31A D33A D35A J3 DNI DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 1469028-1 DNI PLUG HEADER D11+ D7- D0A J3 DNI DNI PLUG HEADER I/O_1 D9+ D5- J3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 DCLKA0 PLUG HEADER I/O_3 D7+ D3- DNI PLUG HEADER I/O_2 I/O_5 D5+ BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 PLUG HEADER I/O_4 SCLK I/O_7 D3+ J2 DNI PLUG HEADER I/O_6 SDI D1- B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 PLUG HEADER I/O_8 SDO DCLK2- PLUG HEADER CSB_1 USB_1 J2 DNI PLUG HEADER CSB_2 D1+ A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 PLUG HEADER CSB_3 DCLK2+ PLUG HEADER CSB_4 APPROVED FPGA CONNECTIONS J2 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 PLUG HEADER D USB_2 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 DATE J1 J1 USB_4 PLUG HEADER USB_3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 PLUG HEADER J1 USB_5 DESCRIPTION DGND 1469028-1 1469028-1 1469028-1 C C DEBUG PINS J8 JTAG CONNECTOR AS CONNECTOR DNI TCK DEBUG2 TDO +3.3VD DEBUG3 TMS DEBUG4 DEBUG5 TDI DEBUG6 R601 +3.3VD R602 10K 10K CONF_DONE NCONFIG NCE R603 DATA_EEPROM NCS 10K ASDI TSW-105-08-G-D DGND DEBUG7 J606 DCLK 1 2 3 4 5 6 7 8 9 10 DGND 1 2 3 4 5 6 7 8 9 10 FPGA CONFIG U101 TSW-105-08-G-D GND ROW OF HEADER B R42 3.74K DGND R41 3.74K R43 3.74K R607 3.74K U4 DATA_EEPROM +3.3VD DATA<0> DCLK CCLK 1A 2A 3A 4A 5A 1B 2B 3B 4B 5B 219-5MST +3.3VD DGND 9 1 2 U601 VCC NCS 7 DCLK 16 ASDI 15 NCS DCLK DATA 8 DATA_EEPROM ASDI GND 10 CS INIT_DONE DATA0 DATA1 DEV_OE NCS NIO_PULLUP DATA2 NRS DATA3 NSTATUS DATA4 NWS DATA5 PGM0 DATA6 PGM1 DATA7 PGM2 DCLK RDYNBSY MSEL0 RUNLU MSEL1 ASDO MSEL2 CRC_ERROR MSEL3 NCEO NCE NCSO NCONFIG TDO AE17 AD16 G22 AF17 R611 Y7 +3.3VD AE21 0 R612 E23 NSTATUS AE22 10K G16 F16 E16 J21 AC16 L16 ASDI E17 AB7 D17 NCS F8 TDO R1 +3.3VD 100 +3.3VD EPCS64SI16N DGND 0 B U21 5 VCC 2 CONF_DONE A Y 4 GND 3 NC7SZ05M5X DGND PORSEL TCK TDI TEMPDIODEN TEMPDIODEP TMS TRST RECONFIG PUSHBUTTON VCCSEL R610 DGND CONFIG CONF_DONE C DO NOT INSTALL DEV_CLRN (GREEN) +3.3VD CLKUSR D6 DGND AC21 CONF_DONE D26 AE24 F17 DATA<1> K17 DATA<2> F21 DATA<3> D21 DATA<4> G21 DATA<5> D23 DATA<6> F22 DATA<7> D22 D25 J8 E8 H8 G8 NCE D24 V17 NCONFIG R608 Y8 TCK V16 0 V19 TDI G7 F7 TMS W19 R609 W17 W18 0 A SAMTECTSW11008GD J605 DEBUG1 LNJ308G8TRA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP2SGX30CF780C5N U9 NCONFIG 1 2 N1 N3 N2 N4 3 4 EVQ-PAC05R EEPROM DGND A A SCHEMATIC A N A L OG DE V CES THIS DRAWING IT IS IN PART, IS THE OF ANALOG THE OR USED IN 7 6 5 4 3 OF ANALOG OR COPIED, FURNISHING PURPOSE DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL TO THE TO OTHERS, DESIGN DRAWING VIEW <DESIGN_VIEW> SIZE PTD ENGINEER SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. BY PATENTS REV NO. - - INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 8 PROPERTY NOT TO BE REPRODUCED OR FOR ANY OTHER <DRAWING_TITLE_HEADER> <PRODUCT_1> <PTD_ENGINEER> 2 DD SCALE - SHEET 6 1 OF 7 8 6 7 1 2 3 4 5 REVISIONS REV DESCRIPTION DATE APPROVED POWER SUPPLIES INPUT 2.5A 220OHM 1 L3 2 C3 .1UF C46 10UF N E5 E10 E11 E12 DGND IN OUT GND NC C4 1UF E1 GRN D +3.3VGXB 4 1 R62 499 A BNX016-01 P 1 2 P ADP3339AKCZ-3.3-RL C32 10UF N NOTE: DGND DGND U702 3 DGND IN OUT GND NC C7 1UF E2 GRN 2 +3.3VD 4 1 DGND 1 PLACE GXB REGULATORS NEAR FPGA ALL REGULATORS SHOULD BE PLACED NEAR FPGA GXB REGULATORS HAVE PRIORITY USE PROPER THERMAL RELIEF ON LAYOUT C6 1UF ADP3339AKCZ-3.3-RL DGND DGND +1.8VD U16 LP38842S-1.2 2 5 1 BIAS OUT 4 +1.2VGXB C SD_N C718 GND .1UF C106 C716 10UF C E9 GRN 1 IN 22UF 3 4 6 5 U8 3 (GREEN) C50 1000PF 2 C C49 1000PF MBRS360T3G 1 LNJ308G8TRA MBRS360T3G 5.1V F701 2 D7 PJ-202A 1 2 3 S1 1 D 1 1 J4 1 MBRS360T3G D701 D702 D703 A C A C A C 2.5A 1 6V, 3 6 U7 NDT456P 1 L2 N R701 ZHCS2000TA R59 100K .1UF C720 10UF GND 3 6 DGND C1 470PF 2 5 1 A1 IN OUT GND NC 1 IN OUT BIAS E711 GRN 4 L703 1 2 +1.2VPLL B SD_N GND .1UF C723 C722 10UF B 3 U708 LP38842S-1.2 DGND 3 6 220OHM .1UF C21 68PF +1.2VD DGND 25.5K DGND OUT SD_N C725 2 80.6K 4 BIAS E710 GRN 4 22UF COMP GND DGND 3 1 IN C724 CS 6 1 2 5 1 C719 IN PGATE FB R53 DGND U17 5 3 4 DGND 1 2 5 6 C51 47UF 22UF G N ADP1864AUJZ-R7 R54 0.04 U707 LP38842S-1.2 P 1 C52 10UF DGND +1.8VD 3.6UH D5 P E3 GRN 2 C721 4 2 3 S D 1 DGND 2 C94 1 4 1UF +1.2VPLL C95 1UF ADP3339AKCZ-1.8-RL DGND DGND C731 .1UF TSW-103-08-G-D P1 DNI 3 IN OUT GND NC 1 C99 1UF A2 2 4 ADP3339AKCZ-2.5-RL DNI DGND C98 1UF 1 2 3 4 5 6 IN OUT GND NC C444 1 1UF DNI 3.3V 1 E6 GRN DNI SM A3 +VADJ C105 1UF A DGND 2 4 C93 1UF ADP3339AKCZ-3.3-RL DGND DGND DRAWING IT IS IN PART, IS THE OF ANALOG THE OR USED IN 5 4 3 OF ANALOG OR COPIED, FURNISHING PURPOSE DEVICES IN INC. WHOLE OR INFORMATION DETRIMENTAL <DRAWING_TITLE_HEADER> <PRODUCT_1> TO THE TO OTHERS, DESIGN DRAWING VIEW <DESIGN_VIEW> SIZE PTD ENGINEER SHOWN HEREON MAY BE PROTECTED BY OWNED ANALOG DEVICES. BY PATENTS REV NO. - - INTERESTS DEVICES. EQUIPMENT OWNED OR CONTROLLED 6 PROPERTY NOT TO BE REPRODUCED OR FOR ANY OTHER 7 SCHEMATIC A N A L OG DE V CES DNI THIS 8 C735 .1UF DGND 2 3 C734 .1UF 1.8V 1 DNI C733 .1UF 2.5V DGND A C732 .1UF <PTD_ENGINEER> 2 DD SCALE - SHEET 7 1 OF 7