Supertex inc. VN4012 N-Channel Enhancement-Mode Vertical DMOS FET Features ►► ►► ►► ►► ►► ►► ►► General Description Free from secondary breakdown Low power drive requirement Ease of paralleling Low CISS and fast switching speeds Excellent thermal stability Integral source-drain diode High input impedance and high gain This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Applications ►► ►► ►► ►► ►► ►► Motor controls Converters Amplifiers Switches Power supply circuits Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) Ordering Information Part Number VN4012L-G VN4012L-G P002 Package Option Product Summary Packing TO-92 1000/Bag TO-92 2000/Reel BVDSS/BVDGS RDS(ON) VGS(TH) IDSS (max) (max) (min) 12Ω 1.8V 150mA 400V VN4012L-G P003 VN4012L-G P005 Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Pin Configuration VN4012L-G P013 VN4012L-G P014 -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. DRAIN SOURCE Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature -55 C to +150 C O O Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Typical Thermal Resistance Package θja TO-92 132OC/W Doc.# DSFP-VN4012 B082013 GATE TO-92 Product Marking Si VN 4012L YYWW YY = Year Sealed WW = Week Sealed = “Green” Packaging Package may or may not include the following marks: Si or TO-92 Supertex inc. www.supertex.com VN4012 Thermal Characteristics Package (continuous)† (pulsed) ID Power Dissipation @TC = 25OC IDR† IDRM 160mA 650mA 1.0W 160mA 650mA TO-92 ID Notes: † ID (continuous) is limited by max rated Tj . Electrical Characteristics (T A = 25OC unless otherwise specified) Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage 400 - - V VGS = 0V, ID = 100µA VGS(th) Gate threshold voltage 0.6 - 1.8 V VGS = VDS, ID = 1.0mA - - 10 nA VGS = ±20V, VDS = 0V - - 1 IGSS Gate body leakage IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) Static drain-to-source on-state resistance - - 100 0.15 0.3 - - 9.5 12 - 17 30 125 350 - GFS Forward transductance CISS Input capacitance - - 110 COSS Common source output capacitance - - 30 CRSS Reverse transfer capacitance - - 10 Rise time - - 20 Turn-on delay time - - 20 Fall time - - 65 Turn-off delay time - - 65 Diode forward voltage drop - - 1.2 tr td(ON) tf td(OFF) VSD Conditions VGS = 0V, VDS = 0.8 Max Rating µA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C A VGS = 4.5V, VDS = 10V Ω VGS = 4.5V, ID = 100mA VGS = 4.5V, ID = 100mA, TA = 125OC mmho VDS = 15V, ID = 100mA pF VGS = 0V, VDS = 25V, f = 1.0MHz ns VDD = 25V, ID = 100mA, RGEN = 25Ω V VGS = 0V, ISD = 160mA Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 10V INPUT 0V Pulse Generator 10% t(ON) td(ON) VDD OUTPUT 0V Doc.# DSFP-VN4012 B082013 VDD 90% t(OFF) tr td(OFF) OUTPUT RGEN tf 10% 10% 90% RL INPUT D.U.T. 90% 2 Supertex inc. www.supertex.com VN4012 3-Lead TO-92 Package Outline (L) D A Seating Plane 1 2 3 L c b e1 e Side View Front View E1 E 1 3 2 Bottom View Symbol Dimensions (inches) A b c MIN .170 .014 NOM - - MAX .210 .022 † .014 † D E E1 e e1 L .175 .125 .080 .095 .045 .500 - - - - - - .205 .165 .105 .105 .055 .610* † .022 † JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-VN4012 B082013 3 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com