Supertex inc. HV2901 Low Charge Injection 32-Channel High Voltage Analog Switch with Bleed Resistors Features ►► 32-channel high voltage analog switch ►► Integrated bleed resistors on the outputs ►► 2:1 Multiplexer / Demultiplexer ►► 3.3V or 5.0V CMOS input logic level ►► 20MHz data shift clock frequency ►► HVCMOS technology for high performance ►► Very low quiescent power dissipation -10µA ►► Low parasitic capacitance ►► DC to 50MHz analog signal frequency ►► -60dB typical OFF-isolation at 5.0MHz ►► CMOS logic circuitry for low power ►► Excellent noise immunity ►► Cascadable serial data register with latches ►► Flexible operating supply voltages Applications ►► ►► ►► ►► ►► Medical ultrasound imaging NDT metal flaw detection Piezoelectric transducer drivers Inkjet printer heads Optical MEMS modules General Description The Supertex HV2901 is a low charge injection 32-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data are shifted into a 32-bit shift registers that can then be retained in a 32-bit latch. To reduce any possible clock feed through noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Block Diagram Latches D LE CLR Level Output Shifters Switches SW0 Y01 D LE CLR SW1 D LE CLR CLK DIN SW2 Y23 D LE CLR SW3 32-Bit Shift Register D LE CLR DOUT SW28 Y2829 D LE CLR SW29 D LE CLR SW30 Y3031 D LE CLR VDD GND Doc.# DSFP-HV2901 B011713 LE CLR SW31 VNN VPP RGND Supertex inc. www.supertex.com HV2901 Ordering Information Pin Configuration Part Number Package Option Packing HV2901K6-G 64-Lead QFN (9x9) 260/Tray 64 1 -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VDD logic supply -0.5V to +6.5V VPP-VNN differential supply 220V VPP positive supply -0.5V to VNN +200V VNN negative supply 64-Lead QFN (K6) (top view) +0.5V to -200V Logic input voltage -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel Storage temperature 3.0A -65°C to 150°C Power dissipation 1.5W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Product Marking HV2901K6 LLLLLLLLL YYWW AAA CCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging Package may or may not include the following marks: Si or 64-Lead QFN (K6) Typical Thermal Resistance Package θja 64-Lead QFN 21OC/W Recommended Operating Conditions Sym Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply +40V to VNN +200V VNN Negative high voltage supply -40V to -160V VIH High level input voltage 0.9VDD to VDD VIL Low level input voltage 0V to 0.1VDD VSIG Analog signal voltage peak-to-peak VNN +10V to VPP -10V Operating free air temperature 0OC to 70OC TA Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Doc.# DSFP-HV2901 B011713 2 Supertex inc. www.supertex.com HV2901 DC Electrical Characteristics (Over recommended operating conditions unless otherwise specified ) Sym RONS Parameter Small signal switch ON-resistance 0OC +25OC +70OC Min Max Min Typ Max Min Max - 30 - 26 38 - 48 - 25 - 22 27 - 32 - 25 - 22 27 - 30 - 18 - 18 24 - 27 - 23 - 20 25 - 30 Unit Conditions ISIG = 5.0mA VPP = +40V, ISIG = 200mA VNN = -160V Ω ISIG = 5.0mA VPP = +100V, ISIG = 200mA VNN = -100V ISIG = 5.0mA VPP = +160V, ISIG = 200mA VNN = -40V - 22 - 16 25 - 27 Small signal switch ON-resistance matching - 20 - 5.0 20 - 20 % RONL Large signal switch ON-resistance ISIG = 5.0mA, VPP = +100V, VNN = -100V - - - 15 - - - Ω VSIG = VPP -10V, ISIG = 1A RINT Value of output bleed resistor - - 20 35 50 - - KΩ ISOL Switch OFF-leakage per switch - 5.0 - 1.0 10 - 15 μA DC offset switch OFF - 300 - 100 300 - 300 VSIG = VPP -10V, VNN +10V DC offset switch ON - 500 - 100 500 - 500 mV No load IPPQ Quiescent VPP supply current - - - 10 50 - - - - - -10 -50 - - μA All switches OFF IPPQ Quiescent VPP supply current - - - 10 50 - - - - - -10 -50 - - μA All switches ON, ISW = 5.0mA Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A Output switching frequency - - - - 50 - - kHz VSIG duty cycle < 0.1% - 16 - - 20 - 22 - 14 - - 14 - 14 - 14 - - 14 - 14 ΔRONS VOS INNQ INNQ ISW fSW IPP Quiescent VNN supply current Quiescent VNN supply current Average VPP supply current Output switch to RGND IRINT = 0.5mA Duty cycle = 50% mA VPP= +40V, All output VNN = -160V switches are VPP= +100V, turning ON VNN = -100V and OFF at VPP= +160V, 50kHz with no load V = -40V mA VPP = +40V, All output VNN = -160V switches are VPP= +100V, turning ON VNN = -100V and OFF at VPP= +160V, 50kHz with no load V = -40V fCLK = 5.0MHz, VDD = 5.0V NN INN Average VNN supply current - 16 - - 20 - 22 - 14 - - 14 - 14 - 14 - - 14 - 14 - 8.0 - - 8.0 - 8.0 mA - 10 - - 10 - 10 μA All logic inputs are static - 0.45 0.70 - 0.40 - mA 0.45 0.70 - 0.40 - mA VOUT = VDD -0.7V 10 - 10 pF IDD Average VDD supply current ISOR Data out source current 0.45 Data out sink current 0.45 - - 10 IDDQ ISINK CIN Quiescent VDD supply current Logic input capacitance - - NN VOUT = 0.7V --- * See Test Circuits on page 5 Doc.# DSFP-HV2901 B011713 3 Supertex inc. www.supertex.com HV2901 AC Electrical Characteristics (Over recommended operating conditions unless otherwise specified) Sym Parameter tSD Set up time before LE rises tWLE Time width of LE tDO Clock delay time to data out tWCLR Time width of CLR tSU Set up time data to clock tH Hold time data from clock 0OC +25OC +70OC Min Max Min Typ Max Min Max 25 - 25 - - 25 - 56 - - 56 - 56 - 12 - - 12 - 12 - 8.0 40 8.0 19 40 8.0 40 8.0 30 8.0 15 30 8.0 30 55 - 55 - - 55 - 21 - 21 - - 21 - 7.0 - 7.0 - - 7.0 - 5.0 - 5.0 - - 5.0 - 7.0 - 7.0 - - 7.0 - - 8 - - 8 - 8 - 20 - - 20 - 20 Unit Conditions ns ns ns ns ns ns --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V fCLK Clock frequency tR, tF Clock rise and fall times - 50 - - 50 - 50 tON Turn ON time - 5.0 - - 5.0 - 5.0 tOFF Turn OFF time - 5.0 - - 5.0 - 5.0 - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 -33 - -30 - -58 - -58 -60 - -58 - -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle OFF capacitance SW to GND - 14 - 9.0 14 - 14 OFF capacitance Y to GND - 28 - 18 28 - 28 pF VSIG = 0, f = 1.0MHz, both SW OFF ON capacitance SW to GND - 33 - 23 33 - 33 ON capacitance Y to GND - 33 - 23 33 - 33 pF VSIG = 0, f = 1.0MHz, one SW ON, one SW OFF +VSPK - - - - +150 - - -VSPK - - - - -150 - - - - - - +150 - - - - - - -150 - - +VSPK - - - - +150 - - -VSPK - - - - -150 - - dv/dt Maximum VSIG slew rate KO OFF isolation KCR Switch crosstalk IID CSG(OFF) CSG(ON) +VSPK -VSPK Output voltage spike SW MHz VDD = 5.0V ns --- μs VSIG = VPP -10V, RLOAD = 10kΩ VPP = +40V, VNN = -160V V/ns VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V dB f = 5.0MHz, 1.0kΩ//15pF load f = 5.0MHz, 50Ω load VPP = +40V, VNN = -160V RLOAD = 50Ω mV VPP = +100V, VNN = -100V RLOAD = 50Ω VPP = +160V, VNN = -40V RLOAD = 50Ω * See Test Circuits on page 5 Doc.# DSFP-HV2901 B011713 4 Supertex inc. www.supertex.com HV2901 AC Electrical Characteristics (cont.) Sym Parameter 0OC +25OC +70OC Unit Conditions Min Max Min Typ Max Min Max +VSPK - - - - +150 - - -VSPK - - - - -150 - - - - - - +150 - - - - - - -150 - - +VSPK - - - - +150 - - -VSPK - - - - -150 - - VPP = +160V, VNN = -40V RLOAD = 50Ω - - - 820 - - - VPP = +40V, VNN = -160V - - - 600 - - - - - - 350 - - - +VSPK -VSPK QC Output voltage spike Y Charge injection (per switch) Doc.# DSFP-HV2901 B011713 5 VPP = +40V, VNN = -160V RLOAD = 50Ω mV pC VPP = +100V, VNN = -100V RLOAD = 50Ω VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V Supertex inc. www.supertex.com HV2901 Test Circuits VPP -10V SW0 ISOL NC NC SW1 SW0 VOUT NC Y01 Y01 RGND RGND VPP VPP VDD VNN VNN GND 5.0V SW0 SW1 VPP VPP VDD VNN GND SW0 VSIG NC IID 50Ω NC RGND VPP VPP VDD VNN VNN GND KO = 20Log 5.0V VPP VPP VDD VNN VNN GND VIN = 10VP-P @5.0MHz NC 1000pF 50Ω NC NC Y01 NC VPP VDD VNN VNN GND VOUT SW1 SW0 5.0V VPP VDD VNN GND SW2 Y01 RL 1kΩ 5.0V NC SW3 VOUT Y23 50Ω VPP VPP VDD VNN VNN GND SW0 NC VPP VPP VDD VNN GND VOUT VIN -VSPK 5.0V SW1 RL 1kΩ VOUT RGND VNN 5.0V Crosstalk +VSPK RGND 5.0V RGND Isolation Diode Current Y01 VPP SW1 Y01 VNN -VSPK 50Ω VNN SW0 KCR = 20Log +VSPK NC TON/TOFF Test Circuit VIN SW1 SW1 Y01 VOUT ΔVOUT VOUT 5.0V SW1 VPP OFF Isolation SW0 SW0 RLOAD 10kΩ VOUT DC Offset ON/OFF Y01 VOUT VPP -10V NC RGND VNN Switch OFF Leakage VIN = 10VP-P @5.0MHz SW1 Y01 NC RGND 50Ω VPP VPP VDD VNN VNN GND 5.0V Q = 1000pF • ∆VOUT Charge Injection Doc.# DSFP-HV2901 B011713 Output Voltage Spike SW 6 Output Voltage Spike Y Supertex inc. www.supertex.com HV2901 Truth Table D0 D1 L ... D15 D16 - - H - - L - D31 LE CLR SW0 SW1 SW15 SW16 - - L L OFF - - - - - - - L L - - - L L ON - - - - - OFF - - - H - - - L L - ON - - - - - - - - L L - - - - - - - - - - L L - - - - - - - L - - H - - L L - - OFF - - - - L L - - ON - - - - L - L L - - - OFF - - - H - L L - - - ON - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - L L L - - - - OFF - - - - H L L - - - - ON X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF ... ... ... ... ... ... ... SW31 - Notes: 1. The 32 switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. All 32 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. 4. DOUT is high when data in the register 31 is high. 5. Shift registers clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DN+1 DN DATA IN 5 0% LE 50% DN-1 50% 50% tWLE tSD 50% CLOCK tSU 50% th tDO DATA OUT VOUT (typ) tOFF OFF tON 90% 1 0% ON CLR Doc.# DSFP-HV2901 B011713 50% 5 0% 5 0% tWCL 7 Supertex inc. www.supertex.com HV2901 Pin Function Pin Function Pin Function Pin Function Pin Function 1 SW30 17 SW2 33 Y1213 49 SW19 2 Y3031 18 Y23 34 SW13 50 SW20 3 SW31 19 SW3 35 VPP 51 Y2021 4 NC 20 SW4 36 RGND 52 SW21 5 CLR 21 Y45 37 VNN 53 SW22 6 NC 22 SW5 38 SW14 54 Y2223 7 LE 23 SW6 39 Y1415 55 SW23 8 CLK 24 Y67 40 SW15 56 SW24 9 VDD 25 SW7 41 SW16 57 Y2425 10 DIN 26 SW8 42 Y1617 58 SW25 11 GND 27 Y89 43 SW17 59 SW26 12 DOUT 28 SW9 44 VNN 60 Y2627 13 NC 29 SW10 45 RGND 61 SW27 14 SW0 30 Y1011 46 VPP 62 SW28 15 Y01 31 SW11 47 SW18 63 Y2829 16 SW1 32 SW12 48 Y1819 64 SW29 VSUB (Thermal Pad) Doc.# DSFP-HV2901 B011713 The central thermal pad on the bottom of package must be connected to VNN externally 8 Supertex inc. www.supertex.com HV2901 64-Lead QFN Package Outline (K6) 9.00x9.00mm body, 1.00mm height (max), 0.50mm pitch D2 D 64 1 64 1 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e E E2 b Top View Bottom View View B Note 3 θ A A3 Seating Plane Side View A1 L Note 2 L1 View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 e 0.20 8.90 7.60 8.90 7.60 0.25 9.00 7.70 9.00 7.70 0.30 9.10 7.80 9.10 7.80 0.50 BSC L L1 θ 0.30 0.00 0O 0.40 - - 0.50 0.15 14O Drawings are not to scale. Supertex Doc.#: DSPD-64QFNK69X9P050, Version B020112 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV2901 B011713 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com