Supertex inc. HV20320 Low Charge Injection 8-Channel High Voltage Analog Switch Features General Description ►► HVCMOS technology for high performance ►► Very low quiescent power dissipation (-10µA) ►► Output on-resistance typically 22Ω ►► Low parasitic capacitances ►► DC to 50MHz small signal frequency response ►► -60dB typical output off isolation at 5.0MHz ►► CMOS logic circuitry for low power ►► Excellent noise immunity ►► On-chip shift register, latch and clear logic circuitry ►► Flexible high voltage supplies This device is a low charge injection, 8-channel, high-voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. ® Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS® technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. Applications ►► Medical ultrasound imaging ►► Piezoelectric transducer drivers These ICs are suitable for various combinations of high voltage supplies, e.g., VPP/VNN : +50V/-150V, or +100V/-100V. Block Diagram Level Output Latches Shifters Switches DIN CLK 8-Bit Shift Register DOUT VDD Doc.# DSFP-HV20320 C071613 LE CL D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 VNN VPP Supertex inc. www.supertex.com HV20320 Pin Configuration Ordering Information 4 Part Number Package Option Packing HV20230PJ-G 28-Lead PLCC 38/Tube HV20230PJ-G M904 28-Lead PLCC 500/Reel 1 28 26 -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter 28-Lead PLCC Value VDD logic power supply voltage -0.5V to +15V VPP - VNN supply voltage VPP positive high voltage supply 220V -0.5V to VNN +200V VNN negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel 3.0A Storage temperature -65 C to +150 C O Power dissipation O 1.2W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. (top view) Product Marking Top Marking YY = Year Sealed WW = Week Sealed LLLLLLLLLL L = Lot Number A = Assembler ID Bottom Marking C = Country of Origin* = “Green” Packaging YYWW AAA HV20320PJ CCCCCCCCCCC *May be part of top marking Package may or may not include the following marks: Si or 28-Lead PLCC Typical Thermal Resistance Package θja 28-Lead PLCC 48OC/W Operating Conditions Sym Parameter Value VDD Logic power supply voltage VPP Positive high voltage supply1,3 VNN Negative high voltage supply VIH High level input voltage VDD -1.5V to VDD VIL Low-level input voltage 0V to 1.5V VSIG Analog signal voltage peak-to-peak TA 4.5V to 13.2V 1,3 40V to VNN +200V -40V to -160V 1,3 VNN +10V toVPP -10V2 Operating free air temperature 0OC to 70OC Notes: 1. Power up/down sequence is arbtrary except GND must be powered -up first and powered down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Doc.# DSFP-HV20320 C071613 2 Supertex inc. www.supertex.com HV20320 DC Electrical Characteristics (Over operating conditions unless otherwise specified ) Sym Parameter 0OC +25OC Min Max Min +70OC Typ Max Min Max Unit Conditions - 30 - 26 38 - 48 ISIG = 5.0mA - 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 - 18 - 18 24 - 27 - 23 - 20 25 - 30 ISIG = 5.0mA - 22 - 16 25 - 27 ISIG = 200mA Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % RONL Large signal switch on-resistance ISIG = 5.0mA, VPP = +100V, VNN = -100V - - - 15 - - - Ω VSIG = VPP -10V, ISIG = 1.0A ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 μA VSIG = VPP -10V, VNN +10V DC offset switch off - 300 - 100 300 - 300 mV RL = 100kΩ DC offset switch on - 500 - 100 500 - 500 mV RL = 100kΩ IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches Off INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches Off IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches On, ISW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches On, ISW = 5.0mA ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycly < 0.1% fSW Output switching frequency - - - - 50 - - kHz - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 RONS ΔRONS VOS IPP INN Small signal switch on-resistance Supply current Supply curent Ω ISIG = 5.0mA ISIG = 200mA VPP = +100V VNN = -100V VPP = +160V VNN = -40V VPP = +40V VNN = -160V mA VPP = +100V VNN = -100V VPP = +160V VNN = -40V Duty cycle = 50% VPP = +40V VNN = -160V mA VPP = +40V VNN = -160V VPP = +100V VNN = -100V VPP = +160V VNN = -40V All output switches are turning On and Off at 50kHz with no load All output switches are turning On and Off at 50kHz with no load IDD Logic supply average current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Logic supply quiescent current - 10 - - 10 - 10 μA --- ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD -0.7V ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V CIN Logic input capacitance - 10 10 - 10 pF --- Doc.# DSFP-HV20320 C071613 - - 3 Supertex inc. www.supertex.com HV20320 AC Electrical Characteristics (Over recommended operating conditions: VDD = 5.0V, unless otherwise specified) Sym Parameter 0OC +25OC Min Max Min +70OC Typ Max Min Max Unit Conditions tSD Set up time before LE rises 150 - 150 - - 150 - ns --- tWLE Time width of LE 150 - 150 - - 150 - ns --- tDO Clock delay time to data out - 150 - - 150 - 150 ns --- tWCL Time width of CL 150 - 150 - - 150 - ns --- tSU Set up time data to clock 15 - 15 8.0 - 20 - ns --- tH Hold time data from clock 35 - 35 - - 35 - ns --- fCLK Clock frequency - 5.0 - - 5.0 - 5.0 tR, tF Clock rise and fall times - 50 - - 50 - 50 ns --- tON Turn on time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩ tOFF Turn off time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩ - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 -33 - -30 - -58 - -58 - - -58 - -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) Off capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz +VSPK - - - - 150 - - -VSPK - - - - 150 - - - - - - 150 - - - - - - 150 - - +VSPK - - - - 150 - - -VSPK - - - - 150 - - - - - 820 - - - - - - 600 - - - - - - 350 - - - dv/dt Maximun VSIG slew rate KO Off isolation KCR Switch crosstalk IID +VSPK -VSPK QC Output switch isolation diode current Output voltage spike Charge injection Doc.# DSFP-HV20320 C071613 4 MHz 50% Duty cycle, fDATA= fCLK/2 VPP = +160V, VNN = -40V V/ns VPP = +100V, VNN = -100V VPP = +40V, VNN = -160V dB f = 5.0MHz, 1.0kΩ/15pF load f = 5.0MHz, 50Ω load VPP = +40V, VNN = -160V, RLOAD = 50Ω mV VPP = +100V, VNN = -100V, RLOAD = 50Ω VPP = +160V, VNN = -40V, RLOAD = 50Ω VPP = +40V, VNN = -160V, VSIG = 0V pC VPP = +100V, VNN = -100V, VSIG = 0V VPP = +160V, VNN = -40V, VSIG = 0V Supertex inc. www.supertex.com HV20320 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On X X X X X X X X H L Hold Previous State X X X X X X X X X H All Switches Off Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch. 4. DOUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DN+1 DN-1 DN DATA IN 50% 50% LE 50% 50% tWLE tSD CLOCK 50% tSU 50% th tDD SU DATA OUT 50% tOFF VOUT (typ) OFF ON 10% 50% CLR Doc.# DSFP-HV20320 C071613 tON 90% 50% tWCL 5 Supertex inc. www.supertex.com HV20320 Test Circuits VPP -10V VPP -10V RL ISOL VOUT VOUT RLOAD 100kΩ VNN +10V VPP VPP VDD VNN VNN GND 10KW RL VPP VPP VDD VNN VNN GND 5.0V 5.0V VPP VPP VDD VNN VNN GND TON/TOFF Test Circuit DC Offset ON/OFF Switch OFF Leakage VIN = 10VP-P @5.0MHz 5.0V VIN = 10VP-P @5.0MHz VSIG IID VOUT 50W VNN RL VPP VPP VDD VNN VNN GND KO = 20Log NC 50W VPP VPP VDD VNN VNN GND 5.0V VOUT VIN 5.0V VPP VPP VDD VNN VNN GND KCR = 20Log Isolation Diode Current OFF Isolation 5.0V VOUT VIN Crosstalk +VSPK VOUT VOUT -VSPK 1000pF VSIG VOUT RL 50W 1KW VPP VPP VDD VNN VNN GND 5.0V VPP VPP VDD VNN VNN GND 5.0V Q = 1000pF x VOUT Output Voltage Spike Charge Injection Doc.# DSFP-HV20320 C071613 6 Supertex inc. www.supertex.com HV20320 Typical Performance Curves Off-Isolation vs Signal Voltage Frequency IDD vs Clock Frequency 3.0 VDD = 5.0V, VPP/VNN = ±100V, TA = 0 to 70OC VDD = 5.0V, VPP/VNN = ±100V -80.0 -75.0 Off-Isolation (dB) IDD Current (mA) TA = 70OC 2.0 1.0 TA = 0OC -70.0 -65.0 -60.0 -55.0 0.0 10 1000 100 -50.0 1.0 10000 CLK Frequency (kHz) 10.0 Signal Voltage Frequency (MHz) RON vs VPP/VNN RON vs Ambient Temperature (TA) VDD = 5.0V, VPP/VNN = ±100V 40.0 ISW = 5.0mA 20.0 ISW = 200mA -25 0 25 50 75 100 125 150 VPP 0 40V VNN -160V VPP/VNN = ±100V 100 IPP/INN Average Current (mA) TDO (ns) 60 VDD = 13.5V 40 20 0 -25 0 25 50 80V 100V 120V 140V 160V -120V -100V -80V -60V -40V VDD = 5.0V, VPP/VNN = ±100V 5 VDD = 5.0V 80 60V -140V IPP/INN vs Output Switching Frequency TDO vs Ambient Temperature (TA) 75 100 TA = 0OC TA = 25OC 4 TA = 70OC TA = 125OC 3 2 1 0 0 125 25 50 75 100 125 150 Output Switching Frequency (KHz) Ambient Temperature ( C) O Doc.# DSFP-HV20320 C071613 TA = 25OC 20.0 10.0 Ambient Temperature (OC) -50 TA = 85OC 30.0 TA = 0OC 10.0 0 -50 TA = 125OC 40.0 RON (Ω) @5.0mA RON (Ω) 30.0 VDD = 5.0V 50.0 7 Supertex inc. www.supertex.com HV20320 Pin Description Pin # Name Pin # Name 1 SW3 15 N/C 2 SW3 16 DIN 3 SW2 17 CLK 4 SW2 18 LE 5 SW1 19 CL 6 SW1 20 DOUT 7 SW0 21 SW7 8 SW0 22 SW7 9 VPP 23 SW6 10 VNN 24 SW6 11 N/C 25 SW5 12 GND 26 SW5 13 VDD 27 SW4 14 N/C 28 SW4 Doc.# DSFP-HV20320 C071613 8 Supertex inc. www.supertex.com HV20320 28-Lead PLCC Package Outline (PJ) .453x.453in. body, .180in. height (max), .050in. pitch D .048/.042 x 45O D1 1 4 28 .056/.042 x 45O 26 .150max Note 1 (Index Area) .075max E E1 Note 2 e .020max (3 Places) Top View Vertical Side View View B b1 A A1 Base .020min Plane A2 Seating Plane b Horizontal Side View R View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .485 .450 .485 .450 NOM .172 .105 - - - .490 .453 .490 .453 MAX .180 .120 .083 .021 .032 .495 .456 .495 .456 e .050 BSC R .025 .035 .045 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. Supertex Doc. #: DSPD-28PLCCPJ, Version B031111. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV20320 C071613 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com