Supertex inc. HV219 200V Low Charge Injection 8-Channel High Voltage Analog Switch Features ►► HVCMOS technology for high performance ►► Very low quiescent power dissipation (-10µA) ►► Output on-resistance typically 11Ω ►► Low parasitic capacitance ►► DC to 50MHz small signal frequency response ►► -60dB typical off-isolation at 5.0MHz ►► CMOS logic circuitry for low power ►► Excellent noise immunity ►► Serial shift register logic control with latches ►► Flexible operating supply voltages ►► Surface mount packages ® Applications ►► Medical ultrasound imaging ►► Non-destructive evaluation General Description The Supertex HV219 is a low switch resistance, low charge injection, 8-channel, 200V, analog switch integrated circuit (IC) intended primarily for medical ultrasound imaging. The device can also be used for NDE (non-destructive evaluation) applications. The HV219 is a lower switch resistance, 11Ω versus 22Ω, version of the Supertex HV20220 device. The lower switch resistance will help reduce insertion loss. It has the same pin configuration as that of the Supertex HV20220PJ and the HV20220FG. The device is manufactured using Supertex’s HVCMOS® (high voltage CMOS) technology with high voltage bilateral DMOS structures for the outputs and low voltage CMOS logic for the input control. The outputs are configured as eight independent single pole single throw 11Ω analog switches. The input logic is an 8-bit serial to parallel shift register followed by an 8-bit parallel latch. The switch states are determined by the data in the latch. Logic high will correspond to a closed switch and logic low as an opened switch. The HV219 is designed to operate on various combinations of high voltage supplies. For example the VPP and VNN supplies can be: +40V/-160V, +100V/-100V, or +160V/-40V. This allows the user to maximize the signal voltage for uni-polar negative, bi-polar, or unipolar positive. Block Diagram Level Output Latches Shifters Switches DIN CLK 8-Bit Shift Register DOUT VDD GND LE CL Doc.# DSFP-HV219 C070713 D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 VNN VPP Supertex inc. www.supertex.com HV219 Pin Configuration Ordering Information Part Number HV219FG-G HV219FG-G M931 HV219PJ-G HV219PJ-G M904 Package Option 48-Lead LQFP 28-Lead PLCC Packing 48 1 250/Tray 1000/Reel 38/Tube 48-Lead LQFP 500/Reel (top view) -G denotes a lead (Pb)-free / RoHS compliant package 4 1 28 26 Absolute Maximum Ratings Parameter VDD logic power supply voltage VPP - VNN supply voltage VPP positive high voltage supply VNN negative high voltage supply Value -0.5V to +15V 220V +0.5V to -200V Logic input voltages -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel Storage temperature Power dissipation: 28-Lead PLCC 48-Lead LQFP 28-Lead PLCC -0.5V to VNN +200V (top view) Product Marking Top Marking YY = Year Sealed WW = Week Sealed L = Lot Number Bottom Marking C = Country of Origin* A = Assembler ID* = “Green” Packaging CCCCCCCC YYWW HV219FG 3.0A LLLLLLLLL -65OC to +150OC 1.2W 1.0W AAA *May be part of top marking Package may or may not include the following marks: Si or 48-Lead LQFP Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Top Marking YYWW HV219PJ Operating Conditions Sym Parameter LLLLLLLLLL VDD Logic power supply voltage 4.5V to 13.2V VPP Positive high voltage supply 40V to VNN +200V VNN Negative high voltage supply -40V to -160V VIH High level input logic voltage VDD -1.5V to VDD VIL Low-level input logic voltage 0V to 1.5V VSIG Analog signal voltage peak-to-peak TA Operating free air temperature Bottom Marking Value VNN +10V to VPP -10V 0OC to 70OC CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Package may or may not include the following marks: Si or 28-Lead PLCC Typical Thermal Resistance Package θja 48-Lead LQFP 52OC/W 28-Lead PLCC 48OC/W Power Up/Down Sequence 1. Power up/down sequence is arbitrary except GND must be powered up first and powered down last. This applies for applications powering GND of the IC with different voltages. 2. VSIG must always be at or in between VPP and VNN or floating during power up/down transition. 3. Rise and fall times of the power supplies VDD, VPP, and VNN should not be less than 1.0ms. Doc.# DSFP-HV219 C070713 2 Supertex inc. www.supertex.com HV219 DC Electrical Characteristics (over recommended operating conditions unless otherwise noted) Sym Parameter 0OC +25OC +70OC Units Conditions Min Max Min Typ Max Min Max - 15 - 13 19 - 24 - 13 - 11 14 - 16 - 13 - 11 14 - 15 - 9.0 - 9.0 12 - 14 - 12 - 10 13 - 15 - 11 - 8 13 - 14 Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % RONL Large signal switch on-resistance ISIG = 5.0mA, VPP = +100V, VNN = -100V - - - 8.0 - - - Ω VSIG = VPP -10V, ISIG = 1.0A ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 µA VSIG = VPP -10V & VNN +10V DC offset switch off - 300 - 100 300 - 300 mV RLOAD = 100kΩ DC offset switch on - 500 - 100 500 - 500 mV RLOAD = 100kΩ IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches on, ISW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches on, ISW = 5.0mA ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycle < 0.1% fSW Output switch frequency - - - - 50 - - kHz - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 RONS ΔRONS VOS IPP INN Small signal switch on-resistance Average VPP supply current Average VNN supply current ISIG = 5.0mA VPP = +40V ISIG = 200mA VNN = -160V Ω ISIG = 5.0mA VPP = +100V ISIG = 200mA VNN = -100V ISIG = 5.0mA VPP= +160V V ISIG = 200mA NN = -40V Duty cycle = 50% VPP = +40V VNN = -160V mA All output switches VPP = +100V are turning on and off VNN = -100V at 50kHz VPP = +160V with no load VNN = -40V VPP = +40V VNN = -160V mA All output switches VPP = +100V are turning on and off VNN = -100V at 50kHz VPP = +160V with no load VNN = -40V IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 µA All logic inputs are static ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD -0.7V ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V CIN Large input capacitance - 10 - - 10 - 10 pF --- Doc.# DSFP-HV219 C070713 3 Supertex inc. www.supertex.com HV219 AC Electrical Characteristics (over recommended operating conditions, V Sym Parameter 0OC +25OC DD = 5.0V, unless otherwise noted) +70OC Min Max Min Typ Max Min Max Units Conditions tSD Set-up time before LE rises 150 - 150 - - 150 - ns --- tWLE Time width of LE 150 - 150 - - 150 - ns --- tDO Clock delay time to data out - 150 - - 150 - 150 ns --- tWCL Time width of CL 150 - 150 - - 150 - ns --- tSU Set-up time data to clock 15 - 15 8.0 - 20 - ns --- tH Hold time data from clock 35 - 35 - - 35 - ns --50% duty cycle, fDATA = fCLK/2 fCLK Clock frequency - 5.0 - - 5.0 - 5.0 MHz tr, tf Clock rise and fall times - 50 - - 50 - 50 ns --- TON Turn-on time - 5.0 - - 5.0 - 5.0 µs TOFF Turn-off time - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10kΩ - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 -33 - - - -58 - -58 - - - - dv/dt Maximum VSIG slew rate VPP = +40V, VNN = -160V V/ns VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V f = 5.0MHz, 1.0KΩ//15pF load KO Off isolation KCR Switch crosstalk - - -60 - - - - dB f = 5.0MHz, 50Ω load Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2% duty cycle CSG(OFF) Off capacitance SW to GND 14 25 14 20 25 14 25 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 40 60 40 50 60 40 60 pF 0V, f = 1.0MHz +VSPK - - - - 150 - - -VSPK - - - - 200 - - - - - - 150 - - - - - - 200 - - +VSPK - - - - 150 - - -VSPK - - - - 200 - - - - - 1450 - - - - - - 1050 - - - - - - 550 - - - IID +VSPK -VSPK QC Output voltage spike Charge injection Doc.# DSFP-HV219 C070713 4 dB f = 5.0MHz, 50Ω load VPP = +40V, VNN = -160V, RLOAD = 50Ω mV VPP = +100V, VNN = -100V, RLOAD = 50Ω VPP = +160V, VNN = -40V, RLOAD = 50Ω VPP = +40V, VNN = -160V, VSIG = 0V pC VPP = +100V, VNN = -100V, VSIG = 0V VPP = +160V, VNN = -40V, VSIG = 0V Supertex inc. www.supertex.com HV219 Truth Table Data in 8-Bit Shift Register Output Switch State LE CL L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON D0 D1 D2 D3 D4 D5 D6 D7 X X X X X X X X H L X X X X X X X X X H SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 Hold Previous State OFF OFF OFF OFF OFF OFF OFF OFF Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition clock. 3. The switches go to a state retaining their present condition at the rising edge of the LE. 4. When LE is low, the shift register data flows through the latch. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The clear input overrides all other inputs. Logic Timing Waveforms DN+1 DN DATA IN 50% LE 50% DN-1 50% 50% tWLE tSD 50% CLOCK tSU DATA OUT VOUT (typ) 50% tDO th 50% tOFF OFF 90% 10% ON CLR tON 50% 50% tWCL Doc.# DSFP-HV219 C070713 5 Supertex inc. www.supertex.com HV219 Test Circuits VPP - 10V VPP -10V ISOL RLOAD 10kΩ VOUT VOUT RLOAD 100kΩ VNN + 10V VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND DC Offset ON/OFF Switch OFF Leakage 5V TON/TOFF Test Circuit VIN = 10VP-P @5.0MHz VIN = 10VP-P @5.0MHz VSIG IID VOUT 50Ω VNN RLOAD VPP VPP VDD VNN VNN GND KO = 20 Log 5V 50Ω VPP VPP VDD VNN VNN GND VOUT VIN 5V VPP VPP VDD VNN VNN GND KCR = 20Log Isolation Diode Current OFF Isolation 5V VOUT VIN Crosstalk +VSPK VOUT VOUT NC -VSPK 1000pF VSIG VOUT RLOAD 50Ω 1.0KΩ VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND 5V Q = 1000pF x VOUT Charge Injection Doc.# DSFP-HV219 C070713 Output Voltage Spike 6 Supertex inc. www.supertex.com HV219 Pin Description 48-Lead LQFP Pin Name Pin Name Pin Name Pin Name 1 SW5 13 NC 25 VNN 37 DOUT 2 NC 14 SW2 26 NC 38 NC 3 SW4 15 NC 27 NC 39 SW7 4 NC 16 SW1 28 GND 40 NC 5 SW4 17 NC 29 VDD 41 SW7 6 NC 18 SW1 30 NC 42 NC 7 NC 19 NC 31 NC 43 SW6 8 SW3 20 SW0 32 NC 44 NC 9 NC 21 NC 33 DIN 45 SW6 10 SW3 22 SW0 34 CLK 46 NC 11 NC 23 NC 35 LE 47 SW5 12 SW2 24 VPP 36 CLR 48 NC Pin Description 28-Lead PLCC Pin Name Pin Name Pin Name Pin Name 1 SW3 8 SW0 15 NC 22 SW7 2 SW3 9 NC 16 DIN 23 SW6 3 SW2 10 VPP 17 CLK 24 SW6 4 SW2 11 NC 18 LE 25 SW5 5 SW1 12 VNN 19 CL 26 SW5 6 SW1 13 GND 20 DOUT 27 SW4 7 SW0 14 VDD 21 SW7 28 SW4 Doc.# DSFP-HV219 C070713 7 Supertex inc. www.supertex.com HV219 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch D D1 E1 E Note 1 (Index Area D1/4 x E1/4) 48 1 e b Top View View B A A2 Gauge Plane L2 Seating Plane L L1 A1 Seating Plane θ View B Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D D1 E E1 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* - - 1.40 0.22 9.00 7.00 9.00 7.00 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* e 0.50 BSC L 0.45 0.60 0.75 L1 L2 1.00 REF 0.25 BSC θ 0O 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. Doc.# DSFP-HV219 C070713 8 Supertex inc. www.supertex.com HV219 28-Lead PLCC Package Outline (PJ) .453x.453in. body, .180in. height (max), .050in. pitch D .048/.042 x 45O D1 1 4 28 .056/.042 x 45O 26 .150max Note 1 (Index Area) .075max E E1 Note 2 e .020max (3 Places) Top View Vertical Side View View B b1 A A1 Base .020min Plane A2 Seating Plane b Horizontal Side View R View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .485 .450 .485 .450 NOM .172 .105 - - - .490 .453 .490 .453 MAX .180 .120 .083 .021 .032 .495 .456 .495 .456 e .050 BSC R .025 .035 .045 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. Supertex Doc. #: DSPD-28PLCCPJ, Version B031111. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV219 C070713 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com