5-V Low Drop Voltage Regulator TLE 4262 Features • • • • • • • • • • • • Output voltage tolerance ≤ ±2% 200 mA output capability Low-drop voltage Very low standby current consumption Overtemperature protection Reverse polarity protection Short-circuit proof Adjustable reset threshold Wide temperature range Suitable for use in automotive electronics Green Product (RoHS compliant) AEC Qualified P-DSO-14-3, -8, -9, -11, 14 Functional Description TLE 4262 GM is a 5-V low-drop voltage regulator in a P/PG-DSO-20-1,-6,-7,-9,-14,PG-DSO-14 or PG-DSO-20 SMD package. The maximum input voltage is 45 V. The maximum output current is more than 200 mA. The IC is short-circuit proof and includes a temperature protection which turns off the IC at overtemperature. The IC regulates an input voltage VI in the range of 6 V < VI < 45 V to VQ,nom = 5.0 V. A reset signal is generated for an output voltage of VQ,rt < 4.5 V. This voltage threshold can be decreased to 3.5 V by external connection of a voltage divider. The reset delay can be set externally with a capacitor. The IC can be switched off via the inhibit input, which reduces the current consumption from 900 µA to typical 0 µA. Type Package TLE 4262 GM PG-DSO-14-30 TLE 4262 G PG-DSO-20-35 Data Sheet 1 Rev. 2.8, 2008-05-19 TLE 4262 Dimensioning Information on External Components The input capacitor CI is necessary for compensation of line influences. Using a resistor of approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values ≥ 22 µF and an ESR of ≤ 3 Ω within the operating temperature range. For small tolerances of the reset delay, the spread of the capacitance of the dalay capacitor and its temperature coefficient should be noted. TLE 4262 GM TLE 4262 G INH RO N.C. GND GND GND GND N.C. D RADJ 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Ι N.C. N.C. GND GND GND GND N.C. N.C. Q RO N.C. GND GND GND D RADJ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 INH Ι GND GND GND Q N.C. AEP02588 AEP01083 Figure 1 Data Sheet Pin Configuration (top view) 2 Rev. 2.8, 2008-05-19 TLE 4262 Table 1 Pin Definitions and Functions Pin PG-DSO-1430 Pin Symbol PG-DSO-2035 Function 1 2 RO Reset output; open-collector output internally connected to the output via a resistor of 30 kΩ. 2, 8 3, 8, 12, 13, 18, 19 N.C. Not connected 3 - 5, 10 - 12 4 - 7, 14 - 17 GND Ground 6 9 D Reset delay; connect capacitor to GND for setting delay time 7 10 RADJ Reset threshold; for setting the switching threshold connect by a voltage divider from output to ground. If this input is connected to GND, reset is triggered at an output voltage of 4.5 V. 9 11 Q 5-V output voltage; block to ground by capacitor with C ≥ 22 µF, ESR ≤ 3 Ω at 10 kHz. 13 20 I Input voltage; block to ground directly at the IC by a ceramic capacitor. 14 1 INH Inhibit; TTL-compatible, low-active input Data Sheet 3 Rev. 2.8, 2008-05-19 TLE 4262 Circuit Description The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. If the externally scaled down output voltage at the reset threshold input drops below 1.35 V, the external reset delay capacitor is discharged by the reset generator. If the voltage on the capacitor reaches the lower threshold VDRL, a reset signal is issued on the reset output and not cancelled again until the upper threshold VDU is exceeded. If the reset threshold input is connected to GND, reset is triggered at an output voltage of 4.5 V. The IC can be switched at the TTL-compatible, low-active inhibit input. It also includes a number of internal circuits for protection against: • • • Overload Overtemperature Reverse polarity Saturation Control and Protection Circuit Temperature Sensor I 9 13 Control Amplifier Bandgap Reference 6 Q D Buffer Reset Generator 1 7 RO RADJ Adjustment 14 INH Figure 2 Data Sheet 3-5, 10-12 GND AEB01081 Block Diagram 4 Rev. 2.8, 2008-05-19 TLE 4262 Table 2 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks Min. Max. VI II -42 – 45 – V – – internally limited VRO IRO -0.3 – 42 – V – – internally limited VRADJ -0.3 6 V – VD ID -0.3 – 42 – V – – internally limited VQ IQ -5.25 – VI – V – – internally limited VINH -42 45 V – IGND -0.5 – A – Tj Tstg – -50 150 150 °C °C – – 5.2 45 V 1) Junction temperature VI Tj -40 150 °C – Thermal resistance junction-ambient junction-case Rthj-a Rthj-p – – 112 32 K/W K/W 2) Input I Input voltage Input current Reset Output RO Voltage Current Reset Input RADJ Voltage Reset Delay D Voltage Current Output Q Voltage Current Inhibit INH Voltage Ground GND Current Temperature Junction temperature Storage temperature Operating Range Input voltage 3) 1) Corresponds with characteristics of drop voltage, output current and power description (see diagrams). 2) Package mounted on PCB 80 × 80 × 1.5 mm3; 35µ Cu; 5µ Sn; Footprint only; zero airflow. 3) Measured to pin 4. Data Sheet 5 Rev. 2.8, 2008-05-19 TLE 4262 Table 3 Characteristics VI = 13.5 V; Tj = 25 °C; VINH > 3.5 V; (unless specified otherwise) Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition Normal Operation Output voltage VQ 4.90 5.00 5.10 V 5 mA ≤ IQ ≤ 150 mA; 6 V ≤ VI ≤ 28 V; -40 °C ≤ Tj ≤ 125 °C Output voltage VQ 4.90 5.00 5.10 V 6 V ≤ VI ≤ 32 V; IQ = 100 mA Tj = 100 °C Output current limiting IQ Iq Iq Iq Iq VDR ∆VQ,lo ∆VQ,li 200 250 – mA – – – – – 0 0.9 10 15 50 1.3 18 23 µA mA mA mA – 0.35 0.50 V – – 25 mV – 3 25 mV PSRR – 54 – dB VINH = 0 V IQ = 0 mA IQ = 150 mA IQ = 150 mA; Vi = 4.5 V IQ = 150 mA1) IQ = 5 mA to 150 mA VI = 6 V to 28 V; IQ = 150 mA fr = 100 Hz; Vr = 0.5 Vpp 4.5 4.65 4.8 V 1.26 1.35 1.44 V – 0.10 0.40 V – 50 100 mV VRADJ = 0 V VQ > 3.5 V IRO = 1 mA VQ < VRT 6 10 15 µA – 1.4 1.8 2.2 V – 0.20 0.35 0.55 V – – 17 – ms – 1.2 – µs CD = 100 nF CD = 100 nF Current consumption; Iq = Ii - IQ Drop voltage Load regulation Line regulation Power Supply Ripple Rejection Reset Generator VQ,rt Reset adjust threshold VRADJ Saturation voltage VRO Saturation voltage VD,sat Charge current ID,c Upper timing threshold VDU Lower timing threshold VDRL trd Reset delay time Reset reaction time trr Switching threshold Data Sheet 6 Rev. 2.8, 2008-05-19 TLE 4262 Table 3 Characteristics (cont’d) VI = 13.5 V; Tj = 25 °C; VINH > 3.5 V; (unless specified otherwise) Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. 3.6 – – V IC turned on – – 0.8 V IC turned off 5 10 25 µA VINH = 5 V Inhibit Switch-ON voltage Switch-OFF voltage Input current VINH,ON VINH,OFF IINH 1) Drop voltage VI ≥ 4.5 V; drop voltage = VI - VQ (below regulating range) Note: The reset output is low within the range 1 V ≤ VQ ≤ VQ,rt. Data Sheet 7 Rev. 2.8, 2008-05-19 TLE 4262 Ι 13 Input 6 V...45 V 9 Q Output 470 nF INH KL15 Reset to µC RO 14 6 TLE 4262G D 100 k Ω 22 µF 100 nF 1 7 RADJ 56 k Ω GND AES03028 Figure 3 Application Circuit II I 1000 µF 13 9 Q IQ 470 nF 22 µF Rext TLE 4262G IINH VI + Vripple INH 14 6 D GND 5.6 k Ω RO 1 4 RADJ VD CD VQ VRO ID VINH IRO IGND Vcd 100 nF VDR = VI - VQ *) PSRR = 20 log *) Below Figure 4 Data Sheet Vripple ∆VQ Regulation Range AES03027_4262 Test Circuit 8 Rev. 2.8, 2008-05-19 TLE 4262 VΙ t < t rr VQ V Q, rt d V Ι D,c = dt CD VD t V DU V DRL VRO t rr t rd t t Power-on-Reset Figure 5 Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED03010 Time Response Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor CD which can be calculated as follows: CD = (∆trd × ID,c)/∆V (1) Definitions: • • • • • CD = delay capacitor ∆trd = delay time ID,c = charge current, typical 10 µA ∆V = VDU, typical 1.8 V VDU = upper delay switching threshold at CD for reset delay time Data Sheet 9 Rev. 2.8, 2008-05-19 TLE 4262 Charge Current versus Temperature ID, c Upper and Lower Timing Threshold VDU and VDRL versus Temperature AED03090 16 µA 14 AED01087_4262 3.2 V V 2.8 VI = 13.5 V 2.4 12 ID, c VI = 13.5 V Vcd = 1.5 V 8 1.6 6 1.2 4 0.8 2 0.4 0 -40 VDU 2.0 10 0 40 80 0 -40 120 ˚C 160 VDRL 0 40 80 Tj Tj Reset Switching Threshold versus Temperature Current Consumption of Inhibit versus Temperature Output Current AED01088 1.6 VRADJ V 1.4 12 1.0 10 0.8 8 0.6 6 0.4 4 0.2 2 0 40 80 0 -40 120 ˚C 160 VINH = 5 V 0 40 80 120 ˚C 160 Tj Tj Data Sheet AED03091 16 µA IINH 14 1.2 0 -40 120 ˚C 160 10 Rev. 2.8, 2008-05-19 TLE 4262 Output Voltage versus Temperature VQ Output Current versus Input Voltage AED01090 5.2 V ΙQ 5.1 VI = 13.5 V mA 200 4.9 150 4.8 100 4.7 50 0 40 80 0 120 ˚C 160 T j = 25 C 250 5.0 4.6 -40 AED01091 300 0 10 20 30 Tj Drop Voltage versus Output Current 40 V 50 VΙ Current Consumption versus Output Current AED01094 800 VDR mV 700 AED01095 32 Iq mA 28 600 24 500 20 VI = 13.5 V 400 16 T j = 125 ˚C 25 ˚C 300 12 200 8 100 4 0 0 50 100 150 200 mA 0 300 50 100 150 200 mA 300 IQ IQ Data Sheet 0 11 Rev. 2.8, 2008-05-19 TLE 4262 Current Consumption versus Input Voltage AED01096 30 Ιq Output Voltage versus Input Voltage mA VQ 25 V 10 20 8 R L = 25 Ω 15 6 10 4 5 2 0 AED01097 12 0 Data Sheet 10 20 30 0 40 V 50 VΙ 12 R L = 25 Ω 0 2 4 6 8 V 10 VΙ Rev. 2.8, 2008-05-19 TLE 4262 Package Outlines 1.75 MAX. C 1) 4 -0.2 B 1.27 0.64 ±0.25 0.1 2) 0.41+0.10 -0.06 6±0.2 0.2 M A B 14x 14 0.2 M C 8 1 7 1) 8.75 -0.2 8˚MAX. 0.19 +0.06 0.175 ±0.07 (1.47) 0.35 x 45˚ A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01230 Figure 6 PG-DSO-14-30 (Plastic Dual Small Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 13 Rev. 2.8, 2008-05-19 1.27 0.35 7.6 -0.2 1) 8˚ MAX. 0.35 x 45˚ 0.23 +0.09 2.65 MAX. 2.45 -0.2 0.2 -0.1 TLE 4262 0.4 +0.8 0.1 +0.15 2) 0.2 20x 20 10.3 ±0.3 11 10 1 12.8 -0.2 1) Index Marking 1) 2) Does not include plastic or metal protrusion of 0.15 max. per side Does not include dambar protrusion of 0.05 max. per side GPS05094 Figure 7 PG-DSO-20-35 (Plastic Dual Small Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 14 Rev. 2.8, 2008-05-19 TLE 4262 Revision History Version Date Rev. 2.8 2008-05-19 Modification according to PCN No. 2008-096: Typo corrected: Current consumption Iq specification @ IQ = 150mA on page 6. Rev. 2.7 2007-03-20 Initial version of RoHS-compliant derivate of TLE 4262 Page 1: AEC certified statement added Page 1 and Page 13 ff: RoHS compliance statement and Green product feature added Page 1 and Page 13 ff: Package changed to RoHS compliant version Legal Disclaimer updated Data Sheet Changes 15 Rev. 2.8, 2008-05-19 Edition 2008-05-19 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. 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