5-V Low Drop Fixed Voltage Regulator TLE 4271-2 Features • • • • • • • • • • • • Output voltage tolerance ≤ ±2% Low-drop voltage Integrated overtemperature protection Reverse polarity protection Input voltage up to 42 V Overvoltage protection up to 65 V (≤ 400 ms) Short-circuit proof Suitable for use in automotive electronics Wide temperature range Adjustable reset and watchdog time Green Product (RoHS compliant) AEC Qualified P-TO220-7-11 ^ Functional Description P-TO220-7-12 The TLE 4271-2 is functional and electrical identical to TLE 4271. The device is a 5-V low drop fixed voltage regulator. The maximum input voltage is 42 V (65 V, ≤ 400 ms). Up to an input voltage of 26 V and for an output current up to 550 mA it regulates the output voltage within a 2% accuracy. The short circuit protection limits the output current of more than 650 mA. The IC can be switched off via the inhibit input. An integrated watchdog monitors the connected controller. The device incorporates overvoltage protection and temperature protection that disables the circuit at overtemperature. Type Package TLE 4271-2 PG-TO220-7-11 TLE 4271-2 S PG-TO220-7-12 TLE 4271-2 G PG-TO263-7-1 Data Sheet 1 P-TO263-7-1 Rev. 2.7, 2007-06-25 TLE 4271-2 PG-TO220-7-11 PG-TO220-7-12 PG-TO263-7-1 1 7 Ι 1 7 1 7 RO D Q INH GND WI AEP01938 Ι RO D Q INH GND WI Ι RO D Q INH GND WI AEP02017 AEP01939 Figure 1 Pin Configuration (top view) Table 1 Pin Definitions and Functions Pin Symbol Function 1 I Input; block to ground directly on the IC with ceramic capacitor. 2 INH Inhibit 3 RO Reset Output; the open collector output is connected to the 5 V output via an integrated resistor of 30 kΩ. 4 GND Ground 5 D Reset Delay; connect a capacitor to ground for delay time adjustment. 6 WI Watchdog Input 7 Q 5-V Output; block to ground with 22 µF capacitor, ESR < 3 Ω. Data Sheet 2 Rev. 2.7, 2007-06-25 TLE 4271-2 Circuit Description The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of a series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. The reset output RO is in high-state if the voltage on the delay capacitor CD is greater or equal VUD. The delay capacitor CD is charged with the current ID for output voltages greater than the reset threshold VRT. If the output voltage gets lower than VRT (‘reset condition’) a fast discharge of the delay capacitor CD sets in and as soon as VD gets lower than VLD the reset output RO is set to low-level. The time for the delay capacitor charge from VUD to VLD is the reset delay time tD. When the voltage on the delay capacitor has reached VUD and reset was set to high, the watchdog circuit is enabled and discharges CD with the constant current IDWD. If there is no rising edge observed at the watchdog input, CD will be discharge down to VLDW, then reset output RO will be set to low and CD will be charged again with the current IDWC until VD reaches VUD and reset will be set high again. If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge period CD is charged again and the reset output stays high. After VD has reached VUD, the periodical behavior starts again. Internal protection circuits protect the IC against: • • • • Overload Overvoltage Overtemperature Reverse polarity Data Sheet 3 Rev. 2.7, 2007-06-25 TLE 4271-2 Saturation Control and Protection Circuit Temperature Sensor Ι 7 1 Control Amplifier Adjustment Bandgap Reference 3 Buffer + - Reset Generator Watchdog 2 INH Figure 2 Data Sheet 4 GND 5 6 Q RO D WI AEB01940 Block Diagram 4 Rev. 2.7, 2007-06-25 TLE 4271-2 Table 2 Absolute Maximum Ratings Tj = -40 to 150 °C Parameter Symbol Limit Values Unit Notes Min. Max. VI VI II -42 – – 42 65 – V V mA – VINH VINH IINH -42 – – 42 65 – V V mA – VRO IRO -0.3 – 42 – V mA – internally limited VD ID -0.3 -5 7 5 V mA – – VW IW -0.3 -5 7 5 V mA – – VQ IQ -1.0 -5 16 – V mA – internally limited IGND -0.5 – A – Tj Tstg – -50 150 150 °C °C – – Input Voltage Voltage Current t ≤ 400 ms internally limited Inhibit Voltage Voltage Current t ≤ 400 ms internally limited Reset Output Voltage Current Reset Delay Voltage Current Watchdog Voltage Current Output Voltage Current Ground Current Temperatures Junction temperature Storage temperature Data Sheet 5 Rev. 2.7, 2007-06-25 TLE 4271-2 Table 3 Operating Range Parameter Symbol Limit Values Unit Notes Min. Max. VI Tj 6 40 V – -40 150 °C – Junction ambient Rthja – – 65 70 K/W K/W – PG-TO263-7-1 Junction case Rthjc Zthjc – – 3 2 K/W K/W – Input voltage Junction temperature Thermal Resistance Data Sheet 6 t < 1 ms Rev. 2.7, 2007-06-25 TLE 4271-2 Table 4 Characteristics VI = 13.5 V; -40 °C ≤ Tj ≤ 125 °C; VINH > VU,INH (unless otherwise specified) Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition Output voltage VQ 4.90 5.00 5.10 V 5 mA ≤ IQ ≤ 550 mA; 6 V ≤ VI ≤ 26 V Output voltage VQ 4.90 5.00 5.10 V 26 V ≤ VI ≤ 36 V; IQ ≤ 300 mA Output current limiting IQmax 650 800 – mA VQ = 0 V Current consumption Iq = II Iq – – 6 µA VINH = 0 V; IQ = 0 mA Current consumption Iq = II Iq – 800 – µA VINH = 5 V; IQ = 0 mA Current consumption Iq = II - IQ Iq – 1 1.5 mA IQ = 5 mA Current consumption Iq = II - IQ Iq – 55 75 mA IQ = 550 mA Current consumption Iq = II - IQ Iq – 70 90 mA IQ = 550 mA; VI = 5 V Drop voltage Vdr ∆VQ – 350 700 mV – 25 50 mV ∆VQ – 12 25 mV – 54 – dB IQ = 550 mA1) IQ = 5 to 550 mA; VI = 6 V VI = 6 to 26 V IQ = 5 mA fr = 100 Hz; Vr = 0.5 Vpp Load regulation Supply voltage regulation Power supply Ripple PSRR rejection Data Sheet 7 Rev. 2.7, 2007-06-25 TLE 4271-2 Table 4 Characteristics (cont’d) VI = 13.5 V; -40 °C ≤ Tj ≤ 125 °C; VINH > VU,INH (unless otherwise specified) Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. 4.5 4.65 4.8 V – 4.5 – – V – Saturation voltage VRT VROH VRO,SAT – 60 – mV Saturation voltage VRO,SAT – 200 400 mV Rintern = 30 kΩ; 1.0 V ≤ VQ ≤ 4.5 V IR = 3 mA2); VQ = 4.4 V Reset pull-up R 18 30 46 kΩ internally connected to Q Lower reset timing threshold VLD 0.2 0.45 0.8 V VQ < VRT Charge current ID VUD 8 14 25 µA VD = 1.0 V 1.4 1.8 2.3 V – tD tRR 8 13 18 ms – – 3 µs CD = 100 nF CD = 100 nF VI, ov 40 44 46 V – VU,INH VL,INH IINH 1.0 2.0 3.5 V 0.8 1.3 3.3 V 8 12 25 µA VQ = high (> 4.5 V) VQ = low (< 0.8 V) VINH = 5 V Upper watchdog switching threshold VUDW 1.4 1.8 2.3 V – Lower watchdog switching threshold VLDW 0.2 0.45 0.8 V – Discharge current IDWD IDWC tWD,P 1.5 2.7 3.5 µA 8 14 25 µA 40 55 80 ms VD = 1 V VD = 1 V CD = 100 nF Reset Generator Switching threshold Reset high voltage Upper timing threshold Delay time Reset reaction time Overvoltage Protection Turn-off voltage Inhibit Turn-on voltage Turn-off voltage Inhibit current Watchdog Charge current Watchdog period Data Sheet 8 Rev. 2.7, 2007-06-25 TLE 4271-2 Table 4 Characteristics (cont’d) VI = 13.5 V; -40 °C ≤ Tj ≤ 125 °C; VINH > VU,INH (unless otherwise specified) Parameter Symbol Watchdog trigger time tWI,tr Watchdog pulse slew rate VWI Limit Values Min. Typ. Max. 30 45 66 Unit Test Condition ms CD = 100 nF see diagram 5 – – V/µs from 20% to 80% VQ 1) Drop voltage = VI - VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 13.5 V input) 2) Test condition not applicable during delay time for power-on reset. Data Sheet 9 Rev. 2.7, 2007-06-25 TLE 4271-2 ΙΙ 1 1000 µF 7 ΙQ 22 µF 470 nF TLE 4271-2 Ι 3 RO 2 VΙ 5 ΙD V INH VD VQ 4 6 Ι GND V WI CD V RO AES01941 Figure 3 Test Circuit 7 1 Input 5 V-Output 470 nF Input e.g. KL 15 2 Reset to MC 3 TLE 4271-2 6 4 Watchdog Signal from MC Figure 4 Data Sheet 22 µF 5 100 nF AES01942 Circuit 10 Rev. 2.7, 2007-06-25 TLE 4271-2 Application Description The IC regulates an input voltage in the range of 6 V < VI < 40 V to VQnom = 5.0 V. Up to 26 V it produces a regulated output current of more than 550 mA. Above 26 V the saveoperating-area protection allows operation up to 36 V with a regulated output current of more than 300 mA. Overvoltage protection limits operation at 42 V. The overvoltage protection hysteresis restores operation if the input voltage has dropped below 36 V. The IC can be switched off via the inhibit input, which causes the quiescent current to drop below 10 µA. A reset signal is generated for an output voltage of VQ < 4.5 V. The watchdog circuit monitors a connected controller. If there is no positive-going edge at the watchdog input within a fixed time, the reset output is set to low. The delay for power-on reset and the maximum permitted watchdog-pulse period can be set externally with a capacitor. Design Notes for External Components An input capacitor CI is necessary for compensation of line influences. The resonant circuit consisting of lead inductance and input capacitance can be damped by a resistor of approx. 1 Ω in series with CI. An output capacitor CQ is necessary for the stability of the regulating circuit. Stability is guaranteed at values of CQ ≥ 22 µF and an ESR of < 3 Ω. Reset Circuitry If the output voltage decreases below 4.5 V, an external capacitor CD on pin D will be discharged by the reset generator. If the voltage on this capacitor drops below VDRL, a reset signal is generated on pin RO, i.e. reset output is set low. If the output voltage rises above the reset threshold, CD will be charged with constant current. After the power-onreset time the voltage on the capacitor reaches VDU and the reset output will be set high again. The value of the power-on-reset time can be set within a wide range depending of the capacitance of CD. Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor Cd which can be calculated as follows: tD = CD × ∆V/ID (1) Definitions: • • • • • CD = delay capacitor tD = reset delay time ID = charge current, typical 14 µA ∆V = VUD, typical 1.8 V VUD = upper delay timing threshold at CD for reset delay time Data Sheet 11 Rev. 2.7, 2007-06-25 TLE 4271-2 The reset reaction time trr is the time it takes the voltage regulator to set the reset out LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs for delay capacitor of 47 nF. For other values for Cd the reaction time can be estimated using the following equation: tRR ≈ 20 s/F × Cd (2) VΙ t VINH VU, INH VL, INH t < t RR VQ VRT VD VUD t t RR dV Ι D = dt C D VLD VD, SAT VRO t tD VRO, SAT t Power on Thermal Reset Shutdown Figure 5 Data Sheet Voltage Drop at Input Undervoltage at Output Secondary Load Spike Bounce Shutdown AET01985 Time Response 12 Rev. 2.7, 2007-06-25 TLE 4271-2 Watchdog Timing V WΙ VΙ VQ VD t WΙ, tr t WD, P VUDW VLDW t WD, L VR t WΙ, tr = Figure 6 Data Sheet (V UDW - VLDW ) Ι DWD C D ; t WD, P = (V UDW - VLDW ) (V UDW - VLDW ) (Ι DWC + Ι DWD ) t WD, L = C ; CD D Ι DWC . Ι DWD Ι DWC AES03078 Time Response, Watchdog Behavior 13 Rev. 2.7, 2007-06-25 TLE 4271-2 Typical Performance Characteristics Output Voltage VQ versus Temperature Tj VQ Output Voltage VQ versus Input Voltage VI (VINH = VI) AED01928 5.2 V AED01929 12 VQ 5.1 V 10 VI = 13.5 V 5.0 8 4.9 6 4.8 4 4.7 2 4.6 -40 0 40 80 0 120 ˚C 160 Tj Data Sheet 14 R L = 25 Ω 0 2 4 6 8 V 10 VΙ Rev. 2.7, 2007-06-25 TLE 4271-2 Output Current Limit IQ versus Temperature Tj Output Current IQ versus Input Voltage VI AED01930 1200 mA I Q max IQ A 1000 1.0 800 0.8 600 0.6 400 0.4 200 0.2 0 -40 0 40 80 AED01931 1.2 0 120 ˚C 160 T j = 125 ˚C 25 ˚C 0 10 20 30 40 V 50 Tj VI Current Consumption Iq versus Output Current IQ Current Consumption Iq versus Output Current IQ Ιq AED03076 6 mA Ιq AED03077 80 mA 70 5 60 4 50 40 3 VΙ = 13.5 V 30 2 VΙ = 13.5 V 20 1 0 10 0 20 40 60 80 0 mA 120 100 200 300 400 mA 600 ΙQ ΙQ Data Sheet 0 15 Rev. 2.7, 2007-06-25 TLE 4271-2 Current Consumption Iq versus Input Voltage VI Drop Voltage Vdr versus Output Current IQ AED01934 120 AED02755 800 mV V Dr 700 Iq mA 100 600 80 500 T j = 125 C R L = 10 Ω 60 400 300 40 R L = 20 Ω 50 Ω 20 0 T j = 25 C 200 100 0 10 20 30 0 40 V 50 0 200 600 400 mA ΙQ VI Inhibit Current IINH versus Inhibit Voltage VINH Output Voltage VQ versus Inhibit Voltage VINH AED01944 12 AED01945 6 Ι INH, high µA Ι INH 10 VQ V 5 V Ι = 13.5 V T j = 25 C Ι INH, on 8 4 6 3 V Ι = 13.5 V T j = 25 C 4 2 2 0 1000 1 Ι INH, off 0 Data Sheet 1 2 3 4 0 5 V 6 V INH 16 0 1 2 3 4 5 V 6 V INH Rev. 2.7, 2007-06-25 TLE 4271-2 Inhibit Current Consumptions IINH versus Temperature Tj AED01946 14 Ι INH Inhibit Voltages VINH versus Temperature Tj AED01947 6 µA 12 V INH Ι INH, high V 5 10 4 8 Ι INH, on 3 6 V INH, on 2 4 1 2 V INH, off Ι INH, off 0 -40 0 40 80 120 Tj 0 -40 160 0 40 80 120 C 160 Tj Switching Voltage VUD and VLDW versus Temperature Tj AED01948 2.4 V V Ι = 13.5 V V 2.0 V UD , V UDW 1.6 1.2 0.8 0.4 V LDW 0 -40 Data Sheet 0 40 80 120 C 160 Tj 17 Rev. 2.7, 2007-06-25 TLE 4271-2 Charge Current ID, IDWC and Discharge Current IDWD versus Temperature Tj 16 µA I 14 Watchdog Pulse Time Tw versus Temperature Tj AED01949 I D, I DWC 12 60 10 50 VI = 13.5 V VD = 1 V 8 AED01950 80 ms T W 70 V Ι = 13.5 V C D = 100 nF 40 30 6 20 4 I DWD 10 2 0 -40 0 40 80 0 -40 120 ˚C 160 Tj Data Sheet 18 0 40 80 120 C 160 Tj Rev. 2.7, 2007-06-25 TLE 4271-2 Package Outlines 10 ±0.2 A 9.9 ±0.2 9.8 ±0.15 1.27 ±0.1 0.25 3.7 ±0.3 10.2 ±0.3 C 0.5 ±0.1 2.4 7x 0.6 ±0.1 6x 1.27 1) 0.05 1.6 ±0.3 2.8 ±0.2 3.7 -0.15 8.6 ±0.3 0...0.15 9.25 ±0.2 1) 13.4 15.65 ±0.3 17 ±0.3 8.5 4.4 1) 3.9 ±0.4 M A C 8.4 ±0.4 Typical All metal surfaces tin plated, except area of cut. GPT09083 Figure 7 PG-TO220-7-11 (Plastic Transistor Single Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 19 Rev. 2.7, 2007-06-25 TLE 4271-2 10 ±0.2 A 9.8 ±0.15 B 0...0.15 13 ±0.5 0.05 0.5 ±0.1 7x 0.6 ±0.1 1.27 9.25 ±0.2 1.27 ±0.1 11±0.5 C 1) 4.4 2.8 ±0.2 1) 13.4 17 ±0.3 15.65 ±0.3 8.5 1) 3.7 -0.15 2.4 0.25 M A B C Typical All metal surfaces tin plated, except area of cut. GPT09084 Figure 8 PG-TO220-7-12 (Plastic Transistor Single Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 20 Rev. 2.7, 2007-06-25 TLE 4271-2 4.4 10 ±0.2 1.27 ±0.1 0...0.3 B 0.05 2.4 0.1 4.7 ±0.5 2.7 ±0.3 7.551) 1±0.3 9.25 ±0.2 (15) A 8.5 1) 0...0.15 7 x 0.6 ±0.1 6 x 1.27 0.5 ±0.1 0.25 M A B 8˚ MAX. 1) Typical Metal surface min. X = 7.25, Y = 6.9 All metal surfaces tin plated, except area of cut. Figure 9 0.1 B GPT09114 PG-TO263-7-1 (Plastic Transistor Single Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 21 Rev. 2.7, 2007-06-25 TLE 4271-2 Revision History Version Date Rev. 2.7 2007-03-20 Initial version of RoHS-compliant derivate of TLE 4271-2 Page 1: AEC certified statement added Page 1 and Page 19 ff: RoHS compliance statement and Green product feature added Page 1 and Page 19 ff: Package changed to RoHS compliant version Legal Disclaimer updated Data Sheet Changes 22 Rev. 2.7, 2007-06-25 Edition 2007-06-25 Published by Infineon Technologies AG 81726 Munich, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. 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