Supertex inc. TN0606 N-Channel Enhancement-Mode Vertical DMOS FET General Description Features ►► ►► ►► ►► ►► ►► ►► This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Low threshold - 2.0V max. High input impedance Low input capacitance - 100pF typical Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage Applications ►► ►► ►► ►► ►► ►► ►► Logic level interfaces – ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches Ordering Information Part Number TN0606N3-G Product Summary Package Option Packing TO-92 1000/Bag TO-92 2000/Reel TN0606N3-G P002 TN0606N3-G P003 TN0606N3-G P005 Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. BVDSS/BVDGS RDS(ON) ID(ON) (max) (min) 1.5Ω 3.0A 60V VGS(th) (max) 3.0V Pin Configuration TN0606N3-G P013 TN0606N3-G P014 -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. DRAIN SOURCE Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature -55OC to +150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. GATE TO-92 Product Marking SiTN 0 6 0 6 YYWW YY = Year Sealed WW = Week Sealed = “Green” Packaging Package may or may not include the following marks: Si or Typical Thermal Resistance Package θja TO-92 132OC/W Doc.# DSFP-TN0606 B080813 TO-92 Supertex inc. www.supertex.com TN0606 Thermal Characteristics ID Package TO-92 (continuous)† ID Power Dissipation (pulsed) @TC = 25OC 500mA 3.2A 1.0W IDR† IDRM 500mA 3.2A Notes: † ID (continuous) is limited by max rated Tj . Electrical Characteristics (T A Sym = 25OC unless otherwise specified) Parameter Min Typ Max Units 60 - - V VGS = 0V, ID = 1.0mA 0.6 - 2.0 V VGS = VDS, ID= 1.0mA Change in VGS(th) with temperature - - -4.5 IGSS Gate body leakage - - 100 nA VGS = ± 20V, VDS = 0V - - 10 µA IDSS Zero gate voltage drain current VGS = 0V, VDS = Max Rating - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) On-state drain current 1.2 2.0 - 3.0 6.7 - - - 15 - 1.5 2.0 - 1.0 1.5 - - 0.75 400 500 - BVDSS † VGS(th) Gate threshold voltage ΔVGS(th) RDS(ON) ΔRDS(ON) Drain-to-source voltage Static drain-to-source on-state resistance Change in RDS(ON) with temperature Conditions mV/OC VGS = VDS, ID= 1.0mA A VGS = 5.0V, VDS = 25V VGS = 10V, VDS = 25V VGS = 3.0V, ID = 250mA Ω VGS = 5.0V, ID = 750mA VGS = 10V, ID = 750mA %/OC VGS = 10V, ID = 750mA GFS Forward transductance CISS Input capacitance - 100 150 COSS Common source output capacitance - 50 85 CRSS Reverse transfer capacitance - 10 35 td(ON) Turn-on delay time - - 6 Rise time - - 14 Turn-off delay time - - 16 Fall time - - 16 Diode forward voltage drop - 0.8 1.8 V VGS = 0V, ISD = 1.5A Reverse recovery time - 300 - ns VGS = 0V, ISD = 1.5A tr td(OFF) tf VSD trr mmho VDS = 25V, ID = 1.0A pF ns VGS = 0V, VDS = 25V, f = 1.0MHz VDD = 25V, ID = 1.5A, RGEN = 25Ω Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 10V INPUT 0V Pulse Generator 10% t(ON) td(ON) VDD OUTPUT 0V Doc.# DSFP-TN0606 B080813 VDD 90% t(OFF) tr td(OFF) OUTPUT RGEN tf INPUT 10% 10% 90% RL D.U.T. 90% 2 Supertex inc. www.supertex.com TN0606 Typical Performance Curves Output Characteristics 10 8.0 8.0 6.0 ID (amperes) VGS = 10V ID (amperes) Saturation Characteristics 10 9V 8V 4.0 7V 6.0 VGS = 10V 9V 8V 4.0 7V 6V 6V 5V 2.0 5V 4V 3V 2.0 3V 0 1.0 0 10 20 30 40 0 0 50 2.0 4.0 6.0 8.0 10 VDS (volts) VDS (volts) Transconductance vs. Drain Current Power Dissipation vs. Case Temperature 2.0 VDS = 25V 0.6 TA = -55OC PD (watts) GFS (siemens) 0.8 25OC 0.4 150OC TO-92 1.0 0.2 0 0 2.0 4.0 6.0 8.0 0 10 ID (amperes) Maximum Rated Safe Operating Area 1.0 Thermal Resistance (normalized) ID (amperes) 1.0 TO-92 (DC) TC = 25OC 0.01 1.0 Doc.# DSFP-TN0606 B080813 10 VDS (volts) 100 25 50 75 100 125 150 TC (OC) 10 0.1 0 0.8 0.6 0.4 0.2 0 1000 Thermal Response Characteristics TO-92 PD = 1.0W TC = 25OC 0.001 0.01 0.1 1.0 10 tP (seconds) 3 Supertex inc. www.supertex.com TN0606 Typical Performance Curves (cont.) BVDSS Variation with Temperature On-Resistance vs. Drain Current 5.0 1.1 VGS = 5.0V RDS(ON) (ohms) BVDSS (normalized) 4.0 1.0 VGS = 10V 3.0 2.0 1.0 0.9 -50 0 50 100 0 150 0 2.0 4.0 10 8.0 10 Tj ( C) Transfer Characteristics V(th) and RDS Variation with Temperature 2.0 VDS = 25V 1.4 6.0 VGS(th) (normalized) TA = -55OC 25OC 4.0 150OC 2.0 V(th) @ 1.0mA 1.2 1.2 RDS @ 10V, 0.75A 1.0 0.8 0.8 RDS(ON) (normalized) 1.6 8.0 ID (amperes) 6.0 ID (amperes) O 0.4 0.6 0 0 2.0 4.0 6.0 8.0 10 -50 0 50 VGS (volts) Tj (OC) Capacitance vs. Drain-to-Source Voltage 200 0 150 100 Gate Drive Dynamic Characteristics 10 f = 1.0MHz VDS = 10V 8.0 VGS (volts) C (picofarads) 150 CISS 100 VDS = 40V 6.0 172 pF 4.0 COSS 50 2.0 CRSS 0 0 10 20 30 95 pF 0 40 Doc.# DSFP-TN0606 B080813 0 0.5 1.0 1.5 2.0 2.5 QG (nanocoulombs) VDS (volts) 4 Supertex inc. www.supertex.com TN0606 3-Lead TO-92 Package Outline (N3) D A Seating Plane 1 2 3 L c b e1 e Side View Front View E1 E 1 3 2 Bottom View Symbol Dimensions (inches) A b c D E E1 e e1 L MIN .170 .014† .014† .175 .125 .080 .095 .045 .500 NOM - - - - - - - - - MAX .210 .022† .022† .205 .165 .105 .105 .055 .610* JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TN0606 B080813 5 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com