Supertex inc. TC8020 Six Pair, N- and P-Channel Enhancement-Mode MOSFET Features ►► High voltage, vertical DMOS technology ►► Integrated gate-to-source resistor ►► Integrated gate-to-source Zener diode ►► Typical peak output +/-3.5A at 50V ►► Low threshold, low on-resistance ►► Low input & output capacitance ►► Fast switching speeds ►► Electrically isolated N- and P-MOSFET pairs Applications ►► High voltage pulsers ►► Amplifiers ►► Buffers ►► Piezoelectric transducer drivers ►► General purpose line drivers ►► Logic level interfaces General Description The Supertex TC8020 consists of six pairs of high voltage, low threshold N- and P-channel MOSFETs in a 56-lead QFN package. All MOSFETs have integrated gate-to-source resistors and gate-to-source Zener diode clamps which are desired for high voltage pulser applications. The complimentary, high-speed, high voltage, gate-clamped N- and P-channel MOSFET pairs utilize an advanced vertical DMOS structure and Supertex’s wellproven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input and output capacitance, and fast switching speeds are desired. Typical Application +3.3V +12V +12V +12V VLL/EN AVDD VDD1 VDD2 OP1A ON1A OP2A 1.8 to 3.3V CMOS Input Logic 10nF 10nF POSA GP3 NEGA ON3A GN3 OP1B GP4 POSB NEGB ON2A SELB OP2B OP3B ON3B AGND GND AVSS(SUB) VSS -12V -12V 10nF 10nF 10nF 10nF SP4 SP1 DP1 DN1 DP2 GN2 OP3A MD1715 SP6 SP3 SP5 SP2 GP2 ON2A 10nF VPP1 GN1 SELA ON2B Doc.# DSFP-TC8020 C091112 10nF GP1 VPP2 TX(A) DN2 DP3 TC8020 GN4 DN3 DP4 DN4 GP5 DP5 GN5 TX(B) DN5 GP6 DP6 GN6 DN6 PAD SN6 SN3 SN5 SN2 SN4 SN1 VNN2 VNN1 Supertex inc. www.supertex.com TC8020 Ordering Information Product Summary Part Number Package Option Packing TC8020K6-G 56-Lead QFN (8x8) 250/Tray BVDSS/BVDGS RDS(ON) (V) -G indicates package is RoHS compliant (‘Green’) (max) (Ω) N-Channel P-Channel N-Channel P-Channel 200 -200 8.0 9.5 Pin Configuration 56 1 Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Operating and storage temperature -55°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. Thermal Characteristics Package θja 56-Lead QFN (K6) 27OC/W Note: 1.0oz, 4-layer, 3”x4” PCB 56-Lead QFN (K6) Top View Package Marking TC8020K6 LLLLLLLLL YYWW AAA CCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging Package may or may not include the following marks: Si or 56-Lead QFN (K6) Doc.# DSFP-TC8020 C091112 2 Supertex inc. www.supertex.com TC8020 N-Channel Electrical Characteristics (T = 25°C unless otherwise specified) A Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 1.0mA VGS(th) Gate threshold voltage 1.0 - 2.4 V VGS = VDS, ID = 1.0mA - - -4.5 mV/OC VGS = VDS, ID = 1.0mA ΔVGS(th) Change in VGS(th) with temperature Conditions RGS Gate-to-source shunt resistor 5.0 - 26 KΩ IGS = 100µA VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = 2.0mA - - 10.0 µA VDS = Max rating, VGS = 0V - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC 1.2 1.8 - 2.0 3.2 - - 6.0 9.0 - 5.3 8.0 - - 1.0 %/ C VGS = 10V, ID =1.0A 400 - - mmho VDS = 25V, ID = 500mA IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) ΔRDS(ON) Static drain-to-source on-state resistance Change in RDS(ON) with temperature GFS Forward transconductance CISS Input capacitance - 50 - COSS Common source output capacitance - 18 - CRSS Reverse transfer capacitance - 7.0 - td(ON) Turn-on delay time - - 10 Rise time - - 15 Turn-off delay time - - 20 Fall time - - 15 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr A Ω O VGS = 4.5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 150mA VGS = 10V, ID = 1.0A pF VGS = 0V, VDS = 25V, f = 1.0MHz ns VDD =25V, ID = 500mA, RGEN = 25Ω 1.8 V VGS = 0V, ISD = 500mA - ns VGS = 0V, ISD = 500mA Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. N-Channel Switching Waveforms and Test Circuit 10V 90% VDD Input 0V 10% t(ON) VDD t(OFF) tr td(ON) Pulse Generator 10% td(OFF) RGEN tf 10% RL OUTPUT D.U.T Input Output 0V Doc.# DSFP-TC8020 C091112 90% 90% 3 Supertex inc. www.supertex.com TC8020 P-Channel Electrical Characteristics (T = 25°C unless otherwise specified) A Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -1.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA - - 4.5 mV/OC VGS = VDS, ID = -1.0mA ΔVGS(th) Change in VGS(th) with temperature Conditions RGS Gate-to-source shunt resistor 5.0 - 26 KΩ IGS = -100µA VZGS Gate-to-source Zener voltage -13.2 - -24.0 V IGS = -2.0mA - - -10 µA VDS = Max rating, VGS = 0V - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC -0.80 -1.25 - -2.00 -2.80 - 7.0 10 - 6.5 9.5 - - 1.0 %/ C VGS = -10V, ID =-1.0A 400 - - mmho VDS = -25V, ID = -500mA IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) Static drain-to-source on-state resistance ΔRDS(ON) Change in RDS(ON) with temperature A GFS Forward transconductance CISS Input capacitance - 55 - COSS Common source output capacitance - 20 - CRSS Reverse transfer capacitance - 8.0 - td(ON) Turn-on delay time - - 10 Rise time - - 15 Turn-off delay time - - 20 Fall time - - 15 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr Ω O VGS = -4.5V, VDS = -25V VGS = -10V, VDS = -25V VGS = -4.5V, ID = -150mA VGS = -10V, ID = -1.0A pF VGS = 0V, VDS = -25V, f = 1.0MHz ns VDD = -25V, ID = -1.0A, RGEN = 25Ω -1.8 V VGS = 0V, ISD = -500mA - ns VGS = 0V, ISD = -500mA Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. P-Channel Switching Waveforms and Test Circuit 0V 10% Pulse Generator Input -10V 90% t(ON) td(ON) 0V Output VDD Doc.# DSFP-TC8020 C091112 RGEN t(OFF) tr td(OFF) 90% 10% D.U.T Input tf Output 90% RL VDD 10% 4 Supertex inc. www.supertex.com TC8020 Test Circuit +12V +12V AVDD VDD1 +12V VPP1 VDD2 SP1 VDD2 OP1 GP1 DP1 VDD2 DN1 ON1 GN1 VNN1 SN1 High Speed Gate Buffers VLL/EN VPP2 SP2 VDD1 OP2 SEL POS NEG Control Logic and Level Translation GP2 DP2 VDD1 DN2 ON2 100Ω GN2 VNN2 SN2 GND High Speed Gate Buffers SP3 OP3 GP3 DP3 VSS VDD1 DN3 ON3 SN3 MD1715 1 OF 2-CH GND PAD AVSS -12V Doc.# DSFP-TC8020 C091112 GN3 TC8020 6 of 12-FETs VSS PAD -12V 5 Supertex inc. www.supertex.com TC8020 ON2A VDD1 GND ON1A VDD2 OP2A GND VDD1 OP1A VDD2 NC NC SP2 NC SP1 VSUB NC NC SN1 NC SN2 NC GP1 GP2 Circuit Pin Layout GN1 DN1 GN2 DP1 NC DN2 DP2 SELA ON3A POSA GND GN3 NEGA GND GP3 DN3 OP3A NC DP3 VLL/EN MD1715 TC8020 GP6 DP6 POSB ON3B GN6 DN5 NEGB GND NC DP5 SP3 SP6 DN6 TX(B) NC NC SP5 NC SP4 NC NC VSUB SN4 NC SN5 DP4 NC DN4 GN4 GP4 GN5 GP5 OP1B VDD2 ON2B VSS VDD1 SELB GND NC ON1B OP3B VDD2 AVSS OP2B SN6 GND SN3 GND VDD1 VSS AVDD AGND TX(A) Pin Description Pin Function Description 1 GN1 Gate of N-MOSFET 1 2 GN2 Gate of N-MOSFET 2 3 NC No Connection 4 GN3 Gate of N-MOSFET 3 5 GP3 Gate of P-MOSFET 3 6 NC No Connection 7 SN3 Source of N-MOSFET 3 8 SN6 Source of N-MOSFET 6 9 NC No Connection 10 GP6 Gate of P-MOSFET 6 11 GN6 Gate of N-MOSFET 6 12 NC 13 GN5 Gate of N-MOSFET 5 14 GN4 Gate of N-MOSFET 4 15 GP5 Gate of P-MOSFET 5 16 GP4 Gate of P-MOSFET 4 17 NC No Connection 18 SN5 Source of N-MOSFET 5 Doc.# DSFP-TC8020 C091112 No Connection 6 Supertex inc. www.supertex.com TC8020 Pin Description (cont.) Pin Function Description 19 NC No Connection 20 SN4 Source of N-MOSFET 4 No Connection 21 NC 22 VSUB 23 NC No Connection 24 SP4 Source of P-MOSFET 4 25 NC No Connection 26 SP5 Source of P-MOSFET 5 27 NC No Connection 28 NC No Connection 29 DP4 Drain of P-MOSFET 4 30 DN4 Drain of N-MOSFET 4 31 DP5 Drain of P-MOSFET 5 Die attachment substrate, must be grounded externally. 32 DN5 Drain of N-MOSFET 5 33 DP6 Drain of P-MOSFET 6 34 DN6 Drain of N-MOSFET 6 35 SP6 Source of P-MOSFET 6 36 SP3 Source of P-MOSFET 3 37 DP3 Drain of P-MOSFET 3 38 DN3 Drain of N-MOSFET 3 39 DP2 Drain of P-MOSFET 2 40 DN2 Drain of N-MOSFET 2 41 DP1 Drain of P-MOSFET 1 42 DN1 Drain of N-MOSFET 1 43 NC No Connection 44 NC No Connection 45 SP2 Source of P-MOSFET 2 46 NC No Connection 47 SP1 Source of P-MOSFET 1 No Connection 48 NC 49 VSUB 50 NC No Connection 51 SN1 Source of N-MOSFET 1 52 NC No Connection 53 SN2 Source of N-MOSFET 2 Die attachment substrate, must be grounded externally. 54 NC No Connection 55 GP1 Gate of P-MOSFET 1 56 GP2 Gate of P-MOSFET 2 Note: Thermal Pad must be grounded externally. Doc.# DSFP-TC8020 C091112 7 Supertex inc. www.supertex.com TC8020 56-Lead QFN Package Outline (K6) 8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch D2 D 56 1 56 1 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e E E2 b View B Top View Bottom View Note 3 θ A A3 L Seating Plane L1 Note 2 Side View A1 View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 0.18 7.85* 2.75 7.85* 2.75 0.25 8.00 5.70 8.00 5.70 0.30 8.15* 6.70 8.15* 6.70 † e † 0.50 BSC L L1 θ 0.30 0.00 0O 0.40 - - 0.50 0.15 14O JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings are not to scale. Supertex Doc.#: DSPD-56QFNK68X8P050, Version A031010. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TC8020 C091112 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com