Supertex inc. HV2762 Low Charge Injection 24-Channel SPST High Voltage Analog Switch with Bleed Resistors Features General Description Applications Input data is shifted into a 24-bit shift register that can then be retained in a 24-bit latch. To reduce any possible clock feed through noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. ►► 24 Channels of high voltage analog switch ►► Integrated bleed resistors on the outputs ►► 3.3 or 5.0V CMOS input logic level ►► 24 Channel SPST configuration ►► 20MHz data shift clock frequency ►► HVCMOS technology for high performance ►► Very low quiescent power dissipation - (10µA) ►► Low parasitic capacitance ►► DC to 50MHz analog signal frequency ►► -60dB typical OFF-isolation at 5.0MHz ►► CMOS logic circuitry for low power ►► Excellent noise immunity ►► Cascadable serial data register with latches ►► Flexible operating supply voltages The Supertex HV2762 is a low charge injection, 24-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers, and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. ►► Medical ultrasound imaging ►► Piezoelectric transducer drivers ►► Inkjet printer heads ►► Optical MEMS modules The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/40V. Block Diagram Latches D LE CLR CLK DIN 24-Bit Shift Register DOUT VDD Doc.# DSFP-HV2762 C091112 GND LE CLR Level Output Shifters Switches SW0 D LE CLR SW1 D LE CLR SW2 D LE CLR SW22 D LE CLR SW23 VPP VNN RGND Supertex inc. www.supertex.com HV2762 Pin Configuration Ordering Information Part Number Package Packing HV2762LA-G 64-Pad LFGA 260/Tray HV2762LB-G 64-Ball LFGA 260/Tray 1 2 3 4 5 6 7 8 9 10 A B C D E -G indicates package is RoHS compliant (‘Green’) F G H J K 64-Lead LFGA (LA/LB) (top view) Absolute Maximum Ratings Parameter Value VDD logic supply Product Marking -0.5V to +6.5V VPP-VNN differential supply HV2762LA LLLLLLLLL YYWW AAA CCC 220V VPP positive supply -0.5V to VNN+200V VNN negative supply +0.5V to -200V Logic input voltage -0.5V to VDD +0.3V Analog signal range L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging Package may or may not include the following marks: Si or 64-Pad LFGA (LA) VNN to VPP Peak analog signal current/channel Storage temperature 2.0A HV2762LB LLLLLLLLL YYWW AAA CCC -65°C to 150°C Power dissipation 1.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging Package may or may not include the following marks: Si or 64-Ball LFGA (LB) Typical Thermal Resistance Package θja 64-Pad LFGA 36OC/W 64-Ball LFGA 37OC/W Recommended Operating Conditions Sym Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply +40V to VNN +200V VNN Negative high voltage supply -40V to -160V VIH High level input voltage 0.9VDD to VDD VIL Low level input voltage 0V to 0.1VDD VSIG Analog signal voltage peak-to-peak VNN +10V to VPP -10V Operating free air temperature 0OC to 70OC TA Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Doc.# DSFP-HV2762 C091112 2 Supertex inc. www.supertex.com HV2762 DC Electrical Characteristics (Over recommended operating conditions unless otherwise specified ) Sym Parameter 0OC +25OC +70OC Unit Conditions Min Max Min Typ Max Min Max - - - 26 - - - - - - 22 - - - - - - 22 - - - - - - 18 - - - - - - 20 - - - - - - 16 - - - Small signal switch ON-resistance matching - 20 - 5.0 20 - 20 % RONL Large signal switch ON-resistance ISIG = 5.0mA, VPP = +100V, VNN = -100V - - - 30 - - - Ω VSIG = VPP -10V, ISIG = 1A RINT Output switch shunt resistance - - 20 35 50 - - KΩ ISOL Switch OFF-leakage per switch Output switch to RGND IRINT = 0.5mA - 5.0 - 1.0 10 - 15 μA VSIG = VPP -10V, VNN +10V DC offset switch OFF - 300 - 100 300 - 300 DC offset switch ON - 500 - 100 500 - 500 mV No load IPPQ Quiescent VPP supply current - - - 10 50 - - INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches OFF IPPQ Quiescent VPP supply current - - - 10 50 - - INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches ON, ISW = 5.0mA ISW Switch output peak current - - - 2.0 1.3 - - A VSIG duty cycle < 0.1% fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50% - 4.0 - - 4.5 - 5.0 - 4.0 - - 4.5 - 5.0 mA - 4.0 - - 4.5 - 5.0 VPP= +40V, All output VNN = -160V switches are VPP= +100V, turning ON VNN = -100V and OFF at VPP= +160V, 50kHz with no load V = -40V mA VPP = +40V, All output VNN = -160V switches are VPP= +100V, turning ON VNN = -100V and OFF at VPP= +160V, 50kHz with no load V = -40V RONS ΔRONS VOS IPP Small signal switch ON-resistance Average VPP supply current ISIG = 5.0mA VPP = +40V, ISIG = 200mA VNN = -160V Ω ISIG = 5.0mA VPP = +100V, ISIG = 200mA VNN = -100V ISIG = 5.0mA VPP = +160V, ISIG = 200mA VNN = -40V NN INN Average VNN supply current - 4.0 - - 4.5 - 5.0 - 4.0 - - 4.5 - 5.0 - 4.0 - - 4.5 - 5.0 NN IDD Average VDD supply current - 8.0 - - 8.0 - 8.0 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 μA All logic inputs are static ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 mA VOUT = VDD -0.7V ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 mA VOUT = 0.7V CIN Logic input capacitance - 10 10 - pF --- - - 10 * See Test Circuits on page 5 Doc.# DSFP-HV2762 C091112 3 Supertex inc. www.supertex.com HV2762 AC Electrical Characteristics (Over recommended operating conditions unless otherwise specified) Sym Parameter tSD Set up time before LE rises tWLE Time width of LE tDO Clock delay time to data out tWCLR Time width of CLR tSU Set up time data to clock tH Hold time data from clock 0OC +25OC +70OC Min Max Min Typ Max Min Max 25 - 25 - - 25 - 56 - 56 - - 56 - 12 - 12 - - 12 - 9.0 40 9.0 - 40 9.0 40 8.0 30 8.0 - 30 8.0 30 55 - 55 - - 55 - 21 - 21 - - 21 - 7.0 - 7.0 - - 7.0 - 5.0 - 5.0 - - 5.0 - 5.0 - 5.0 - - 5.0 - - 8 - - 8 - 8 - 20 - - 20 - 20 Unit ns ns ns ns ns ns Conditions --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V fCLK Clock frequency tR, tF Clock rise and fall times - 50 - - 50 - 50 tON Turn ON time - 5.0 - - 5.0 - 5.0 tOFF Turn OFF time - 5.0 - - 5.0 - 5.0 - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 -33 - -30 - -58 - -58 -60 - -58 - -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) OFF capacitance SW to GND - 14 - 9.0 14 - 14 CSG(ON) ON capacitance SW to GND - 17 - 12 17 - 17 pF VSIG = 0V, f = 1.0MHz +VSPK - - - - 150 - - -VSPK - - - - 150 - - - - - - 150 - - - - - - 150 - - +VSPK - - - - 150 - - -VSPK - - - - 150 - - VPP = +160V, VNN = -40V RLOAD = 50Ω - - - 820 - - - VPP = +40V, VNN = -160V - - - 600 - - - - - - 350 - - - dv/dt Maximum VSIG slew rate KO OFF isolation KCR Switch crosstalk IID +VSPK -VSPK QC Output switch isolation diode current Output voltage spike (per switch) Charge injection (per switch) MHz VDD = 5.0V ns --- μs VSIG = VPP -10V, RLOAD = 10kΩ VPP = +40V, VNN = -160V V/ns VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V dB f = 5.0MHz, 1.0KΩ//15pF load f = 5.0MHz, 50Ω load VPP = +40V, VNN = -160V RLOAD = 50Ω mV pC VPP = +100V, VNN = -100V RLOAD = 50Ω VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V * See Test Circuits on page 5 Doc.# DSFP-HV2762 C091112 4 Supertex inc. www.supertex.com HV2762 Test Circuits VPP -10V VPP -10V ISOL 10kΩ RLOAD VOUT VOUT Open Open RGND RGND RGND VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND Switch Off Leakage per Switch 5V VPP VDD VNN VNN GND 5V TON/TOFF Test Circuit DC Offset Switch ON/OFF VIN =10VPP @5.0MHz VIN =10VPP @5.0MHz VSIG IID VOUT VNN RLOAD VPP VPP VDD VNN VNN GND KO = 20Log 5V VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND KCR = 20Log Output Switch Isolation Diode Current OFF Isolation 50Ω RGND VPP VOUT VIN NC 50Ω RGND RGND 5V VOUT VIN Switch Crosstalk +VSPK ΔVOUT VOUT –VSPK 1000pF VSIG RGND VOUT RLOAD 50Ω RGND 1kΩ VPP VPP VDD VNN VNN GND 5V Q = 1000pF x ΔVOUT Charge Injection Doc.# DSFP-HV2762 C091112 VPP VPP VPP VDD VNN VNN GND 5V Output Voltage Spike 5 Supertex inc. www.supertex.com HV2762 Truth Table D0 D1 L ... D15 D16 - - H - - D23 LE CLR SW0 SW1 SW15 SW16 - - L L OFF - - - - - - - L L ON - - - - L - - - L L - OFF - - - - H - - - L L - ON - - - - - - - - L L - - - - - - - - - - L - - L L - - - - - - - L L - - OFF - - - - H - - L L - - ON - - - - L - L L - - - OFF - - - H - L L - - - ON - - - - - - - - L L - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - L L L - - - - OFF - - - - H L L - - - - ON ... ... ... ... ... X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF ... ... SW23 - Notes: 1. The 24 switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. All 24 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. 4. DOUT is high when data in the register 23 is high. 5. Shift registers clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DN - 1 DN DN + 1 DATA IN DIN 5 0% LE 50% 50% 50% tWLE tSD 50% CLOCK 50% th tSU tDO DATA OUT DOUT VOUT 50% tON tOFF OFF 90% (typ) 1 0% ON CLR Doc.# DSFP-HV2762 C091112 5 0% 5 0% tWCL 6 Supertex inc. www.supertex.com HV2762 Pin Description - 64-Pad LFGA (LA) Pin Name Pin Name Pin Name Pin Name A1 SW22B B7 SW18A F1 VDD J5 SW3B A2 VNN B8 SW17A F2 GND J6 SW4B A3 SW21B B9 SW16A F9 SW11B J7 SW5B A4 SW20B B10 SW14B F10 SW11A J8 SW6B A5 SW19B C1 N/C G1 DIN J9 SW7B A6 SW18B C2 VPP G2 DOUT J10 SW9A A7 SW17B C9 SW14A G9 SW10B K1 SW1A A8 SW16B C10 SW13B G10 VNN K2 VNN A9 SW15B D1 CLR H1 RGND K3 SW2A A10 SW15A D2 RGND H2 VPP K4 SW3A B1 SW23B D9 VNN H9 SW10A K5 SW4A B2 SW23A D10 SW13A H10 SW9B K6 SW5A B3 SW22A E1 LE J1 SW0A K7 SW6A B4 SW21A E2 CLK J2 SW0B K8 SW7A B5 SW20A E9 SW12B J3 SW1B K9 SW8A B6 SW19A E10 SW12A J4 SW2B K10 SW8B Name Pin Name Ball Description - 64-Ball LFGA (LB) Pin Name Pin Name Pin A1 SW22B B7 SW18A F1 VDD J5 SW3B A2 VNN B8 SW17A F2 GND J6 SW4B A3 SW21B B9 SW16A F9 SW11B J7 SW5B A4 SW20B B10 SW14B F10 SW11A J8 SW6B A5 SW19B C1 N/C G1 DIN J9 SW7B A6 SW18B C2 VPP G2 DOUT J10 SW9A A7 SW17B C9 SW14A G9 SW10B K1 SW1A A8 SW16B C10 SW13B G10 VNN K2 VNN A9 SW15B D1 CLR H1 RGND K3 SW2A A10 SW15A D2 RGND H2 VPP K4 SW3A B1 SW23B D9 VNN H9 SW10A K5 SW4A B2 SW23A D10 SW13A H10 SW9B K6 SW5A B3 SW22A E1 LE J1 SW0A K7 SW6A B4 SW21A E2 CLK J2 SW0B K8 SW7A B5 SW20A E9 SW12B J3 SW1B K9 SW8A B6 SW19A E10 SW12A J4 SW2B K10 SW8B Doc.# DSFP-HV2762 C091112 7 Supertex inc. www.supertex.com HV2762 64-Pad LFGA Package Outline (LA) 7.00x7.00mm body, 0.85mm height (max), 0.65mm pitch 10 9 D 8 7 6 5 D1 4 3 2 1 A e Note 1 (Pad A1 Index Area D/4 x E/4) B C D E E1 E F G H J K Top View View B Bottom View Φb Seating Plane A e Side View View B Notes: 1. Pad A1 identifier must be located in the index area indicated. Pad A1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A b D MIN 0.75 0.25 6.925 NOM 0.80 0.30 7.000 MAX 0.85 0.35 7.075 D1 5.85 BSC E 6.925 7.000 7.075 E1 e 5.85 BSC 0.65 BSC Drawings not to scale. Supertex Doc. #: DSPD-64LFGALA, Version A021511. Doc.# DSFP-HV2762 C091112 8 Supertex inc. www.supertex.com HV2762 64-Ball LFGA Package Outline (LB) 7.00x7.00mm body, 1.00mm height (max), 0.65mm pitch 10 9 D 8 7 6 5 D1 4 3 2 1 A e Note 1 (Pad A1 Index Area D/4 x E/4) B C D E E1 E F G H J K e Top View Side View A1 Bottom View View B View A Φb A Seating Plane View A View B Notes: 1. Ball A1 identifier must be located in the index area indicated. Ball A1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 b D MIN 0.90 0.10 0.25 6.925 NOM 0.95 0.15 0.30 7.000 MAX 1.00 0.20 0.35 7.075 D1 5.85 BSC E 6.925 7.000 7.075 E1 e 5.85 BSC 0.65 BSC Drawings not to scale. Supertex Doc. #: DSPD-64LFGALB, Version A021511. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV2762 C091112 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com