HV7350 DATA SHEET (07/24/2014) DOWNLOAD

Supertex inc.
HV7350
Eight-Channel, High Speed, ±60V, ±1.0A,
Ultrasound RTZ Pulser
Features
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General Description
HVCMOS technology for high performance
High density integrated ultrasound transmitter
0 to ±60V output voltage
±1.0A source and sink current in pulse mode
±1.0A source and sink current in RTZ mode
Up to 20MHz operating frequency
Matched delay times
Optional clock re-alignment
3.3V CMOS logic interface and reference
+3.3V low voltage supply for VDD
Built-in linear regulators for floating gate driver
Built-in output drain diodes & bleed resistors
The Supertex HV7350 is an eight channel monolithic high voltage highspeed pulse generator with built-in fast return to zero damping FETs.
This high voltage and high-speed integrated circuit is designed for
portable medical ultrasound image devices.
HV7350 consists of a controller logic interface circuit, level translators,
MOSFET gate drives, and high current power P-channel and N-channel
MOSFETs as the output stage for each channel.
The output peak currents of each channel are guaranteed to be over
±1.0A with up to ±60V pulse swings as well as return-to-zero (RTZ)
mode. The gate drivers for the output MOSFETs are powered by built-in
linear 5.0V regulators referenced to VPP and VNN. This direct coupling
topology of the gate drivers not only saves four floating voltage supplies
or AC coupling capacitors per channel, but also makes the PCB layout
smaller and easier.
Application
►► Portable medical ultrasound imaging
►► Piezoelectric transducer drivers
►► Pulse waveform generator
An input clock pin is available to realign all the logic input control lines to
a master clock. Precise logic timing is always essential in any ultrasound
systems.
Typical Application Circuit
+3.3V
0.1µF
+3.3V
+10 to +60V
1.0µF
VLL
1.0µF
VDD
CPOS
CPF
LRP
REN
+5.0V
OEN
VPF
1.0µF
VPP
LRP
GND
1 of 8 Channels
GND
RGND
P-Driver
PIN1
3.3V Logic
1.0µF
NIN1
Logic
&
Level
Translator
PIN8
+5.0V
VPF
TX1
DMP
VNF
-5.0V
NIN8
CLK
GND
SUB
DAP
GND
GND
VNF
RGND
GND
LRN
LRN
CNEG
CNF
1.0µF
X1
Rb
N-Driver
-5.0V
HVOUT1
VNN
RGND
1.0µF
1.0µF
-10 to -60V
Doc.# DSFP-HV7350
A011314
Supertex inc.
www.supertex.com
HV7350
Ordering Information
Part Number
Package
Packing
HV7350K6-G
56-Lead (8x8) QFN
250/ Tray
HV7350K6-G M937
56-Lead (8x8) QFN
2000/Reel
ESD Sensitive Device
-G denotes a lead (Pb)-free / RoHS compliant package
Pin Configuration
Absolute Maximum Ratings
Parameter
56
Value
VSUB, substrate voltage is GND
1
0V
VLL, Positive logic supply
-0.5V to +5.5V
VDD, Positive logic and level translator supply
-0.5V to +5.5V
CPOS to GND, Positive level translator circuit
-0.5V to +5.5V
CNEG to GND, Negative level translator circuit
+0.5V to -5.5V
(VPP - CPF), Positive gate driver circuit
-0.5V to +5.5V
(CNF - VNN), Negative gate driver circuit
-0.5V to +5.5V
(VPP - VNN) Differential high voltage supply
56-Lead QFN
+130V
VPP, High voltage positive supply
-0.5V to +65V
VNN, High voltage negative supply
+0.5V to -65V
All logic input PINX, NINX, OEN and REN voltages
-0.5V to +5.5V
Operating temperature
-40°C to 125°C
Storage temperature
-65°C to 150°C
(top view)
Package Marking
Package may or may not include the following marks: Si or
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Output Current & Ron
ISC
1.5A
RonP
RonN
13Ω
56-Lead QFN
Typical Thermal Resistance
Package
θja
56-Lead (8x8) QFN
21OC/W
IDMP
6.5Ω
1.5A
Notes:
1.VPP/VNN = +/-60V, VDD = +3.3V; REN = 1
2. ISC is current into 1.0Ω to GND;
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
HV7350K6
LLLLLLLLL
YYWW
AAA CCC
RonDP
RonDN
13Ω
8.0Ω
3. IDMP is current from +/-30V connected to TX pin.
4. Max pulse width for current measurement on TX pin is 100ns.
Power-Up Sequence
Power-Down Sequence
Step
Description
Step
Description
1
VLL with logic signal low
1
All logic signals go to low
2
VDD
2
VPP and VNN
3
REN = 1 (external supplies on)
3
REN = 0 (external supplies off)
4
VPP and VNN
4
VDD
5
Logic control signals active
5
VLL
Note:
Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequence is only recommended in
order to minimize possible inrush current.
Doc.# DSFP-HV7350
A011314
2
Supertex inc.
www.supertex.com
HV7350
Operating Supply Voltages and Current (Eight Active Channels)
(Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +3.3V, VPP = +60V ,VNN = -60V, VCLK = +3.3V, TA = 25°C)
Sym
VDD
Parameter
Min
Typ
Max
VDD voltage supply
2.97
3.30
5.20
V
---
2.30
2.60
2.80
V
---
2.50
3.30
5.00
V
---
1.30
1.55
1.70
V
---
UVLODD VDD UVLO
VLL
Logic voltage reference
UVLOLL VLL UVLO
Units Conditions
VPP
Positive high voltage supply
+10
-
+60
V
---
VNN
Negative high voltage supply
-60
-
-10
V
---
ILLQ
VLL current
-
8.0
-
IDDQ
VDD current
-
1.0
-
IPPQ
VPP current
-
5.0
10
μA
OEN = REN = 0
INNQ
VNN current
-
5.0
10
ILLEN
VLL current
-
13
20
IDDEN
VDD current
-
480
700
IPPEN
VPP current
-
220
350
μA
OEN = REN = 1
5.0ms after f = 0MHz
INNEN
VNN current
-
300
400
IDDCW
VDD current
-
2.3
-
IPPCW
VPP current
-
80
-
INNCW
VNN current
-
80
-
ILL,CLK
VLL current
-
33
-
mA
f = 5.0MHz, Continuous, no loads,
for calculation reference only.
μA
fCLK = 10MHz, PIN = NIN = 0
Electrical Characteristics
(Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +3.3V, VPP = +60V ,VNN = -60V, VCLK = +3.3V, TA = 25°C)
Pulser P-Channel MOSFET
Sym
Parameter
Min
Typ
Max
Units Conditions
IOUT
Output saturation current
1.0
1.5
-
A
---
RON
Channel resistance
-
13.2
-
Ω
ISD = 100mA
Parameter
Min
Typ
Max
IOUT
Output saturation current
1.0
1.5
-
A
---
RON
Channel resistance
-
8.0
-
Ω
ISD = 100mA
Parameter
Min
Typ
Max
IOUT
Output saturation current
1.0
1.5
-
A
---
RON
Channel resistance
-
13
-
Ω
ISD = 100mA
Parameter
Min
Typ
Max
IOUT
Output saturation current
1.0
1.5
-
A
---
RON
Channel resistance
-
9.0
-
Ω
ISD = 100mA
Pulser N-Channel MOSFET
Sym
Units Conditions
Damping P-Channel MOSFET
Sym
Units Conditions
Damping N-Channel MOSFET
Sym
Doc.# DSFP-HV7350
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Units Conditions
Supertex inc.
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HV7350
Logic Inputs
Sym
Parameter
Min
Typ
Max
Units Conditions
VIH
Input logic high voltage
0.7 • VLL
-
VLL
V
VIL
Input logic low voltage
0
-
0.3 • VLL
V
VIH
Input logic high voltage
0.8 • VLL
-
VLL
V
VIL
Input logic low voltage
0
-
0.2 • VLL
V
IIH
Input logic high current
-
-
10
μA
---
IIL
Input logic low current
-10
-
-
μA
---
CIN
Input logic capacitance
-
-
5.0
pF
---
Min
Typ
Max
12
17
25
kΩ
---
-
-
50
mW
---
VLL = 2.5 to 3.3V
VLL = 5.0V
MOSFET Drain Bleed Resistor
Sym
Parameter
RB1~8
Output Bleed Resistance
PRB1~8
Bleed Resistors Power Limit
Units Conditions
AC Electrical Characteristics
(Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +3.3V, VPP = +60V ,VNN = -60V, VCLK = +3.3V, TA = 25°C)
Sym
Parameter
Min
Typ
Max
Units Conditions
tr
Output rise time
-
30
-
ns
tf
Output fall time
-
30
-
ns
tEN
Enable time
-
300
500
μs
tDIS
Disable time
-
2.8
10
μs
td1
Delay time on PINX rise
-
12
-
td2
Delay time on NINX rise
-
12
-
td3
Delay time on damping rise
-
12
-
td4
Delay time on damping fall
-
12
-
tdc
Delay time on CLK rise
-
9.0
-
Delay time matching
-
±3.0
-
ns
P to N, channel to channel
tj
Delay jitter on rise or fall
-
TBD
-
ps
VPP/VNN = +/-25V, input tr 50% to HVOUT
tr or tf 50%, with 330pF//2.5kΩ load
trr
RTZ FETs drain diode trr
-
25
-
ns
IF = 1.0A, IR = 1.0A, RL = 10Ω
10
220
-
MHz
---
-
0.5
5.0
ns
---
ΔtDELAY
fCLK
tRC, tFC
Re-timing clock frequency
Re-timing clock rise & fall times
ns
330pF//2.5kΩ load
10 - 90%
Cap value see page 1 diagram.
OEN = REN
1.0Ω resistor load, D%<1%
(See timing diagram)
50% inputs to 50% TX current
tsu
Set-up time, PIN/NIN to CLK
2.0
-
-
ns
---
tH
Hold time, CLK to PIN/NIN
1.0
-
-
ns
---
tCLK_LO
Clock time low
2.0
-
100
ns
tCLK_HI
Clock time high
2.0
-
100
ns
-
2.0
-
ns
150
300
800
ns
tCLK_REC
Clock recognition time
tCLK_RLS
Clock release time
fOUT
Output frequency range
-
-
20
MHz
HD2
Second harmonic distortion
-
-40
-
dB
COSS
Output capacitance
-
50
-
pF
Doc.# DSFP-HV7350
A011314
4
CLK input must have at least one
pulse before PIN and NIN inputs are
not zero. Be sure to return inputs to
zero before stopping clock.
100Ω resistor load
VDS = 25V, f = 1.0MHz , of TX pin total
Supertex inc.
www.supertex.com
HV7350
Truth Table
Logic Inputs
TXn Output
OEN
CLK
PINX
NINX
VPP
VNN
RGND
1
VLL
0
0
OFF
OFF
ON
1
VLL
1
0
ON
OFF
OFF
1
VLL
0
1
OFF
ON
OFF
1
VLL
1
1
OFF
OFF
OFF
1
0
0
OFF
OFF
ON
1
1
0
ON
OFF
OFF
1
0
1
OFF
ON
OFF
1
1
1
OFF
OFF
OFF
X
X
OFF
OFF
OFF
0
X
Note
Asynchronous Mode
Output change on PIN/NIN
Synchronous Mode
Output change at retiming
clock(CLK) rising edge,
registered by PIN/NIN
Disabled
Switching Time Diagram
CLK
CLK
PINn
(NINn = 0)
NINn
(PINn = 0)
50%
td1
50%
td4
IOUT
td3
td2
50%
TXn
0A
0A
TXn
50%
Asynchronous Mode
IOUT
CLK
CLK
PINn
(NINn = 0)
NINn
(PINn = 0)
tdc
tdc
tdc
tdc
IOUT
50%
TXn
TXn
0A
0A
50%
Synchronous Mode
IOUT
Doc.# DSFP-HV7350
A011314
5
Supertex inc.
www.supertex.com
HV7350
Pin Description
Pin
Name
Description
1
PIN2
Input logic control of high voltage output P-FET for channel 2, Hi = on, Low = off. (see logic table)
2
NIN2
Input logic control of high voltage output N-FET for channel 2, Hi = on, Low = off. (see logic table)
3
PIN3
Input logic control of high voltage output P-FET for channel 3, Hi = on, Low = off. (see logic table)
4
NIN3
Input logic control of high voltage output N-FET for channel 3, Hi = on, Low = off. (see logic table)
5
PIN4
Input logic control of high voltage output P-FET for channel 4, Hi = on, Low = off. (see logic table)
6
NIN4
Input logic control of high voltage output N-FET for channel 4, Hi = on, Low = off. (see logic table)
7
OEN
Output enable Hi = on, Low = off. See logic truth table
8
REN
Built-in positive and negative 5V voltage regulators enable. Hi = on, Low = off. If REN = 0, external floating 5V power supplies may be supplied across CPF, CNF CPOS and CNEG capacitors
9
PIN5
Input logic control of high voltage output P-FET for channel 5, Hi = on, Low = off. (see logic table)
10
NIN5
Input logic control of high voltage output N-FET for channel 5, Hi = on, Low = off. (see logic table)
11
PIN6
Input logic control of high voltage output P-FET for channel 6, Hi = on, Low = off. (see logic table)
12
NIN6
Input logic control of high voltage output N-FET for channel 6, Hi = on, Low = off. (see logic table)
13
PIN7
Input logic control of high voltage output P-FET for channel 7, Hi = on, Low = off. (see logic table)
14
NIN7
Input logic control of high voltage output N-FET for channel 7, Hi = on, Low = off. (see logic table)
15
PIN8
Input logic control of high voltage output P-FET for channel 8, Hi = on, Low = off. (see logic table)
16
NIN8
Input logic control of high voltage output N-FET for channel 8, Hi = on, Low = off. (see logic table)
17
VLL
Logic supply voltage and reference input (+3.3V)
18
GND
Logic and circuit return ground (0V)
19
VDD
Positive voltage power supply (+3.3V)
20
VPP
21
VPP
22
VPP
23
CPF
Built-in linear voltage VPF regulator output decoupling capacitor pin, 1uF from VPP to CPF per
each
24
CNF
Built-in linear voltage VNF regulator output decoupling capacitor pin, 1uF from CNF to VNN per
each
25
VNN
26
VNN
27
VNN
28
TX8
29
RGND
30
TX7
31
RGND
32
TX6
Doc.# DSFP-HV7350
A011314
Positive high voltage power supply (+10 to +60V)
Negative high voltage power supply (-10 to -60V)
TX pulser channel 8 output
Damping ground and bleed resistors common return ground
TX pulser channel 7 output
Damping ground and bleed resistors common return ground
TX pulser channel 6 output
6
Supertex inc.
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HV7350
Pin Description (cont.)
Pin
Name
Description
33
RGND
Damping ground and bleed resistors common return ground
34
TX5
35
CNEG
Built-in linear voltage -5V regulator output decoupling capacitor pin, 1.0uF from CNEG to GND
36
CPOS
Built-in linear voltage +5V regulator output decoupling capacitor pin, 1.0uF from CPOS to GND
37
TX4
38
RGND
39
TX3
40
RGND
41
TX2
42
RGND
43
TX1
44
VNN
45
VNN
46
VNN
47
CNF
Built-in linear voltage VNF regulator output decoupling capacitor pin, 1uF from CNF to VNN per
each
48
CPF
Built-in linear voltage VPF regulator output decoupling capacitor pin, 1uF from VPP to CPF per
each
49
VPP
50
VPP
51
VPP
52
VDD
Positive voltage power supply (+3.3V)
53
GND
Logic and circuit return ground (0V)
54
CLK
Re-timing register clock input. Connect to VLL to disable the re-timing function
55
PIN1
Input logic control of high voltage output P-FET for channel 1, Hi = on, Low = off. (see logic table)
56
NIN1
Input logic control of high voltage output N-FET for channel 1, Hi = on, Low = off. (see logic table)
VSUB (Thermal Pad)
Doc.# DSFP-HV7350
A011314
TX pulser channel 5 output
TX pulser channel 4 output
Damping ground and bleed resistors common return ground
TX pulser channel 3 output
Damping ground and bleed resistors common return ground
TX pulser channel 2 output
Damping ground and bleed resistors common return ground
TX pulser channel 1 output
Negative high voltage power supply (-10 to -60V)
Positive high voltage power supply (+10 to +60V)
Substrate bottom is internally connected to the central thermal pad on the bottom of package. It
must be connected to GND (0V) externally
7
Supertex inc.
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HV7350
56-Lead QFN Package Outline (K6)
8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch
D2
D
56
1
56
1
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
e
E
E2
b
View B
Top View
Bottom View
Note 3
θ
A
A3
L
Seating
Plane
Side View
A1
L1
Note 2
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
Dimension
(mm)
A
A1
MIN
0.80
0.00
NOM
0.90
0.02
MAX
1.00
0.05
A3
0.20
REF
b
D
D2
E
E2
0.18
7.85*
2.75
7.85*
2.75
0.25
8.00
5.70
8.00
5.70
0.30
8.15*
6.70
8.15*
6.70
†
e
†
0.50
BSC
L
L1
θ
0.30
0.00
0O
0.40
-
-
0.50
0.15
14O
JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings are not to scale.
Supertex Doc.#: DSPD-56QFNK68X8P050, Version A031010.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV7350
A011314
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1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
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