Data Sheet TLE 6230 GP Smart Octal Low-Side Switch Supply voltage Drain source clamping voltage On resistance Output current (all outp.ON equal) (individually) Features Product Summary • Short Circuit Protection • Overtemperature Protection • Overvoltage Protection • 16 bit Serial Data Input and Diagnostic Output (2 bit/ch. acc. SPI protocol) • Direct Parallel Control of Four Channels for PWM Applications • Parallel Inputs High or Low Active Programmable • General Fault Flag • Low Quiescent Current • Compatible with 3,3 V Micro Controllers • Electostatic Discharge (ESD) Protection • Green Product (RoHS compliant) • AEC Qualified VS VDS(AZ)max RON ID(NOM) 4.5 – 5.5 V 55 V 0.75 Ω 500 mA 1 A PG-DSO 36 Application • µC Compatible Power Switch for 12 V and 24V Applications • Switch for Automotive and Industrial Systems • Solenoids, Relays and Resistive Loads • Robotic Controls General description Octal Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and eight open drain DMOS output stages. The TLE 6230 GP is protected by embedded protection functions and designed for automotive and industrial applications. The output stages are controlled via an SPI Interface. Additionally four channels can be controlled direct in parallel for PWM applications. Therefore the TLE 6230 GP is particularly suitable for engine management and powertrain systems. PRG GND VS RESET FAULT VS VBB Protection Functions IN1 IN2 as Ch. 1 IN3 as Ch. 1 IN4 as Ch. 1 LOGIC Output Stage 16 SCLK SI CS 4 1 8 Serial Interface SPI OUT1 Output Control Buffer 8 OUT8 SO GND V2.3 Page 1 18. Nov. 2009 Data Sheet TLE 6230 GP Block Diagram Detailed Block Diagram RESET FAULT VS Channel 1 Normal function GND VS SCB/Overload PRG Open load short to ground IN1 & Output Stage OUT1 IN2 IN3 IN4 SO SI SCLK & Channel 2 OUT2 & Channel 3 OUT3 & Channel 4 OUT4 Channel 5 OUT5 Channel 6 OUT6 Channel 7 OUT7 Channel 8 OUT8 SPI Interface 16 bit CS GND V2.3 Page 2 18. Nov. 2009 Data Sheet TLE 6230 GP Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol GND NC NC OUT1 OUT2 IN1 IN2 VS RESET CS PRG IN3 IN4 OUT3 OUT4 NC NC GND GND NC NC OUT5 OUT6 NC NC FAULT SO SCLK SI NC NC OUT7 OUT8 NC NC GND Pin Configuration (Top view) Function Ground not connected not connected Power Output Channel 1 Power Output Channel 2 Input Channel 1 Input Channel 2 Supply Voltage Reset Chip Select Program (inputs high or low-active) Input Channel 3 Input Channel 4 Power Output Channel 3 Power Output Channel 4 not connected not connected Ground Ground not connected not connected Power Output Channel 5 Power Output Channel 6 not connected not connected General Fault Flag Serial Data Output Serial Clock Serial Data Input not connected not connected Power Output Channel 7 Power Output Channel 8 not connected not connected Ground GND NC NC OUT1 OUT2 IN1 IN2 VS RESET CS PRG IN3 IN4 OUT3 OUT4 NC NC GND 1• 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 GND 35 NC 34 NC 33 OUT8 32 OUT7 31 NC 30 NC 29 SI 28 SCLK 27 SO 26 FAULT 25 NC 24 NC 23 OUT6 22 OUT5 21 NC 20 NC 19 GND Power SO 36 Heat Slug internally connected to ground pins V2.3 Page 3 18. Nov. 2009 Data Sheet TLE 6230 GP Maximum Ratings for Tj = – 40°C to 150°C Parameter Supply Voltage Symbol VS Continuous Drain Source Voltage (OUT1...OUT8) VDS Input Voltage, All Inputs and Data Lines VIN Values -0.3 ... + 7 Unit V 40 V - 0.3 ... + 7 V 2) Load Dump Protection VLoad Dump = UP+US; UP=13.5 V With Automotive Relay Load RL = 70 Ω RI1)=2 Ω; td=400ms; IN = low or high With RL= 24 Ω; RI=2 Ω; td=400ms; IN = high or low VLoad Dump Operating Temperature Range Storage Temperature Range Tj Tstg - 40 ... + 150 - 55 ... + 150 °C Output Current per Channel (see el. characteristics) ID(lim) ID(lim) min A Output Current per Channel @ TA = 25°C (All 8 Channels ON; Mounted on PCB ) 3) ID 500 mA V 80 52 Output Clamping Energy (single pulse) ID = 0.5 A EAS 50 mJ Power Dissipation (mounted on PCB) @ TA = 25°C Ptot 3.3 W Electrostatic Discharge Voltage (Human Body Model) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 – 1993 Output 1-8 Pins All other Pins VESD VESD 2000 2000 V V DIN Humidity Category, DIN 40 040 E IEC Climatic Category, DIN IEC 68-1 40/150/56 Thermal Resistance junction - case junction - ambient @ min. footprint junction - ambient @ 6 cm2 cooling area with heat pipes RthJC RthJA 5 50 38 K/W PCB with heat pipes, backside 6 cm2 cooling area Minimum footprint 1) RI=internal resistance of the load dump test pulse generator LD200 VLoadDump is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839. 3) Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 °C the output current has to be calculated using RthJA according mounting conditions. 2) V2.3 Page 4 18. Nov. 2009 Data Sheet TLE 6230 GP Electrical Characteristics Parameter and Conditions VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) Symbol Values min Unit typ max 1. Power Supply, Reset Supply Voltage4 Supply Current (outputs ON) VS 4.5 -- 5.5 IS(ON) -- 1 2 mA IS(OFF) -- 1 2 mA tReset,min 10 -- -- µs TJ = 25°C TJ = 150°C RDS(ON) --- 0.8 -- 1 1.7 Ω Output OFF VDS(AZ) 40 -- 55 V ID(lim) 1 1.5 2 A ID(lkg) -- -- 5 µA 5 Supply Current (outputs OFF) 5 Minimum Reset Duration V 2. Power Outputs ON Resistance VS = 5 V; ID = 500 mA Output Clamping Voltage Current Limit Output Leakage Current VReset = L Vbb=12V Turn-On Time ID = 0.5 A, resistive load tON -- 8 12 µs Turn-Off Time ID = 0.5 A, resistive load tOFF -- 6 10 µs Input Low Voltage VINL - 0.3 -- 1.0 V Input High Voltage VINH 2.0 -- -- V Input Voltage Hysteresis VINHys 50 100 200 mV Input Pull Down/Up Current (IN1 ... IN4) IIN(1..4) 20 50 100 µA PRG, Reset Pull Up Current IIN(PRG,Res) 20 50 100 µA Input Pull Down Current (SI, SCLK) IIN(SI,SCLK) 10 20 50 µA Input Pull Up Current ( CS ) IIN(CS) 10 20 50 µA -- V 3. Digital Inputs 4. Digital Outputs (SO, FAULT ) SO High State Output Voltage ISOH = 2 mA VSOH ISOL = 2.5 mA VSOL -- -- 0.4 V Output Tri-state Leakage Current CS = H, 0 ≤ VSO ≤ VS FAULT Output Low Voltage IFAULT = 1.6 mA ISOlkg -10 0 10 µA VFAULTL -- -- 0.4 V SO Low State Output Voltage VS - 0.4 -- 4 For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched off. This undervoltage reset gets active at VS = 3V (typ. value) and is guaranteed by design. 5 For Reset = H. V2.3 Page 5 18. Nov. 2009 Data Sheet TLE 6230 GP Electrical Characteristics cont. Parameter and Conditions Symbol VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) Values Unit min typ max 5. Diagnostic Functions Open Load Detection Voltage VDS(OL) VS -2.5 VS -2 VS -1.3 V Output Pull Down Current IPD(OL) 50 90 150 µA Fault Delay Time td(fault) 50 100 200 µs Short to Ground Detection Voltage VDS(SHG) Short to Ground Detection Current ISHG -50 -100 -150 µA ID(lim) 1...8 1 1.5 2 A Tth(sd) Thys 170 -- -10 200 -- °C K Serial Clock Frequency (depending on SO load) fSCK DC -- 5 MHz Serial Clock Period (1/fclk) tp(SCK) 200 -- -- ns Serial Clock High Time tSCKH 50 -- -- ns Serial Clock Low Time tSCKL 50 -- -- ns Enable Lead Time (falling edge of CS to rising edge of CLK) tlead 250 -- -- ns Enable Lag Time (falling edge of CLK to rising edge of CS ) tlag 250 --- -- ns Data Setup Time (required time SI to falling of CLK) tSU 20 -- -- ns Data Hold Time (falling edge of CLK to SI) tH 20 -- -- ns tDIS -- -- 150 ns tdt 200 -- -- ns tvalid ---- 110 120 150 160 170 200 ns Current Limitation; Overload Threshold Current Overtemperature Shutdown Threshold Hysteresis6 6 VS –3.3 VS -2.9 VS -2.5 V 6. SPI-Timing 6 Disable Time @ CL = 50 pF 7 Transfer Delay Time ( CS high time between two accesses) Data Valid Time 6 7 CL = 50 pF6 CL = 100 pF6 CL = 220 pF6 This parameter will not be tested but guaranteed by design This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time td(fault)max = 200µs. V2.3 Page 6 18. Nov. 2009 Data Sheet TLE 6230 GP Functional Description The TLE 6230 GP is an octal-low-side power switch which provides a serial peripheral interface (SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The power transistors are protected against short to VBB, overload, overtemperature and against overvoltage by an active zener clamp. The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (SO). Circuit Description Output Stage Control Each output is independently controlled by an output latch and a common reset line, which disables all eight outputs. Serial data input (SI) is read on the falling edge of the serial clock. A logic high input data bit turns the respective output channel ON, a logic low data bit turns it OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition of CS transfers the serial data input bits to the output buffer. Special conditions for Channel 1 to 4: In addition to the serial control of the outputs it is possible to control channel 1 to channel 4 directly in parallel for PWM applications. These inputs are high or low active (programmable via PRG pin) and ANDed with the SPI control bit. The table shows the AND-operation of the parallel IN 1 - 4 input pin (here active high) and the corresponding 0 SPI bit. For an application where the parallel input is 0 always "ON", it is possible to switch the channel 1 OFF via the SPI bit, e.g. for diagnosis in OFF-state. 1 SPI-Bit 0 - 3 0 1 0 1 OUT 1 - 4 OFF OFF OFF ON ⇒ SPI Priority for OFF-state Operation with parallel inputs: Set SPI bits to logic high. Operation via SPI: Connect parallel inputs to logic high (if programmed to active high). PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 4 are high active PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active. If the parallel input pins are not connected (independent of high or low activity) it is guaranteed that the channels 1 to 4 are switched OFF. PRG pin itself is internally pulled up when it is not connected. V2.3 Page 7 18. Nov. 2009 Data Sheet TLE 6230 GP Power Transistor Protection Functions8) Each of the eight output stages has its own zener clamp, which causes a voltage limitation at the power transistor when solenoid loads are switched off. The outputs are provided with a current limitation set to a minimum of 1 A. The continuous current for each channel is 500 mA (all channels ON). Each output is protected by embedded protection functions. In the event of an overload or short to supply, the current is internally limited and the corresponding bit combination is set (early warning). If this operation leads to an overtemperature condition, a second protection level (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shutdown with restart) to prevent critical chip temperatures. SPI Signal Description CS - Chip Select. The system microcontroller selects the TLE 6230 GP by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice versa. CS High to Low transition: - diagnostic status information is transferred from the power outputs into the shift register. - serial input data can be clocked in from then on - SO changes from high impedance state to logic high or low state corresponding to the SO bits CS Low to High transition: - transfer of SI bits from shift register into output buffers - reset of diagnosis register To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition of CS . When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6230 GP. The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS makes any transition. The number of clock pulses will be counted during a chip select cycle. The received data will only be accepted, if exactly 16 clock pulses were counted during CS is active. SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the output stages. The input data consists of two bytes - a "control byte” followed by a "data byte". The control byte contains the information as to whether the data byte will be accepted or ignored (see diagnostics section). The data byte contains the input information for the eight channels. A logic 8) The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or permanently V2.3 Page 8 18. Nov. 2009 Data Sheet TLE 6230 GP high level at this pin (within the data byte) will switch on the power switch, provided that the corresponding parallel input is also switched on (AND-operation for channel 1 to 4). SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the rising edge of SCLK. RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs OFF. An internal pull-up structure is provided on chip. Diagnostics FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transi- tion as soon as an error occurs for any one of the eight channels. This fault indication can be used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called after this fault indication. This saves processor time compared to a cyclic reading of the SO information. As soon as a fault occurs, the fault information is latched into the diagnosis register. A new error will over-write the old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. The rising edge of CS will reset all error registers. Diagnostic Serial Data Out SO 15 14 Ch.8 HH HL LH LL 13 12 Ch.7 11 10 9 8 Ch.6 Ch.5 - ---- Normal function Overload, Shorted Load or Overtemperature Open Load Shorted to Ground Figure 1: Two bits per channel diagnostic feedback There are two diagnostic bits per channel configured as shown in Figure 1. Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function. Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemperature condition. Open load: An open load condition is detected when the drain voltage decreases below 3 V (typ.). LH bit combination is set. Short Circuit to GND: If a drain to ground short circuit exists and the drain to ground current exceeds 100 µA, short to ground is detected and the LL bit combination is set. V2.3 Page 9 18. Nov. 2009 Data Sheet TLE 6230 GP A definite distinction between open load and short to ground is guaranteed by design. The standard way of obtaining diagnostic information is as follows: Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs tosettle. Clock in the identical serial information once again - during this process the data coming out at SO contains the bit combinations representing the diagnosis conditions as described in figure 1. By means of the control byte it is possible either to: a) control the eight outputs according to the data byte, as well as being able to read the diagnostic information or b) purely get diagnostic information without changing the state of the outputs. a) Serial Control of Outputs HHHHHHHH LHLHHLLL : Serial input information 1442443 14 4244 3 Control Byte Data Byte Control byte is set to FFhex: Data byte will be accepted. The outputs will be switched ON or OFF according to the information of the data byte and the parallel inputs (Channel 1 to 4 because of AND operation). All other control words except the one for 'Diagnosis Only = 00hex' will also be accepted as a valid control word and the data will be accepted. Example: HLLHLHLH DDDDDDDD: Outputs will switch according to the data bits. b) Diagnosis Only LLLLLLLL XXXXXXXX : Serial input information 14 4244 3 144244 3 Control Byte Data Byte Control byte is set to 00hex: Data byte will be ignored. Diagnostic information can be read out at any time with no change of the switching conditions. Only 00hex means 'Diagnosis Only'. V2.3 Page 10 18. Nov. 2009 Data Sheet TLE 6230 GP Timing Diagrams CS SCLK C SI O N T R O L Byte 7 6 5 4 13 12 11 10 9 8 7 6 5 4 3 2 1 2 1 MSB 15 SO 0 LSB 14 3 0 Figure 2: Serial Interface Figure 3: Input Timing Diagram CS 0.7VS tdt 0.2 VS tlag tSCKH SCLK tlead 0.7VS 0.2VS tSCKL tSU tH 0.7VS SI 0.2VS Figure 4: 0.7 VS SCLK CS 0.2 VS tvalid tDis SO 0.7 VS SO 0.2 VS SO 0.7 VS 0.2 VS SO Valid Time Waveforms V2.3 Enable and Disable Time Waveforms Page 11 18. Nov. 2009 Data Sheet TLE 6230 GP VIN t tOFF tON VDS 80% 20% t Figure 5: Power Outputs Timing is valid for resistive load with parallel and serial control. Rising edge of chip select initiates the switching Application Circuits VBB VS = 5V C 10k VS PRG OUT1 FAULT OUT2 RESET IN1 µC e.g. C167 V2.3 IN2 IN3 IN4 MTSR SI MRST SO CLK CLK P xy CS TLE 6230 GP OUT8 GND Page 12 18. Nov. 2009 Data Sheet TLE 6230 GP Typical electrical Characteristics Drain-Source on-resistance RDS(ON) = f (Tj) ; Vs = 5V Channel 1-8 Typical Drain- Source ON-Resistance 1,5 1,4 1,3 RDS(ON) [Ohm] 1,2 1,1 1 0,9 0,8 0,7 0,6 0,5 0,4 -50 -25 0 25 50 75 100 125 150 175 Tj[°C] Figure 6 : Typical ON Resistance versus Junction-Temperature Channel 1-8 Output Clamping Voltage VDS(AZ) = f (Tj) ; Vs = 5V Channel 1-8 Typical Clamping Voltage 45 VDS(AZ) [V] 44 43 42 41 -50 -25 0 25 50 75 100 125 150 175 Tj[°C] Figure 7 : Typical Clamp Voltage versus Junction-Temperature Channel 1-8 V2.3 Page 13 18. Nov. 2009 Data Sheet TLE 6230 GP Maximum single clamp Energy TLE 6230, single Clamp, linear Current Ramp Maximum Energy Rating @ Tj=150°C 300 250 200 150 100 50 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 Peak current [A] Maximum Clamp Energy (single event) versus Peak Current Figure 8 : Channel 1-8 Parallel SPI Configuration Injector 1 4 P x.1-4 MTSR 4 PW M Channels SI SO CLK CS CS MRST CLK P x.y 4 SI SO C167 CLK P x.y Injector 3 TLE 6220 GP Quad Injector 4 4 PW M Channels P x.1-4 µC Injector 2 CS TLE 6230 GP Octal Engine Management Application TLE 6230 GP in combination with TLE 6240 GP (16-fold switch) for relays and general purpose loads and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the numerous loads to be driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16 can be controlled direct in parallel for PWM applications. 8 8 PW M Channels P x.1-8 P x.y V2.3 SI SO CLK CS TLE 6240 GP 16-fold Page 14 18. Nov. 2009 Data Sheet TLE 6230 GP Package and Ordering Code (all dimensions in mm) PG-DSO 36 TLE 6230 GP V2.3 Page 15 18. Nov. 2009 Data Sheet TLE 6230 GP Edition 2008-04-17 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. V2.3 Page 16 18. Nov. 2009