INFINEON TLE6240GP_10

TLE6240GP
Smart 16-Channel Low-Side Switch
coreFLEX
Data Sheet
Rev.3.3, 2010-02-15
Automotive Power
TLE6240GP
Smart 16-Channel Low-Side Switch
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
2.1
2.2
2.3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
4.1
4.2
4.3
Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
5.1
5.2
5.3
5.3.1
5.4
5.5
Electrical and Functional Description of Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Functions and FAULT-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
13
14
17
18
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.5.1
6.1.5.2
6.1.5.3
6.1.5.4
6.1.5.5
6.1.5.6
6.2
6.2.1
Control of the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Stage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Control and PRG - Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control of the Outputs: SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control- and Data Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Byte - Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Byte No.1 and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Byte No. 2 and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Byte No. 3 and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Byte No. 4 and 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Byte No. 5 and 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example for an access to channel 1 to 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis Read-out options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
21
21
23
24
24
25
26
26
27
28
28
29
7
7.1
7.2
7.3
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Engine Management Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
32
33
34
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Sheet
2
5
5
5
6
V3.3, 2010-02-15
Smart 16-Channel Low-Side Switch
coreFLEX
1
TLE6240GP
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
Short Circuit Protection
Overtemperature Protection
Overvoltage Protection
16 bit Serial Data Input and Diagnostic Output
(2 bit/channel for Open Load- and Short to GND detection)
Direct Parallel Control of eight channels for PWM Applications
Parallel Inputs High or Low Active programmable
General Fault Flag
Low Quiescent Current
Compatible with 3 V Microcontrollers
Electrostatic discharge (ESD) Protection
Green Product (RoHS compliant)
AEC Qualified
PG-DSO-36
Applications
•
•
Automotive and Industrial Systems
Solenoids, Relays and Resistive Loads
General Description
16-fold Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and 16 open
drain DMOS output stages. The TLE6240GP is protected by embedded protection functions and designed for
automotive and industrial applications. The output stages are controlled via SPI Interface. Additionally 8 channels
can be controlled direct in parallel for PWM applications. Therefore the TLE6240GP is particularly suitable for
engine management and powertrain systems, safety and body applications.
Type
Package
Marking
TLE6240GP
PG-DSO-36
TLE6240GP
Data Sheet
3
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Overview
Product Summary
Parameter
Symbol
Value
Unit
Supply voltage
VS
VDS(AZ)max
RON1-8 (max @ 150°C)
RON10,11,14,15 (max @ 150°C)
RON9,12,13,16 (max @ 150°C)
ID
ID
ID(lim)_min
ID(lim)_min
4.5 … 5.5
V
45 .... 60
V
2.2
Ω
0.7
Ω
0.6
Ω
0.5
A
1
A
1
A
3
A
Drain source clamping voltage
On resistance
Nominal Output current (channel 1 - 8)
Nominal Output current (channel 9 - 16)
Minimum Output current Limit (channel 1 - 8)
Minimum Output current Limit (channel 9 - 16)
Block Diagram
Figure 1
Data Sheet
Application Block Diagram
4
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Block Diagram
2
Block Diagram
2.1
Detailed Block Diagram
Figure 2
Detailed Block Diagram
2.2
Description of Block Diagram
All 16 channels can be controlled via the serial interface (SPI). In addition to the serial control it is possible to
control channel 1 to 4 and 9 to 12 direct in parallel with a separate input pin. The parallel input signal is either OR
- operated or AND - operated with the respective SPI data bit. This boolean operation can be programmed via SPI
control byte (see Chapter 5). The SPI interface also performs a diagnostic information for each channel.
Data Sheet
5
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Block Diagram
2.3
Terms
VBatt
PG-DSO-36
IOUT9
VOUT9
IOUT10
V OUT10
IOUT1
VOUT1
IOUT2
VOUT2
IIN1
V IN1
IIN2
VIN 2
IS
VS
IRESET
VRESET
ICS
VCS
IPRG
VPRG
IIN3
VIN3
IIN4
VIN4
I OUT3
VOUT3
IOUT4
VOUT4
VOUT11
IOUT11
IOUT12
VOUT12
1
GND
2
OUT9
3
4
OUT10
OUT1
GND
36
IOUT16
OUT16
35
IOUT15
OUT15
34
IOUT8
OUT8
33
I OUT7
5
OUT2
OUT7
32
IIN12
6
IN1
IN12
31
IIN11
7
IN2
IN11
30
ISI
SI
29
ISCLK
SCLK
28
I SO
SO
27
FAULT
26
IIN10
IN10
25
IIN9
8
VS
9
RESET
10
CS
11
PRG
12
IN3
VOUT4
VIN4
IN4
IN9
24
I OUT6
14
OUT3
OUT6
23
IOUT5
15
OUT4
OUT5
22
IOUT14
16
OUT11
OUT14
21
IOUT13
17
OUT12
OUT13
20
18
GND
GND
19
VOUT8
VOUT7
V IN12
V IN11
VSI
VSCLK
VSO
I FAULT
13
V OUT16
V OUT15
V FAULT
VIN10
VIN9
VOUT6
VOUT5
V OUT14
V OUT13
DSO-36(Power )_terms_TLE6240 .vsd
Figure 3
Data Sheet
Terms for Voltages and Currents
6
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
PG-DSO-36
GND
1
36
OUT9
2
35 OUT16
OUT10 3
34 OUT15
GND
OUT1
4
33
OUT8
OUT2
5
32
OUT7
IN1
6
31
IN12
IN2
7
30
IN11
VS
8
29
SI
RESET 9
28
SCLK
CS
10
27
SO
PRG
11
26
FAULT
IN3
12
25
IN10
IN4
13
24
IN9
OUT3
14
23
OUT6
OUT4
15
22
OUT5
OUT11 16
21
OUT14
OUT12 17
20
OUT13
18
19
GND
GND
DSO-36(Power )_TLE6240.vsd
Figure 4
Pin Configuration (top view)
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1
GND
Ground
2
OUT9
Power Output Channel 9
3
OUT10
Power Output Channel 10
4
OUT1
Power Output Channel 1
5
OUT2
Power Output Channel 2
6
IN1
Input Channel 1
7
IN2
Input Channel 2
8
VS
Supply Voltage
9
RESET
Reset
10
CS
Chip Select
Data Sheet
7
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Pin Configuration
Pin
Symbol
Function
11
PRG
Program (inputs high or low-active)
12
IN3
Input Channel 3
13
IN4
Input Channel 4
14
OUT3
Power Output Channel 3
15
OUT4
Power Output Channel 4
16
OUT11
Power Output Channel 11
17
OUT12
Power Output Channel 12
18
GND
Ground
19
GND
Ground
20
OUT13
Power Output Channel 13
21
OUT14
Power Output Channel 14
22
OUT5
Power Output Channel 5
23
OUT6
Power Output Channel 6
24
IN9
Input Channel 9
25
IN10
Input Channel 10
26
FAULT
General Fault Flag
27
SO
Serial Data Output
28
SCLK
Serial Clock
29
SI
Serial Data Input
30
IN11
Input Channel 11
31
IN12
Input Channel 12
32
OUT7
Power Output Channel 7
33
OUT8
Power Output Channel 8
34
OUT15
Power Output Channel 15
35
OUT16
Power Output Channel 16
36
GND
Ground
Heat Slug internally connected to ground pins
Data Sheet
8
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Maximum Ratings and Operating Conditions
4
Maximum Ratings and Operating Conditions
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Max.
VS
VDS
-0.3
7
V
–
–
45
V
–
Voltages
4.1.1
Supply voltage
4.1.2
Continuous Drain Source Voltage
(OUT1 to OUT16)
4.1.3
Input Voltage, All Inputs and Data Lines
VIN
-0.3
7
V
–
4.1.4
Output current per Channel
(see Chapter 5)
ID(lim)
–
ID(lim) min
A
–
4.1.5
Output current per Channel
(All 16 Channels ON; Mounted on PCB)2)
–
0.3
A
–
0.5
A
TA = 25 °C
TA = 25 °C
4.1.6
Output current
(Max. total current of all channels on; Heat
Sink required)
ID 1-8
ID 9-16
IDmax
–
14
A
–
VESD
–
2000
V
HBM3)
Currents
ESD Susceptibility
4.1.7
Electrostatic Discharge Voltage
1) Not subject to production test, specified by design.
2) Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 °C the output current has to
be calculated using RthJA according mounting conditions.
3) Human Body Model according to EIA/JESD22-A114-E.
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
9
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Maximum Ratings and Operating Conditions
4.2
Pos.
Functional Range
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
-40
–
150
°C
–
-55
–
150
°C
–
–
–
50
mJ
TJ = 25 °C;
ID1-8 = 0.5 A;
ID9-16 = 1 A
–
3.3
–
W
TA = 25 °C
Temperature Range
4.2.1
Operating Temperature Range
4.2.2
Storage Temperature Range
Tj
Tstg
Single Pulse Inductive Energy
4.2.3
Single pulse inductive Energy (internal EAS
clamping)
Power Dissipation
4.2.4
Power Dissipation (mounted on PCB)
Ptot
all Channel
active
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Pos.
Thermal Resistance
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
4.3.1
Junction to Case (die soldered on heat
slug)1)
RthJSp
–
0.5
1
K/W
Pv = 3W
4.3.2
Junction to ambient (see Figure 51)); all
channels active
RthjA
–
12
–
K/W
Pv = 3W
1) Not subject to production test, specified by design.
Data Sheet
10
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Maximum Ratings and Operating Conditions
Dimensions: 76.2 x 114.3 x 1.5 mm³ ; Material: FR4
Thermal Vias: diameter= 0.3 mm; plating 25 µm; 61 pcs.
Metalization accodring: JEDEC 2s2p (JESD 51-7) + (JESD 51-5)
70µm modeled (traces)
1,5 mm
35µm, 90% metalization
35µm, 90% metalization
70µm, 5% metalization
Thermal_Setup.vsd
Figure 5
Data Sheet
Thermal Simulation - PCB set-up
11
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
5
Electrical and Functional Description of Blocks
The TLE6240GP is an 16-fold low-side power switch which provides a serial peripheral interface (SPI) to control
the 16 power DMOS switches, and diagnostic feedback. The power transistors are protected against short to VBB,
overload, overtemperature and against overvoltage by active zener clamp.
The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (SO).
5.1
Power Supply & Reset
RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs
OFF. An internal pull-up structure is provided on chip. In case the RESET Pin is pulled down statically, the device
remains in Stand-by Mode
Electrical Characteristics: Power Supply
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos.
Parameter
Symbol
1)
5.1.1
Supply Voltage
5.1.2
Supply Current
5.1.3
Supply Current in Standby Mode
Limit Values
VS
IS
IS(stdy)
Unit
Conditions
Min.
Typ.
Max.
4.5
–
5.5
V
–
–
5
10
mA
–
–
10
50
µA
(RESET = L)
1) For VS < 4.5 V the power stages are switched according the input signals and data bits or are definitely switched off. This
undervoltage reset gets active at VS = 3 V (typ. value) and is specified by design and not subject to production test.
5.2
Digital Inputs
In this chapter is the electrical behavior of the following Digital Input Pins described:
•
•
•
parallel Input Pin INx
Reset Pin RESET
Program Pin PRG
Electrical Characteristics: Digital Inputs
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos.
Parameter
5.2.1
Input Low Voltage
5.2.2
Input High Voltage
5.2.3
Input Voltage Hysteresis
5.2.4
Input Pull-down/up Current
(IN1 to IN4, IN9 to IN12)
5.2.5
PRG, Reset Pull-up Current
5.2.6
Minimum Reset Duration
(After a reset all parallel inputs are
ORed with the SPI data bits)
Data Sheet
Symbol
Limit Values
VINL
VINH
VINHys
IIN(1..4,9..12)
Min.
Typ.
Max.
-0.3
–
1.0
Unit
Conditions
V
–
2.0
–
–
V
–
50
100
200
mV
–
20
50
100
µA
VIN = 5 V
IIN(PRG,Res) 20
tReset,min 10
50
100
µA
–
–
–
µs
–
12
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
5.3
Power Outputs
Power Transistor Protection Functions1)
Each of the 16 output stages has its own zener clamp, which causes a voltage limitation at the power transistor
when solenoid loads are switched off. The outputs are provided with a current limitation set to a minimum of 1 A
for channels 1 to 8 and 3 A for channels 9 to 16.
In the event of an overload or short to supply, the current is internally limited and the corresponding diagnosis bit
combination is set. If this operation leads to an overtemperature condition, a second protection level will change
the output into a low duty cycle PWM (selective thermal shut-down with restart) to prevent critical chip
temperatures.
Electrical Characteristics: Power Outputs
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos.
Parameter
Symbol
5.3.1
ON Resistance VS = 5 V;
Channel 1-8
RDS(ON)
ON Resistance VS = 5 V;
Channel 10, 11, 14, 15
RDS(ON)
ON Resistance VS = 5 V;
Channel 9, 12, 13, 16
RDS(ON)
5.3.4
Output Clamping Voltage
Channel 1-8
5.3.5
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
1
–
Ω
–
1.7
2.2
Ω
–
0.35
–
Ω
–
0.60
0.70
Ω
–
0.30
–
Ω
–
0.50
0.60
Ω
TJ = 25 °C1)
TJ = 150 °C
TJ = 25 °C1)
TJ = 150 °C
TJ = 25 °C1)
TJ = 150 °C
VDS(AZ)
45
50
60
V
Output OFF
Output Clamping Voltage
Channel 9-16
VDS(AZ)
45
52.5
60
V
Output OFF
5.3.6
Current Limit Channel 1-8
1
1.5
2
A
–
5.3.7
Current Limit Channel 9-16
3
4.5
6
A
–
5.3.8
Output Leakage Current
–
–
10
µA
5.3.9
Turn-On Time
–
6
12
µs
VReset = L
ID = 0.5 A,
5.3.10
Turn-Off Time
ID(lim)
ID(lim)
ID(lkg)
tON
tOFF
–
6
12
µs
resistive load
5.3.2
5.3.3
1) Specified by design and not subject to production test.
1) The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal
operation or permanently.
Data Sheet
13
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
V IN
t
tOFF
tON
V DS
80%
20%
t
Figure 6
Timing
5.3.1
Typical Characteristics
Drain-Source On-Resistance
RDS(ON) = f(Tj); VS = 5 V
RDS(ON) [Ohm]
Typical Drain-Source ON- Resistance
Figure 7
Channel 1 - 8
1,8
1,7
1,6
1,5
1,4
1,3
1,2
1,1
1
0,9
0,8
0,7
0,6
-50
-25
0
25
50
Tj [°C]
75
100
125
150
175
Typical ON Resistance versus Junction-Temperature (Channel 1-8)
Typical Drain-Source ON- Resistance Channel 10,11,14,15
0,65
0,6
RDS(ON) [Ohm]
0,55
0,5
0,45
0,4
0,35
0,3
0,25
0,2
-50
Figure 8
Data Sheet
-25
0
25
50
Tj [°C]
75
100
125
150
175
Typical ON Resistance versus Junction-Temperature (Channel 10, 11, 14, 15)
14
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
Typical Drain-Source ON- Resistance Channel 9,12,13,16
0,55
RDS(ON) [Ohm]
0,5
0,45
0,4
0,35
0,3
0,25
0,2
0,15
-50
Figure 9
-25
0
25
50
Tj [°C]
75
100
125
150
175
Typical ON Resistance versus Junction-Temperature (Channel 9, 12, 13, 16)
Output Clamping Voltage
VDS(AZ) = f(Tj); VS = 5 V
Typical Clamping Voltage
Channel 1-8
54
53
VDS(AZ) [V]
52
51
50
49
48
47
46
-50
Figure 10
Data Sheet
-25
0
25
50
Tj [°C]
75
100
125
150
175
Typical Clamping Voltage versus Junction Temperature (Channel 1-8)
15
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
Typical Clamping Voltage
Channel 9-16
56
55
VDS(AZ) [V]
54
53
52
51
50
49
48
-50
Figure 11
Data Sheet
-25
0
25
50
Tj [°C]
75
100
125
150
175
Typical Clamping Voltage versus Junction Temperature (Channel 9-16)
16
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
5.4
Diagnostic Functions and FAULT-Pin
The device provides diagnosis information about the device and about the load. There are following diagnosis
flags implemented for each channel:
•
•
•
The diagnosis information of the protective functions, such as “over current” and “over temperature”
The open load diagnosis
The short to ground information.
For further details, refer to the Chapter “Control of the device”
FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transition as soon as an
error occurs for any one of the sixteen channels. This fault indication can be used to generate a µC interrupt.
Therefore a ‘diagnosis’ interrupt routine need only be called after this fault indication. This saves processor time
compared to a cyclic reading of the SO information.
As soon as a fault occurs, the fault information is latched into the diagnosis register. A new error will overwrite the
old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal,
all diagnosis bits can be shifted out serially.
Electrical Characteristics: Diagnostic Functions
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Unit
Conditions
Max.
VDS(OL)
Output Pull-down Current
IPD(OL)
Fault Delay Time
td(fault)
Short to Ground Detection Voltage VDS(SHG)
Short to Ground Detection Current ISHG
Overload Detection Threshold
ID(lim) 1-8
ID(lim) 9-16
Overtemperature Shutdown
Tth(sd)
VS - 2.5 VS - 2
VS - 1.3 V
50
90
150
µA
VReset = H
50
100
200
µs
–
5.4.8
Overtemperature Hysteresis1)
5.4.9
FAULT Output Low Voltage
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
Open Load Detection Voltage
VS - 3.3 VS - 2.9 VS - 2.5 V
–
–
-50
-100
-150
µA
VReset = H
1
1.3
2
A
–
3
4
6
A
–
170
–
200
°C
–
–
10
–
K
–
–
–
0.4
V
IfaultL = 1.6 mA
Threshold1)
Thys
VfaultL
1) Specified by design and not subject to production test.
Data Sheet
17
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
5.5
SPI Interface
Electrical Characteristics: SPI Interface
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos.
Parameter
Symbol
Limit Values
5.5.1
Input Pull-down Current (SI, SCLK) IIN(SI,SCLK) 10
5.5.2
Input Pull-up Current (CS)
5.5.3
SO High State Output Voltage
5.5.4
SO Low State Output Voltage
5.5.5
Output Tri-state Leakage Current
5.5.6
Min.
Unit
Conditions
Typ.
Max.
20
50
µA
–
20
50
µA
–
VS - 0.4 –
–
V
–
–
0.4
V
ISOH = 2 mA
ISOL = 2.5 mA
IIN(CS)
VSOH
VSOL
ISOlkg
10
-10
0
10
µA
CS = H;
0 ≤ VSO ≤ VS
Serial Clock Frequency
(depending on SO load)
fSCK
DC
–
5
MHz
–
5.5.7
Serial Clock Period (1/fclk)
200
–
–
ns
–
5.5.8
Serial Clock High Time
50
–
–
ns
–
5.5.9
Serial Clock Low Time
50
–
–
ns
–
5.5.10
Enable Lead Time (falling edge of
CS to rising edge of CLK)
tp(SCK)
tSCKH
tSCKL
tlead
200
–
–
ns
–
5.5.11
Enable Lag Time (falling edge of
CLK to rising edge of CS)
tlag
200
–
–
ns
–
5.5.12
Data Setup Time (required time SI tSU
to falling of CLK)
20
–
–
ns
–
5.5.13
Data Hold Time (falling edge of
CLK to SI)
tH
20
–
–
ns
–
5.5.14
Disable Time (@ CL = 50 pF)1)
tDIS
tdt
–
–
150
ns
–
200
–
–
ns
–
tvalid
–
–
100
ns
–
–
120
ns
–
–
150
ns
CL = 50 pF1)
CL = 100 pF1)
CL = 220 pF1)
2)
5.5.15
Transfer Delay Time
(CS high time between two
accesses)
5.5.16
Data Valid Time
1) This parameter will not be tested but specified by design
2) This time is necessary between two write accesses to control e.g. channel 1 to 8 during the first access and channel 9 to
16 during the second access. To get the correct diagnostic information, the transfer delay time has to be extended to the
maximum fault delay time td(fault)max = 200 µs.
Data Sheet
18
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
CS
0.7VS
tdt
0.2 VS
tlag
tSCKH
tlead
SCLK
0.7VS
0.2VS
tSU
tSCKL
tH
0.7VS
SI
0.2VS
Figure 12
Input Timing Diagram
0.7 VS
CS
SCLK
0.2 VS
tvalid
tDis
SO
0.7 VS
SO
0.2 VS
SO
0.7 VS
0.2 VS
Figure 13
SO Valid Time Waveforms and Enable and Disable Time Waveforms
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE6240GP by means of the CS pin. Whenever the pin
is in a logic low state, data can be transferred from the µC and vice versa.
•
•
CS High to Low Transition:
– diagnostic status information is transferred from the power outputs into the shift register
– serial input data can be clocked in from then on
– SO changes from high impedance state to logic high or low state corresponding to the SO bits
CS Low to High Transition:
– transfer of SI bits from shift register into output buffers
To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition
of CS. When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a
high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE6240GP. The serial input
(SI) accepts data into the input shift register on the falling edge of SCLK while the serial output (SO) shifts
Data Sheet
19
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
diagnostic information out of the shift register on the rising edge of serial clock. It is essential that the SCLK pin is
in a logic low state whenever chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on
the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the
output stages.
The input data consist of 16 bit, made up of one control byte and one data byte. The control byte is used to program
the device, to operate it in a certain mode as well as providing diagnostic information (see Chapter 6.2). The eight
data bits contain the input information for the eight channels, and are high active.
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a
high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin
following the rising edge of SCLK.
Data Sheet
20
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6
Control of the Device
6.1
Output Stage Control
The 16 outputs of the TLE6240GP can be controlled via serial interface. Additionally eight of these 16 channels
can alternatively be controlled in parallel (Channel 1 to 4 and 9 to 12) for PWM applications.
6.1.1
Parallel Control and PRG - Pin
A Boolean operation (either AND or OR) is performed on each of the parallel inputs and respective SPI data bits,
in order to determine the states of the respective outputs. The type of Boolean operation performed is programmed
via the serial interface.
The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins are not connected
(independent of high or low activity) it is guaranteed that the outputs 1 to 4 and 9 to 12 are switched off. The PRG
pin itself is internally pulled up when it is not connected.
PRG - Program pin.
•
•
PRG = High (VS): Parallel inputs Channel 1 to 4 and 9 to 12 are high active
PRG = Low (GND): Parallel inputs Channel 1 to 4 and 9 to 12 are low active
6.1.2
Serial Control of the Outputs: SPI Protocol
6.1.3
Overview
Each output is independently controlled by an output latch and a common reset line, which disables all outputs.
The Serial Input (SI) is read on the falling edge of the serial clock. A logic high input ‘data bit’ turns the respective
output channel ON, a logic low ‘data bit’ turns it OFF.
CS must be low whilst shifting all the serial data into the device. A low-to-high transition of CS transfers the serial
data input bits to the output control buffer.
The 16 channels of the TLE6240GP are divided up into two parts for the control of the outputs (ON, OFF) and the
diagnosis information.
Serial Input (SI) information consists of 16 bit. 8 bit contain the input driver information for channel 1 to 8 or for
channel 9 to 16. The remaining 8 bits are used to program a certain operation mode.
Serial Output (SO) data consists of 16 bit containing the diagnosis information for channels 1 to 8 or channels 9
to 16 with two bits per channel.
Channel 1 to 8:
•
•
•
Control Byte 1: Operation mode and diagnosis select for channels 1 to 8
Data Byte1: ON/OFF information for channel 1 to 8
DIAG_1: Diagnosis data for channels 1 to 8
Channel 9 to 16:
•
•
•
Control Byte 2: Operation mode and diagnosis select for channels 9 to 16
Data Byte2: ON/OFF information for channel 9 to 16
DIAG_2: Diagnosis data for channels 9 to 16
Data Sheet
21
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
To drive all 16 channels and to get the complete diagnosis data of the TLE6240GP a two step access has to be
performed as follows:
CS
SI
SO
CS
Control Byte1
SI
Data Byte1
SO
16 bit Diagnosis
SI command: Control Byte 1 programs the
operation mode of channels 1 to 8.
Data Byte 1 gives the input information (on
or off) for Channel 1 to 8.
SO diagnosis: Diagnosis information of
channel 1 to 8 or 9 to 16, depending on the
SI control word before.
Figure 14
DIAG_1 (Ch. 1 to 8)
First Access
SI
SO
CS
Control Byte2
SI
Data Byte2
SO
16 bit Diagnosis
SI command: Control Byte 2 programs the
operation mode of channels 9 to 16.
Data Byte 2 gives the input information (on
or off) for Channel 9 to 16.
SO diagnosis: Diagnosis information of
channel 1 to 8 or 9 to 16, depending on the
SI control word before.
Data Sheet
Data Byte1
SI command: Control Byte 1 programs the
operation mode of Channels 1 to 8.
Data Byte 1 gives the input information (on
or off) for Channel 1 to 8.
SO diagnosis: 16 bit diagnosis information
(two bit per channel) of channels 1 to 8
CS
Figure 15
Control Byte1
Control Byte2
Data Byte2
DIAG_2 (Ch. 9 to 16)
SI command: Control Byte 2 programs the
operation mode of Channels 9 to 16.
Data Byte 2 gives the input information (on
or off) for Channel 9 to 16.
SO diagnosis: 16 bit diagnosis information
(two bit per channel) of channels 9 to 16
Second Access
22
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6.1.4
Control- and Data Byte
As mentioned above, the serial input information consist of a control byte and a data byte. Via the control byte, the
specific mode of the device is programmable.
Table 1
Control and Data Byte
MSB
LSB
C
C
C
C
C
C
C
C
D
D
D
Control Byte
D
D
D
D
D
Data Byte
Ten specific control words are recognized, having the following functions:
Table 2
No.
Commands
Control Byte Data Byte
Function
Channel 1 to 8
1
LLLL LLLL1)
XXXX XXXX2)
‘Full Diagnosis’ (two bits per channel) performed for channels 1 to 8. No
change to output states.
2
HHLL LLLL
XXXX XXXX
State of the eight parallel inputs and ‘1-bit Diagnosis’ for channel 1 to 8 is
provided.
3
HLHL LLLL
XXXX XXXX
4
LLHH LLLL
DDDDDDDD
5
HHHH LLLL
DDDDDDDD
Echo-function of SPI; SI direct connected to SO.
2)
IN1 … 4 and serial data bits ‘OR’ed. ‘Full Diagnosis’ performed for
channels 1 to 8.
IN1 … 4 and serial data bits ‘AND’ed. ‘Full Diagnosis’ performed for
channels 1 to 8.
Channel 9 to 16
6
LLLL HHHH1) XXXX XXXX
‘Full Diagnosis’ (two bits per channel) performed for channels 9 to 16. No
change to output states.
7
HHLL HHHH
XXXX XXXX
State of the eight parallel inputs and ‘1-bit Diagnosis’ for channel 9 to 16 is
provided.
8
HLHL HHHH
XXXX XXXX
Echo-function of SPI; SI direct connected to SO.
9
LLHH HHHH
DDDDDDDD
IN9 … 12 and serial data bits ‘OR’ed. ‘Full Diagnosis’ performed for
channels 9 to 16.
10
HHHH HHHH DDDDDDDD
IN9 … 12 and serial data bits ‘AND’ed. ‘Full Diagnosis’ performed for
channels 9 to 16.
1) Control Byte: Channel Selection via Bit 0 to 3
Bits 0 to 3 = L, Channels 1 to 8 selected
Bits 0 to 3 = H, Channels 9 to 16 selected
2) Data Byte: ‘X’ means ‘don’t care’, because this data bits will be ignored.
‘D’ represents the data bits, either being H (= ON) or L (= OFF).
Control words beside No. 1- 10
Not specified Control words are not executed (cause no function) and the shift register (SO Data) is reset after the
CS signal (all ‘0’).
Data Sheet
23
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6.1.5
Control Byte - Detailed description
In the following section the different control bytes will be described. X used within the control byte means:
Table 3
Control Byte - Channel Group selection
MSB
Comment
X
X
X
X
L
L
L
L
Command is valid for Channels 1 to 8
X
X
X
X
H
H
H
H
Command is valid for Channels 9 to 16
Control Byte
The following Control Byte descriptions are referring to the Overview Table 2.
6.1.5.1
Control Byte No.1 and 6
Table 4
Control Byte No. 1 to 6
MSB
Comment
L
L
L
L
X
X
X
Diagnosis only
X
Control Byte
By clocking in this control byte, it is possible to get pure diagnostic information (two bits per channel) in accordance
with Figure 21. The data bits are ignored, so that the state of the outputs are not influenced. This command is only
active once unless the next control command is again “Diagnosis only”. Diagnostic information can be read out at
any time with no change of the switching conditions.
CS
SI
L L L L
L L L L
X X X X
X X X X
SO
H H H H
H H H H
H H H H
H H H H
SI command: Diagnosis only for channels 1 to 8. No change of
the output states
SO diagnosis: No fault, normal function of channels 1 to 8 or 9 to
16 depending on previous SI command
CS
SI
L L L L
SO
H H H H
X X X X
X X X X
DIAG_1
SI command: Diagnosis only for channels 9 to 16. No change of
the output states ⇒ DIAG_2 provided during next chip select cycle
SO diagnosis: 2 bit diagnosis performed for channels 1 to 8
Figure 16
Data Sheet
Example for two Consecutive Chip Select Cycles
24
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6.1.5.2
Control Byte No. 2 and 7
Table 5
Control Byte No. 2 and 7
MSB
Comment
H
H
L
L
X
X
X
Reading back of the eight inputs and ‘1-bit
Diagnosis’ provided
X
Control Byte
If the TLE6240GP is used as bare die in a hybrid application, it is necessary to know if proper connections exist
between the µC-port and parallel inputs. By entering ‘HHLL’ as the control word, the first eight bits of the SO give
the state of the parallel inputs, depending on the µC signals. By comparing the IN-bits with the corresponding
µC-port signal, the necessary connection between the µC and the TLE6240GP can be verified - i.e. ‘read back of
the inputs’.
The second 8-bits fed out at the serial output contains ‘1-bit’ fault information of the outputs (H = no fault, L = fault).
In the expression given below for the output byte, ‘FX’ is the fault bit for channel X.
Table 6
Serial Output
MSB
IN12
LSB
IN11
IN10
IN9
IN4
IN3
IN2
IN1
FX
FX
Parallel Input Signals
FX
FX
FX
FX
FX
FX
Fault Bits Channel 1 to 8 or 9 to 16
CS
SI
H H L L
L L L L
X X X X
X X X X
SO
H H H H
H H H H
H H H H
H H H H
SI command: No change of the output states; reading back of
the 8 inputs and 1bit diagnosis for channels 1 to 8
SO diagnosis: No fault, normal function of channels 1 to 8 or 9 to
16 depending on previous SI command
CS
SI
H H L L
SO
H H H H
X X X X
X X X X
State of 8 par. inputs 1bit diagnosis Ch.1..8
SI command: No change of the output states; reading back of
the 8 inputs and 1bit diagnosis for channels 9 to 16 provided
during next chip select cycle
SO diagnosis: State of eight parallel inputs and 1 bit diagnosis
performed for channels 1 to 8
Figure 17
Data Sheet
Example for two Consecutive Chip Select Cycles
25
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6.1.5.3
Control Byte No. 3 and 8
Table 7
Control Byte No. 3 and 8
MSB
Comment
H
L
H
L
X
X
X
X
Echo-function of SPI
Control Byte
To check the proper function of the serial interface the TLE6240GP provides a “SPI Echo Function”. By entering
HLHL as control word, SI and SO are connected during the next CS period. By comparing the bits clocked in with
the serial output bits, the proper function of the SPI interface can be verified. This internal loop is only closed
once (for one CS period). The “Echo Function” does not cause any internal processing of data and after the next
CS signal the SO data is ‘0’ (all registers reset).
CS
CS
SI
H L H L
L L L L
X X X X
X X X X
SO
H H H H
H H H H
H H H H
H H H H
SI command: No change of the output states; Echo function of
SPI
SO diagnosis: No fault, normal function of channels 1 to 8 or 9 to
16 depending on previous SI command
Figure 18
Echo-function of SPI
6.1.5.4
Control Byte No. 4 and 9
Table 8
Control Byte No. 4 and 9
MSB
L
SI
SI and SO int. connected
SO
Echo-function of SPI, i.e. SI
directly connected to SO.
SI information will not be
accepted during this cycle.
Comment
L
H
H
X
X
X
X
OR operation, and ‘full diagnosis’
Control Byte
With LLHH LLLL as the control word, each of the input signals IN1 to IN4 are ‘OR’ed with the corresponding SI
data bits.
With LLHH HHHH as the control word, each of the input signals IN9 to IN12 are ‘OR’ed with the corresponding SI
data bits.
Data Sheet
26
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
IN 1...4/9...12
Output
Driver
≥1
Serial Input,
data bits 0...3
Figure 19
OR Operation between IN and Serial Input
This OR operation enables the serial interface to switch the channel ON, even though the corresponding parallel
input might be in the off state.
SPI Priority for ON-State
Also parallel control of the outputs is possible without an SPI input.
The OR-function is the default Boolean operation if the device restarts after a Reset, or when the supply voltage
is switched on for the first time.
If the OR operation is programmed it is latched until it is overwritten by the AND operation.
6.1.5.5
Control Byte No. 5 and 10
Table 9
Control Byte No. 5 and 10
MSB
H
Comment
H
H
H
X
X
X
AND operation, and ‘full diagnosis’
X
Control Byte
With HHHH LLLL as the control word, each of the input signals IN1 to IN4 are ‘AND’ed with the corresponding SI
data bits.
With HHHH HHHH as the control word, each of the input signals IN9 to IN12 are ‘AND’ed with the corresponding
SI data bits.
IN 1...4/9...12
&
Output
Driver
Serial Input,
data bits 0...3
Figure 20
Data Sheet
AND Operation between IN and Serial Input
27
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
The AND operation implies that the output can be switched off by the SPI data bit input, even if the corresponding
parallel input is in the ON state.
SPI Priority for OFF-State
This also implies that the serial input data bit can only switch the output channel ON if the corresponding parallel
input is in the ON state.
If the AND operation is programmed it is latched until it is overwritten by the OR operation.
6.1.5.6
Example for an access to channel 1 to 8
LLHH LLLL HLLH LLLH: OR operation between parallel inputs and data bits, i.e channel 1, 5 and 8 will be switched
on.
The next command is now: LHHH LLLL HHHH LLLL
LHHH LLLL as command word has no special meaning and will not be accepted. The output states will not be
changed and the shift register will be reset (at the next CS SO Data all ‘0’).
6.2
Diagnostics
For full diagnosis there are two diagnostic bits per channel configured as shown in Figure 21.
Diagnostic Serial Data OUT SO
15
14
12
11 10
9
Ch.8 Ch.7
Ch.16 Ch.15
Ch.6
Ch.14
Ch.5
Ch.13
HH
HL
LH
LL
Figure 21
•
•
•
•
13
8
7
6- - - - -
Normal function
Overload, Shorted Load or Overtemperature
Open Load
Shorted to Ground
Two Bits per Channel Diagnostic Feedback
Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function.
Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current limitation gets
active, i.e. there is a overload, short to supply or overtemperature condition.
Open load: An open load condition is detected when the drain voltage decreases below 3 V (typ.). LH bit
combination is set.
Short Circuit to GND: If a drain to ground short circuit exists and the drain to ground current exceeds 100 µA,
short to ground is detected and the LL bit combination is set.
A definite distinction between open load and short to ground is specified by design.
The standard way of obtaining diagnostic information is as follows:
Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs to settle. Clock in the
identical serial information once again - during this process the data coming out at SO contains the bit
combinations representing the diagnosis conditions as described in Figure 21.
Reset of the Diagnosis Register
The diagnosis register is reset after reading the diagnosis data (after the falling CS edge). This is done for
channels 1-8 and channels 9-16 separately depending on the previous command.
Data Sheet
28
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6.2.1
Diagnosis Read-out options
By means of the control byte it is possible either to:
1. control the outputs according to the data byte, as well as being able to read the diagnostic information (two bits
per channel)
2. or purely get diagnostic information without changing the state of the outputs
3. or read back the parallel inputs plus a simple diagnosis (one bit per channel)
4. or SPI “Echo Function” as a diagnosis of proper SPI function.
Diagnosis Read-Out Option 1): Serial Control of Outputs
Table 10
OR-operation valid for channels 1 to 8
MSB
L
LSB
L
H
H
L
L
L
L
L
H
L
Control Byte
H
H
L
L
L
Data Byte
SI information: OR-operation valid for channels 1 to 8
SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle
Table 11
OR-operation valid for channels 9 to 16
MSB
L
LSB
L
H
H
H
H
H
H
H
L
H
Control Byte
L
H
L
L
L
Data Byte
SI information: OR-operation valid for channels 9 to 16
SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle
Table 12
AND-operation valid for channels 1 to 8
MSB
H
LSB
H
H
H
L
L
L
L
L
H
L
Control Byte
H
H
L
L
L
Data Byte
SI information: AND-operation valid for channels 1 to 8
SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle
Table 13
AND-operation valid channels 9 to 16
MSB
H
LSB
H
H
H
H
H
H
H
L
Control Byte
H
L
H
H
L
L
L
Data Byte
SI information: AND-operation valid for channels 9 to 16
SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle
Data Sheet
29
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
Diagnosis Read-Out Option 2): Diagnosis only
Table 14
diagnosis - No change of output states
MSB
L
LSB
L
L
L
L
L
L
L
X
X
X
Control Byte
X
X
X
X
X
Data Byte
SI information: Full diagnosis for channels 1 to 8. No change of output states
SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle
Table 15
diagnosis - No change of output states
MSB
L
LSB
L
L
L
H
H
H
H
X
X
X
Control Byte
X
X
X
X
X
Data Byte
SI information: Full diagnosis for channels 9 to 16. No change of output states
SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle
Diagnosis Read-Out Option 3): Read back of parallel inputs plus simple diagnosis
Table 16
No change of output states - read
MSB
H
LSB
H
L
L
L
L
L
L
X
X
X
Control Byte
X
X
X
X
X
Data Byte
SI information: No change of the output states. Read back of parallel inputs and 1 bit diagnosis for channels 1 to 8
SO: State of eight inputs plus 1 bit diagnosis for channel 1 to 8 during next chip select cycle
Table 17
No change of output states - read
MSB
H
LSB
H
L
L
H
H
H
H
X
X
X
Control Byte
X
X
X
X
X
Data Byte
SI information: No change of the output states. Read back of parallel inputs and 1 bit diagnosis for channels 9 to 16
SO: State of eight inputs plus 1 bit diagnosis for channel 9 to 16 during next chip select cycle
Diagnosis Read-Out Option 4): SPI Echo function
Table 18
No change of output states - Echo
MSB
H
LSB
L
H
L
L
L
L
L
X
Control Byte
Data Sheet
X
X
X
X
X
X
X
Data Byte
30
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
SI information: Echo function of SPI interface. No change of the output states
SO: During next chip select cycle the SI bits clocked in appear directly at SO because of an internal connection
for this cycle
Table 19
No change of output states - Echo
MSB
H
LSB
L
H
L
H
H
H
H
X
X
X
X
Control Byte
X
X
X
X
Data Byte
SI information: Echo function of SPI interface. No change of the output states
SO: During next chip select cycle the SI bits clocked in appear directly at SO because of an internal connection
for this cycle
CS
SCLK
SI
C
O
N
T
R
O
L
Byte
7
6
5
4
12
11
10
9
8
7
6
5
4
3
2
1
2
1
MSB
SO
Figure 22
Data Sheet
15
0
LSB
14
13
3
0
Serial Interface
31
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Application Hints
7
Application Hints
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
7.1
Application Circuits
VBat
VS
10K
47nF*
PRG
FAULT
RESET
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SO
SI
CS
CLK
I/O
I/O
SI
SO
CS
CLK
Micro
Controller
Data Sheet
OUTx
TLE6240GP
* Ceramic Capacitor located close to Power Device
Figure 23
OUTx
OUTx
Application Circuit .vsd
Application Circuit
32
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Application Hints
7.2
Engine Management Application
TLE6240GP can be used in combination with Multichannel Switches for relays and general purpose loads.
This arrangement covers the numerous loads to be driven in a modern Engine Management/Powertrain system.
From 28 channels in sum 16 can be controlled direct in parallel for PWM applications.
TLE
6240GP
Application_Hint_EMS_FLEX.vsd
Figure 24
Data Sheet
Engine Management Application
33
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Application Hints
7.3
Daisy Chain Application
Px .1
Px .2
CS
µC
MTSR
CLK
SI
CS
SO
CLK
SI
TL6240GP
16-folds
CS
SO
TL6240GP
16-folds
CLK
SI
SO
TL6240GP
16-folds
MRST
Figure 25
Data Sheet
Daisy Chain Application
34
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Package Outlines
Package Outlines
0.65
0.25 +0.13
6.3
0.1 C
(Mold)
5˚ ±3˚
0.25
2.8
1.3
15.74 ±0.1
(Heatslug)
B
+0.07
-0.02
11 ±0.15 1)
3.5 MAX.
0 +0.1
1.1 ±0.1
3.25 ±0.1
8
Heatslug
0.95 ±0.15
36x
0.25 M A B C
14.2 ±0.3
0.25 B
19
1
18
10
36
5.9 ±0.1
(Metal)
19
3.2 ±0.1
(Metal)
Bottom View
36
Index Marking
1 x 45˚
15.9 ±0.1 1)
(Mold)
1)
A
13.7 -0.2
(Metal)
1
Heatslug
Does not include plastic or metal protrusion of 0.15 max. per side
GPS09181
Figure 26
PG-DSO-36 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
35
Dimensions in mm
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Revision History
9
Version
Revision History
Date
Changes
V3.3, 2010-02-15, up-date
V3.3
2010-02-15
Template up-date
ESD standard up-date
Thermal Resistance parameters up-date
Temperature range for functional range added
Package name modified
Data Sheet
36
Rev.3.3, 2010-02-15
Edition 2010-02-15
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 2010.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
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Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
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of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
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