TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER SLAS091 – DECEMBER 1994 D D D description The TL5632C is a low-power ultra-high-speed video digital-to-analog converter that uses the Advanced Low-Power Schottky (ALS) process. The device has a three channel I/O; the red, the blue, and the green channel. The red, blue, and green signals are referred to collectively as the RGB signal. An internally generated reference is also provided for the standard video output voltage range. Conversion of digital signals to analog signals can be at a sampling rate of dc to 60 MHz. The high conversion rate makes the TL5632C suitable for digital television, computer digital video processing, and high-speed data conversion. FR PACKAGE (TOP VIEW) NC DVCC AVCC GND ROUT GND GOUT GND BOUT GND REF IN D D 8-Bit Resolution Linearity . . . ± 1/2 LSB Maximum Differential Nonlinearity . . . ± 1/2 LSB Maximum Conversion Rate . . . 60 MHz Min Nominal Output Signal Operating Range VCC to VCC – 1 V TTL Digital Input Voltage 5-V Single Power Supply Operation Low Power Consumption . . . 350 mW Typ (MSB) R1 R2 R3 R4 R5 R6 R7 (LSB) R8 (MSB) G1 G2 G3 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 REF OUT AVCC CCOMP DVCC GND CLKR IN CLKG IN CLKB IN B8 (LSB) B7 B6 12 13 14 15 16 17 18 19 20 21 22 G4 G5 G6 G7 (LSB) G8 NC (MSB) B1 B2 B3 B4 B5 D D D NC – No internal connection The TL5632C is characterized for operation from 0°C to 70°C. FUNCTION TABLE STEP DIGITAL INPUT OUTPUT VOLTAGE 0 1 • • • 127 128 129 • • • 254 255 LLLLLLLL LLLLLLLH • • • LHHHHHHH HLLLLLLL HLLLLLLH • • • HHHHHHHL HHHHHHHH 3.980 V 3.984 V • • • 4.488 V 4.492 V 4.996 V • • • 4.996 V 5.000 V AVAILABLE OPTIONS TA 0°C to 70°C PACKAGE TL5632CFR Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER SLAS091 – DECEMBER 1994 functional block diagram ROUT GOUT BOUT AVCC Resistor Network (R) Resistor Network (B) Resistor Network (G) 8 8 Current Switch (R) 8 Current Switch (G) Current Switch (B) CCOMP 8 8 8 REF IN Buffer (R) Buffer (G) 8 8 Master-Slave Register (R) CLKR IN R1 – R8 Buffer (B) 8 Master-Slave Register (G) CLKG IN G1 – G8 Reference Resistor Reference Voltage Master-Slave Register (B) CLKB IN B1 – B8 schematics of outputs EQUIVALENT OF REF OUT EQUIVALENT OF ROUT, GOUT, BOUT AVCC AVCC 1 kΩ REF OUT 240 Ω typical ROUT, GOUT, BOUT 4 kΩ GND 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 REF OUT TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER SLAS091 – DECEMBER 1994 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION B1 – B8 BOUT 18 – 25 I B-channel digital input (B1= MSB) 36 O B-channel analog output CCOMP 31 CLKB IN CLKG IN 26 I B-channel clock input 27 I G-channel clock input CLKR IN G1 – G8 28 I R-channel clock input 9 – 16 I G-Channel digital input (G1= MSB) GND Phase compensation capacitance. A 1 µF capacitor is connected from CCOMP to GND. 29, 35, 37, 39, 41 GOUT 38 NC 17, 44 R1 – R8 Ground. All GND terminals are connected internally; however, all GND terminals should be connected externally to a ground plane or equivalent low impedance ground return. O G-channel analog output No connection internally 1–8 I R-channel digital input (R1= MSB) ROUT 40 O R-channel analog output AVCC DVCC 32, 42 REF IN 34 I Reference voltage input. REF IN accepts the reference voltage on REF OUT. An external reference can also be applied consistent with Note 1. REF OUT 33 O Reference voltage output. An internal voltage divider generates the voltage level (see schematics of outputs, page 2). Analog power supply voltage 30, 43 Digital power supply voltage NOTE 1: VCC – Vref ≤ 1.2 V absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Power supply voltage range, AVCC, DVCC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Digital input voltage range,VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DVCC Analog output voltage range, ROUT, GOUT, BOUT, CCOMP (externally applied) . . . . – 0.3 V to AVCC + 0.3 V Reference input range, REF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVCC + 0.3 V Reference output range, REF OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVCC + 0.3 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2: All voltage values are with respect to GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER SLAS091 – DECEMBER 1994 recommended operating conditions Supply voltage, AVCC, DVCC MIN NOM MAX UNIT 4.75 5 5.25 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 Reference voltage, Vref (see Note 1) 3.8 Setup time, data before CLK↑, tsu1 10 ns 3 ns Pulse duration at high level, tw1 8.3 ns Pulse duration at low level, tw2 8.3 ns Hold time, data after CLK↑, th1 External phase compensation capacitance, CCOMP 1 Operating free-air temperature, TA 0 4 4.2 V V µF 70 °C NOTE 1: VCC – Vref ≤ 1.2 V electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX Resolution IIH IIL High-level input current Low-level input current VCC = 5.25 V, VCC = 5.25 V, VIH = 2.7 V VIH = 2.7 V Iref Vref Reference input current REF IN = 4 V Reference output voltage With internal reference VFS VZS Full-scale analog output voltage VCC = 5 V, VIH = 2 V, Zero-scale analog output voltage VIL = 0.8 V, REF IN = 4 V REF IN = 4 V 8 Bit 20 µA µA – 400 3.8 AVCC – 15 3.9 UNIT 4 10 µA 4.2 V AVCC AVCC+ 15 3.98 4.05 mV V RGB full-scale ratio 0% 4% 8% zo Output impedance 200 240 280 W ICC Supply current 70 90 mA operating characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS EL ED Linearity error End point, Differential linearity error REF IN = 4 V fc tPLH Maximum conversion rate tPHL tr Propagation delay time, high-to-low level TYP† REF IN = 4 V Propagation delay time, low-to-high level Rise time CL ≤ 5 pF‡ 10 5 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ± 0.5 LSB LSB MHz 10 TA = 25°C, 25°C MAX ± 0.5 60 tf Fall time † All typical values are at VCC = 5 V, TA = 25°C. ‡ CL includes probe and jig capacitances. 4 MIN ns ns TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER SLAS091 – DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION tw1 tw2 3V 1.5 V CLKR IN, CLKG IN, CLKB IN (Clock) 0 tsu1 th1 3V R1 – R8, G1 – G8, B1 – B8 (Input Data) 1.5 V 0 tr tf 90% 50% 10% 90% 50% 10% ROUT, GOUT, BOUT (Analog Output) VFS VZS tPLH tPHL TYPICAL CHARACTERISTICS VFS EL 254 4.996 • • • 4.496 VO – Analog Output Voltage – V 4.492 4.488 • • • 3.988 EL 128 ↓ ↑ ↓ ↓ EL 1 ↑ EL 2 11111111 ••• 11111110 10000001 10000000 ••• 01111111 00000010 11111111 ••• 11111110 10000001 10000000 01111111 00000010 00000001 00000000 ••• VZS 00000000 ↑ 3.980 MSB EL 129 ↑ EL 127 ↑ 3.984 LSB ↓ ↓ ↑ ↓ 00000001 VO – Analog Output Voltage – V 5 Digital Input Code Digital Input Code Figure 1. Ideal Conversion Characteristics POST OFFICE BOX 655303 Figure 2. End-Point Linearity Error • DALLAS, TEXAS 75265 5 TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER SLAS091 – DECEMBER 1994 APPLICATION INFORMATION The following design procedures should be used for optimum operation. D D D D D D D D 6 External analog and digital circuitry should be physically separated and shielded as much as possible to reduce system noise. RF breadboarding or RF printed-circuit-board (PCB) techniques should be used throughout the evaluation and production process. Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance and resistance. A ground plane is the better choice for noise reduction. AVCC and DVCC are also separate internally, so they must be connected externally. These external PCB leads should also be made as wide as possible. A ferrite bead or equivalent inductance should be placed in series with AVCC and the decoupling capacitor before the AVCC and DVCC leads are connected together on the board. It is critical that the supply voltage applied to AVCC be as noise free and ripple free as possible. Ripple and noise rejection should be a minimum of 60 dB below the full-scale output range of 1 V peak-to-peak. AVCC to GND and DVCC to GND should be decoupled with 3.3-µF and 0.1-µF capacitors, respectively, as close as possible to the appropriate device terminals. A ceramic chip capacitor is recommended for the 0.1-µF capacitor. The phase compensation capacitor should be connected between CCOMP and GND with as short a lead-in as possible. The no-connection (NC) terminals on the small-outline package should be connected to GND. AVCC, DVCC, and ROUT, GOUT, and BOUT should be shielded from the high-frequency terminals CLKR IN, CLKG IN ,and CLKB IN and the input data terminals. GND traces should be placed on both sides of the ROUT, GOUT, and BOUT traces on the PCB to the following signal processing stage. These output traces should be as short as possible. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER SLAS091 – DECEMBER 1994 APPLICATION INFORMATION DVCC AVCC 3.3 µF CC 3.3 µF CC 8 8 Buffer CC 0.1 µF ROUT GOUT BOUT 0.1 µF 6 R5 TL5632C 7 R7 8 R8(LSB) 9 G1(MSB) G3 G4 G2 11 0.1 µF 1 µF 0.1 µF CLKR IN 28 CLKG IN 27 R6 10 GND REF IN GND BOUT GND GOUT R4 CLKB IN 26 (LSB)B8 25 B7 24 B6 23 B5 5 R3 B3 B4 4 B1 (MSB) B2 3 NC 8 Buffer R2 G5 8 0.1 µF REF OUT 33 AVCC 32 CCOMP 31 DVCC 30 GND 29 R1(MSB) G8 (LSB) 2 G6 G7 1 GND ROUT NC DVCC AVCC 44 43 42 41 40 39 38 37 36 35 34 3 12 13 14 15 16 17 18 19 20 21 22 8 8 Buffer 3 Buffer NOTES: A. Buffers are SN74AS244 or equivalent. B. 0.1 µF capacitors should be placed as close to the device terminals as possible. C. The coupling capacitor (CC) value is application specific and selectable by the user. Figure 3. Typical Bypass, Buffer, and Output Configuration POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER SLAS091 – DECEMBER 1994 MECHANICAL DATA FR/S-PQFP-G44 PLASTIC QUAD FLATPACK 33 23 22 34 0,80 TYP 0,40 0,20 12 44 1 0,20 0,10 11 8,00 TYP 10,20 SQ 9,80 12,80 SQ 12,00 0,10 MIN Seating Plane 0°–10° 0,80 0,30 2,25 MAX 0,10 4040159/A–10/93 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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